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Internet Message Format  |  1992-12-14  |  876 b 
  1. Xref: sparky comp.lsi.cad:1210 comp.arch:11640
  2. Path: sparky!uunet!think.com!paperboy.osf.org!hsdndev!dartvax!coos.dartmouth.edu!pichet
  3. From: pichet@coos.dartmouth.edu (Pichet Chintrakulchai)
  4. Newsgroups: comp.lsi.cad,comp.arch
  5. Subject: Why no tri-state outputs in FPGA cells?
  6. Message-ID: <1992Dec14.221541.25270@dartvax.dartmouth.edu>
  7. Date: 14 Dec 92 22:15:41 GMT
  8. Sender: news@dartvax.dartmouth.edu (The News Manager)
  9. Organization: Dartmouth College, Hanover, NH
  10. Lines: 10
  11. Originator: pichet@coos.dartmouth.edu
  12.  
  13. Hello,
  14.  
  15. I've been working on a project designing a processor with FPGA's.  One severe
  16. limitation I found is that their cells do not have tri-state outputs and thus
  17. forcing me to use MUXes on buses consuming a lot of the resources.
  18.  
  19. Does anybody have any idea why they didn't make these cell outputs tri-state?
  20.  
  21. Thanks.
  22. Pichet Chintrakulchai        (pichet@dartmouth.edu)
  23.