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- Path: sparky!uunet!elroy.jpl.nasa.gov!decwrl!pa.dec.com!mayo
- From: mayo@pa.dec.com (Bob Mayo)
- Newsgroups: comp.lsi.cad
- Subject: Re: Magic transistor netlists
- Date: 12 Dec 1992 01:19:31 GMT
- Organization: DEC Western Research Lab
- Lines: 12
- Distribution: inet
- Message-ID: <1gben3INNal2@usenet.pa.dec.com>
- References: <1992Dec11.120248.425@gmd.de>
- NNTP-Posting-Host: mayo.pa.dec.com
- Keywords: magic,spice,netlists
-
- In article <1992Dec11.120248.425@gmd.de> huebner@eissn5.gmd.de writes:
- >Hi netters,
- >Does anybody know what the next line produced by magic means???
- >Ok, I know it's a line of a transistor netlist. But where are
- >the source gate drain and bulk nodes?
- >
- >p bsp.ch.2_0/I10 bsp.row_2_0/aoi21s_0/6_4_86# bsp.row_2_0/fts_0/Vdd 2 29 51 60
-
- See the file ~cad/src/magic/doc/man/sim.5 for a specification of the .sim
- file format.
-
- --Bob
-