NetNews Usenet Archive 1992 #30/NN_1992_30.iso/spool/comp/lang/verilog/481

Text File | 1992-12-21 | 1.2 KB | 29 lines

Newsgroups: comp.lang.verilog
Path: sparky!uunet!spool.mu.edu!uwm.edu!zaphod.mps.ohio-state.edu!cs.utexas.edu!wotan.compaq.com!twisto.eng.hou.compaq.com!tiktok.eng.hou.compaq.com!ehlers
From: [e-mail] (Steve Ehlers)
Subject: Re: execution of always blocks
Message-ID: <[e-mail]>
Sender: [e-mail] (Netnews Account)
Organization: Compaq Computer Corp.
References: <[e-mail]> <[e-mail]>
Date: Fri, 18 Dec 1992 20:01:53 GMT
Lines: 17

In article <[e-mail]> [e-mail] writes:
>[e-mail] (Terry Manley) writes:
>
>> always @(posedge Clk) c = b;
>> always @(posedge Clk) b = a;
>
>If you have to use two always blocks, you could put
>a #0 delay before the procedural assignment that you want
>done last. That will make VerilogXL schedule that event
>for processing at the end of that timestamp.

Which is fine if you only care about which ONE is last.  If you have
three (or more) registers, you'll still have problems.  Using the
non-blocking assignment operator ( <= ) will give you the behavior you want:

 always @(posedge Clk) c <= b;
 always @(posedge Clk) b <= a;