NetNews Usenet Archive 1992 #30/NN_1992_30.iso/spool/comp/lang/verilog/480

Text File | 1992-12-21 | 1.1 KB | 34 lines

Newsgroups: comp.lang.verilog
Path: sparky!uunet!spsgate!mogate!newsgate!usenet
From: [e-mail] (Rajesh Patil)
Subject: Re: execution of always blocks
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Organization: Motorola SPS ASIC, Chandler, AZ
References: <[e-mail]>
Date: Fri, 18 Dec 1992 17:44:51 GMT
Lines: 20

[e-mail] (Terry Manley) writes:

> always @(posedge Clk) c = b;
> always @(posedge Clk) b = a;

Verilog does not guarantee the sequence of execution of
multiple procedural blocks such as the always blocks above.
If you have to use two always blocks, you could put
a #0 delay before the procedural assignment that you want
done last. That will make VerilogXL schedule that event
for processing at the end of that timestamp.

---
Rajesh Patil
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Advanced Product Operations                 [e-mail]
Motorola ASIC
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