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- From: tdbear@dvorak.amd.com (Thomas D. Barrett)
- Newsgroups: comp.arch,comp.arch.storage
- Subject: Re: ?Concurrent DMA possible on smarter PC buses (EISA/MCA/Localbus)
- Keywords: EISA,MCA,Localbus,VESA,PC,IBM,smartIO
- Message-ID: <1992Dec19.163012.25678@dvorak.amd.com>
- Date: 19 Dec 92 16:30:12 GMT
- References: <1992Dec17.153141.3926@urbana.mcd.mot.com> <1992Dec17.191131.17701@twisto.eng.hou.compaq.com> <1gul5nINN7ln@cbl.umd.edu>
- Organization: Advanced Micro Devices, Inc.; Austin, Texas
- Lines: 18
-
- In article <1gul5nINN7ln@cbl.umd.edu> mike@cbl.umd.edu (Michael Santangelo) writes:
- >
- >So this theoretical EISA SCSI controller and this theoretical EISA FDDI
- >controller could both be doing DMA writes to main memory (interleaving their
- >accesses I assume)?
-
- Actually, they could "snarf" (to, eek!, borrow an intel term) each
- other's transfers to main memory I suppose. This concept of single
- transfers being snarfed-up was first seen by me in a Z80 design which
- used a series of POPs and PUSHs to perform a block move in half the
- time.
-
-
- --
- | Tom Barrett (TDBear), Sr. Engineer | tom.barrett@amd.com
- | AMD PCD / Austin, TX 78741 | v:512-462-6856 / f:512-462-5155
- | "No is yes, And we're all free" | CO made a #2 no-no... PU!
- | My views may not be shared by the organization of origin
-