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- From: simonich@croatia.eng.hou.compaq.com (Chris Simonich)
- Subject: Re: ?Concurrent DMA possible on smarter PC buses (EISA/MCA/Localbus)
- Message-ID: <1992Dec17.191131.17701@twisto.eng.hou.compaq.com>
- Keywords: EISA,MCA,Localbus,VESA,PC,IBM,smartIO
- Sender: news@twisto.eng.hou.compaq.com (Netnews Account)
- Organization: Compaq Computer Corp.
- References: <1gntdfINNu7@cbl.umd.edu> <1992Dec16.211712.13142@twisto.eng.hou.compaq.com> <1992Dec17.153141.3926@urbana.mcd.mot.com>
- Date: Thu, 17 Dec 1992 19:11:31 GMT
- Lines: 40
-
- In article <1992Dec17.153141.3926@urbana.mcd.mot.com> dfields@urbana.mcd.mot.com writes:
- >In article <1992Dec16.211712.13142@twisto.eng.hou.compaq.com>, simonich@croatia.eng.hou.compaq.com (Chris Simonich) writes:
- >> In article <1gntdfINNu7@cbl.umd.edu> mike@cbl.umd.edu (Michael Santangelo) writes:
- >>>Can EISA, MicroChannel, or the new VESA LocalBus on PC's allow
- >>multiple controllers plugged into them (say two smart bus mastering
- >>>SCSI disk controllers on one of these buses) xfer data simultaneously
- >>>to main memory (DMA)?
- >>>
- >>Generally, shared bus architectures are shared by time-division multiplexing.
- >>In short, only one device may use the "bus" at a time, so the answer to your
- >>question is No.
- >
- >I read waht he said and wasn't so sure from the example he gave that the
- >question he asked is the one he wanted to ask. To controllers can be doing
- >DMA trnasfers at the same time byspliting the transfers into smaller chunks
- >and doing the "time-division multiplexing" of the bus via an arbitraition
- >scheme.
- >
- >>There was a post about a new I/O architecture from Compaq. This architecture
- >>does allow multiple controllers to perform simultaneously.
- >
- >If the MIOC in Compaq's proposal is implemented with a multi-port interface
- >to main memory then it will. You would loose some on cost of course.
- >--
- >Dave Fields Motorola Computer Group dfields@urbana.mcd.mot.com
- >SVR4: The Winchester Mystery Kernel uiucuxc!udc!dfields
-
- A multi-port interface to memory is not required. If two devices on an IOC
- are performing DMA simultaneously, all that is required is that the IOC
- send the data upstream at a rate equal to that of the total of the devices.
- There is nothing preventing the upstream channel on the IOC from running
- at 100 MHz. Of course, another way to solve the problem would be to use
- additional buffering in the IOC, for example. The point is that from the
- devices point of view it doesn't have to share its channel with anybody at
- any time.
- --
- ======================================================
- Christopher Simonich simonich@twisto.compaq.com
- Compaq Computer Corp. [713] 374-1898
- ======================================================
-