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- Path: sparky!uunet!spool.mu.edu!agate!doc.ic.ac.uk!uknet!mucs!mshute
- From: mshute@cs.man.ac.uk (Malcolm Shute)
- Newsgroups: comp.arch
- Subject: What's the difference between Horizontal and Vertical microcode?
- Message-ID: <7018@m1.cs.man.ac.uk>
- Date: 11 Dec 92 12:49:31 GMT
- Sender: news@cs.man.ac.uk
- Organization: Dept Computer Science, University of Manchester, U.K.
- Lines: 68
-
- Through an email conversation with a computer architect,
- far more learned and experienced than I,
- I discovered that we were talking at cross-purposes.
-
- The distinction between Vertical and Horizontal microcode which I had
- picked up, was not one that he worked with.
-
- This suggests, to me, that either I am completely wrong, or that the distinction
- is not a tightly defined one (hardly surprising, I suppose, when you look at
- other classifying terms in computer architecture...
- anyone for another RISC v CISC war?)
-
- So...
-
- The purpose of this posting is to ask people to respond, preferably by email,
- as to what they understand the distinction to be.
-
- I will undertake to collate the responses, and to summarise to the net.
- In order that I might do this easily, I would appreciate if you would keep
- your responses down to less than 23 lines (an old VDU screenful).
-
- To give you an idea of the sort of thing that I want, here are the two
- definitions which I have so far:
-
- ----------------------------------------------------------------------------
- DEFINITION 1:
-
- HuC: instructions are not atomic: they can be broken down into a number
- of sub-instructions. These are encoded in 'fields' layed out horizontally
- along the instruction op-code.
-
- VuC: instructions are not atomic: they can be broken down into a number
- of sub-instructions. These are listed in a 'microprogram', in a
- structure which ressembles a CASE statement from a high level language
- (with one case block for each macro instruction being defined).
-
- In practice: Most VuC machines have a native instruction set that is
- vertically microcoded into micro instructions, with the micro-instruction
- set horizontally microcoded. The fields of the micro-instruction are
- then supported directly in the hardware. Thus: the *instructions* are
- the things which can be said to be microcoded or not (in this case,
- the native instructions are vertically microded, the microcode instructions
- are horizontally microcoded, and the microcode fields are not microcoded)
- ----------------------------------------------------------------------------
- DEFINITION 2:
-
- VuC: instructions are not atomic: they can be broken down into a number
- of sub-instructions. These are listed in a 'microprogram', in a
- structure which ressembles a CASE statement from a high level language
- (with one case block for each macro instruction being defined).
- Each micro instruction is very tightly encoded, and can be quite narrow.
-
- HuC: instructions are not atomic: they can be broken down into a number
- of sub-instructions. These are listed in a 'microprogram', in a
- structure which ressembles a CASE statement from a high level language
- (with one case block for each macro instruction being defined).
- Each micro instruction is extravagantly wide, to aid the decode operation
- which has to go on in the hardware (as in the 'In practice:' clause of
- definition-1).
-
- In practice: It is the *machine* which is the thing that can be said to be
- microcoded or not. Those machines which *are* microcoded can then be
- categorised as having a wide (HuC) or narrow (VuC) microprogram control
- store.
- ----------------------------------------------------------------------------
- --
-
- Malcolm SHUTE. (The AM Mollusc: v_@_ ) Disclaimer: all
-