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- From: jones@pyrite.cs.uiowa.edu (Douglas W. Jones,201H MLH,3193350740,3193382879)
- Subject: Re: Request for instruction cycle counts
- Sender: news@news.uiowa.edu (News)
- Message-ID: <1992Dec20.234924.16714@news.uiowa.edu>
- Date: Sun, 20 Dec 1992 23:49:24 GMT
- References: <HOLMER.92Dec18174207@rose.eecs.nwu.edu>
- Nntp-Posting-Host: pyrite.cs.uiowa.edu
- Organization: University of Iowa, Iowa City, IA, USA
- Lines: 28
-
- From article <HOLMER.92Dec18174207@rose.eecs.nwu.edu>, by holmer@eecs.nwu.edu (Bruce Holmer):
- >
- > Does someone have a table of instruction cycle
- > counts for a high-end PDP-8? I'd need to know
- > about how many cycles the different addressing
- > modes require and how to calculate the cycle
- > count for the OPR instructions.
-
- There were two different memory cycle times on the PDP-8/E (that was probably
- the highest of the high-end PDP-8 machines): 1200ns and 1400ns.
-
- An instruction fetch was one short cycle.
- Indirect addressing cost one short cycle, unless it was through an
- autoindex register, in which case you pay for a long cycle.
- Operand fetch for AND and TAD cost one long cycle.
- Operand fetch/increment/store for ISZ cost one long cycle.
- Operand store for DCA and JMS cost one long cycle.
- JMP cost nothing other than the instruction fetch and indirect cycles.
- IOT to omnibus peripherals cost nothing beyond the instruction fetch cycle.
- OPR for non EAE instructions cost nothing beyond the instruction fetch cycle.
-
- These figures are for the standard PDP-8 memory, and must be adjusted if
- you want to talk about the various strange things that happened when they
- abandoned core, particularly, it should be noted that the ROM technology
- of the mid 1970's was a bit on the slow side.
-
- Doug Jones
- jones@cs.uiowa.edu
-