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- Newsgroups: comp.sys.mac.hardware
- Path: sparky!uunet!cs.utexas.edu!uwm.edu!rpi!psinntp!psinntp!newstand.syr.edu!rodan.acs.syr.edu!isr
- From: isr@rodan.acs.syr.edu (Michael S. Schechter - ISR group account)
- Subject: Re: Re: Lifetime of 25MHz IIsi (was: 25MHz IIsi and my engineering friend)
- Message-ID: <1992Nov18.104115.16778@newstand.syr.edu>
- Organization: Syracuse University, Syracuse, NY
- References: <1992Nov16.181708.22881@news.uni-stuttgart.de> <71610001@hpl-otis.hpl.hp.com>
- Date: Wed, 18 Nov 92 10:41:15 EST
- Lines: 12
-
- In article <71610001@hpl-otis.hpl.hp.com> blalock@hpl-otis.hpl.hp.com (Travis Blalock) writes:
- >In comp.sys.mac.hardware, isr@rodan.acs.syr.edu (Michael S. Schechter - ISR group account) writes:
- >
- >> they'll be more voltrage drop, and the CPU will draw still more amperage,
- >
- >Ack! Less voltage --> lower current
- >
- >Actually, in the CMOS case, the output capacitances have to be charged to
- >lower voltages when the supply voltage decreases. As a consequence the
- >average current goes down. Unfortunately, the max speed of the logic gate
-
- Some people just don't recognize good fiction... A little too much
-