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Internet Message Format  |  1992-11-20  |  768 b 
  1. Xref: sparky comp.lang.vhdl:540 comp.lang.verilog:440
  2. Path: sparky!uunet!dtix!darwin.sura.net!jvnc.net!badboy.protocol.zycad.com!dominick
  3. From: dominick@protocol.zycad.com (Dom Paniscotti)
  4. Newsgroups: comp.lang.vhdl,comp.lang.verilog
  5. Subject: Wanted: VHDL to Verilog Translator
  6. Keywords: VHDL Verilog translator
  7. Message-ID: <1ejl2bINNlq5@hayaku.protocol.zycad.com>
  8. Date: 20 Nov 92 21:24:27 GMT
  9. Sender: dominick@hayaku.protocol.zycad.com
  10. Reply-To: dominick@protocol.zycad.com
  11. Organization: Protocol, a Division of ZYCAD Corporation
  12. Lines: 6
  13. NNTP-Posting-Host: hayaku.protocol.zycad.com
  14.  
  15.  
  16. Does anyone know where I could find a behavioural VHDL to
  17. Verilog translator?  or possibly a yacc grammar for VHDL? 
  18.  
  19.                 Thanks in advance,
  20.                         Dom
  21.