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Text File  |  1992-11-18  |  742 b   |  28 lines
  1. Newsgroups: comp.cad.cadence
  2. Path: sparky!uunet!noc.near.net!meiko.com!miranda!ianj
  3. From: ianj@meiko.co.uk (Ian Jamison)
  4. Subject: Verilog to Edif conversion.
  5. Message-ID: <1992Nov19.121111.28584@meiko.com>
  6. Followup-To: comp.cad.cadence
  7. Keywords: verilog edif convert
  8. Sender: news@meiko.com
  9. Reply-To: ianj@meiko.co.uk
  10. Organization: Meiko Ltd.
  11. Date: Thu, 19 Nov 1992 12:11:11 GMT
  12. Lines: 14
  13.  
  14. Hi all,
  15.  
  16. I have a gate-level verilog description of a chip and would like
  17. to convert it to an EDIF netlist. I believe that Synopsis could
  18. do this for me but I don't have (or want to have) Synopsis.
  19.  
  20. Anyone got a utility for this, or know where I can get one.
  21.  
  22. Public domain would be nicest, but other info would be appreciated
  23. also.
  24.  
  25. Many thanks,
  26. Ianj.
  27.  
  28.