NetNews Usenet Archive 1992 #16/NN_1992_16.iso/spool/comp/sys/sgi/11470

Internet Message Format | 1992-07-27 | 1.8 KB

Path: sparky!uunet!olivea!sgigate!odin!fido!zola!zuni!tenno.boston.sgi.com!tarolli
From: [e-mail] (Gary Tarolli)
Newsgroups: comp.sys.sgi
Subject: Re: TLB miss cost?
Message-ID: <[e-mail]>
Date: 27 Jul 92 19:19:28 GMT
References: <[e-mail]>
Sender: [e-mail] (Net News)
Organization: Silicon Graphics, Inc.
Lines: 25

I believe the first level TLB miss cost is 18-20 cycles.  There also is
such a thing as a second level TLB miss.  It could also be the case that
you are missing the data cache.  First level misses are in the 10-20 cycle
range, second level misses are in the 100-150 cycle ranges, depending
on machine etc.

If the problem is TLB faults and the TLB replacement algorithm is deterministic,
I would think that the performance would be same all the time regardless of
position in memory.  On the other hand, if the data was
moved around in memory, some pages might end up conflicting in the data
cache where they hadn't before, resulting in different number of cache misses
and therefore performance.

There's also the icache, I've been noticing some peculiar things regarding
what I believe to be icache misses.  Sometimes a benchmark pgm runs slower
than I expect.  Just copying it to another file can temporarily make it run
fast.  Just waiting a few hours or days also makes it run faster or slower.
I believe the problem is the mapping of virtual pages to physical pages, and
therefore to the icache.  If indeed this is the problem, then the dcache is
probably affected also.
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