NetNews Usenet Archive 1992 #16/NN_1992_16.iso/spool/comp/sys/intel/1378

Internet Message Format | 1992-07-30 | 2.6 KB

Path: sparky!uunet!mcsun!Germany.EU.net!gmdtub!bigfoot!tmh
From: [e-mail] (Thomas Hoberg)
Newsgroups: comp.sys.intel
Subject: Intel Micro 2000 (was:Re: "586" rumours?)
Message-ID: <[e-mail]>
Date: 31 Jul 92 03:15:29 GMT
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Organization: GMD-FIRST, Berlin
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In-reply-to: [e-mail]'s message of 30 Jul 92 16:06:56 GMT

I remember reading something in BYTE some years ago about Intels
Project 2000 (The article was called "A talk with Intel", I believe.
The baseline was, that a chip for the year 2000 would include more
than one processor and big caches. When you look at todays
workstation, you'll find a CPU+FPU(+Cache and so forth) and a graphics
accellerator and a DSP for sound and communications. There are in my
opinion right now two things that limit graphics accellerators
performance and versatility: 1) CPU <-> GX throughput, 2) memory
bandwidth. I see the versatility of graphics accellerators hamperd by
the fact, that they a) either work only on dedicated frame buffer
memory or b) have to do DMA on *physical* addresses. A graphics
accellerator included within the CPU would not have that problem. It
might have a separate set of address/data lines for the frame buffer
and use the normal CPU bus to do graphics operations on offscreen
areas. So including a RISC based graphics accellerator on the same die
as a 386 compatible unit seems like a good idea to me. The same goes
for a DSP unit. While you are add it you might add another 386 unit or
a 860 like floating point pipeline. To make things work, you might
include some kind of (big) local cache, that can be used as a
scratch-pad area for communication between the differnt units. You
might partition that scratch-pad and put a cross-bar like interface
before it, so that memory contention between the diffrent units for
the scratch pad area is low. Remember that once you go off the chip
you loose throughput bad.

I find it hard to believe that people find it so difficult to imagine
what might go into the P5 or it's successors--the path is pretty
clear. Like CPU's integrated that whole bunch of LSI logic that made
up the CPU of a PDP-11/45, tomorrows CPUs should integrate all those
pin monsters that we see in a NextStation or a Sparcstation (to make
an even bigger pin monster--but they are probably working on
interconnect, too).

Comments anyone?
---
Thomas M. Hoberg   | Internet: [e-mail]
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