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- Newsgroups: comp.lang.verilog
- Path: sparky!uunet!Cadence.COM!cadence.com!cranston
- From: cranston@ayn.com (W. Scott Cranston)
- Subject: Re: Getting round verilog hierarchical structure
- In-Reply-To: dank@blacks.jpl.nasa.gov's message of Tue, 28 Jul 1992 00:14:59 GMT
- Message-ID: <CRANSTON.92Jul29102024@ayn.com>
- Sender: usenet@Cadence.COM (Usenet News)
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- Organization: Cadence Design Systems, Lowell MA, United States of America
- References: <Bs23x4.330@brunel.ac.uk> <dank.712282499@blacks.jpl.nasa.gov>
- Date: Fri, 17 Jul 1992 02:36:24 GMT
- Lines: 61
-
- In article <dank.712282499@blacks.jpl.nasa.gov> dank@blacks.jpl.nasa.gov (Dan Kegel) writes:
-
- > Chijioke.Anyanwu@brunel.ac.uk (Chijioke D Anyanwu) writes:
- > >Modules in Verilog are organised in a hierarchical structure which,
- > >presumably, is in keeping in line with standard programming practice.
- > >However, I've come up against situations when this rigid structure has
- > >been a problem.
- > >As a simple example, consider the system below in which A, B and C are
- > >modules (representing hardware blocks) with dedicated links to each other.
- > > [ Diagram of A, B, and C, with a signal running from each to each. ]
- >
- > Why not use an overlying module which invokes A, B, and C,
- > and uses module ports for all communication?
- > Seems more egalitarian than putting any of A, B, or C higher or lower.
- > - Dan Kegel (dank@blacks.jpl.nasa.gov)
-
- Or...remember that one can always use a complete hierarchical path to
- access objects in any other module in the system.
-
- For instance:
-
- module a;
-
- wire m;
-
- xor x1(m, b.t, c.t);
-
- endmodule
-
-
- module b;
- wire w1, t;
-
- nand n1(t, w1, c.t);
-
- endmodule
-
-
- module c;
- wire w1, w2, t;
-
- nor n1(t, w1, w2);
-
- endmodule
-
- I believe this will give you what you want.
-
- Scott Cranston
- Cadence Design Systems
-
-
-
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