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Text File  |  1992-07-28  |  442 b   |  15 lines
  1. Newsgroups: comp.lang.verilog
  2. Path: sparky!uunet!stanford.edu!leland.Stanford.EDU!vasu
  3. From: vasu@leland.Stanford.EDU (Swaminatha Vasudevan)
  4. Subject: Verilog Synthesis
  5. Message-ID: <1992Jul29.030523.28537@leland.Stanford.EDU>
  6. Sender: news@leland.Stanford.EDU (Mr News)
  7. Organization: DSG, Stanford University, CA 94305, USA
  8. Date: Wed, 29 Jul 92 03:05:23 GMT
  9. Lines: 4
  10.  
  11. Who makes ASIC synthesis s/w for Verilog besides Synopsys and Cadence?
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  13. \V
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