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- Path: sparky!uunet!caen!hellgate.utah.edu!cc.usu.edu!ivie
- From: ivie@cc.usu.edu (CP/M lives!)
- Newsgroups: comp.arch
- Subject: Re: Graphics Systems
- Message-ID: <1992Jul30.104250.57660@cc.usu.edu>
- Date: 30 Jul 92 10:42:50 MDT
- References: <1992Jul27.110218.57519@cc.usu.edu> <1392@dms.agames.com>
- Organization: Utah State University
- Lines: 46
-
- In article <1392@dms.agames.com>, albaugh@dms.agames.com (Mike Albaugh) writes:
- > the sort of feel that makes one chuckle at
- > comp.arch postings that talk about "real time" in terms of sub _milli_second
- > interrupt latencies :-)
-
- On the subject of interrupts, it seems to me that it's the _modern_
- processors that have clunky interrupt handling. Consider:
-
- 1965, PDP-8: Processor disables interrupts,
- Saves program counter,
- and jumps to a fixed location to execute code to figure out what
- caused the int.
- The first thing this code has to do is save the accumulator and
- processor status.
- For complex systems, the code to figure out which device
- caused an interrupt can be quite lengthy (it is usually 1/3
- unconditional skips)
- 1970, PDP-11: Processor fetches a vector telling it what caused the int,
- Saves program counter,
- Saves processor status,
- Fetches new processor status (giving it updated IPL),
- Fetches new program counter,
- and jumps to the interrupt service routine.
- The interrupt service routine still has to save registers
- it uses.
- 1978, VAX: Adds a separate stack pointer for processing interrupts so
- that non-interrupt code doesn't have to worry as much about
- how much stack space is used by interrupts (a lot under VMS).
- The interrupt service routine still has to save registers it
- uses.
- 1992, Alpha: See PDP-8, except there is no processor status to save.
- In addition to figuring out what caused the interrupt, the
- code executed must figure out the new interrupt priority
- level; this was simple on the -8, since there are only two
- (enabled or disabled).
-
- I realize that Alpha machines will have instruction caches and the RISC
- guys generally consider instruction fetches to be free, but I don't think
- the interrupt-handling code will generally be in cache; if it is, the
- system is probably spending too much of its time processing interrupts.
- At least the CISC machines generally have the decency to figure out which
- device caused the interrupt and go directly to the service routine without
- a lot of fuss and bother.
-
- Roger Ivie
- ivie@cc.usu.edu
-