NetNews Usenet Archive 1992 #16/NN_1992_16.iso/spool/comp/arch/8433

Text File | 1992-07-29 | 1.7 KB | 34 lines

Newsgroups: comp.arch
Path: sparky!uunet!darwin.sura.net!wupost!gumby!destroyer!ubc-cs!uw-beaver!noah
From: [e-mail] (Rick Noah Zucker)
Subject: Re: Cached DRAM from Mitsubishi
Message-ID: <[e-mail]>
Sender: [e-mail] (USENET News System)
Organization: Computer Science & Engineering, U. of Washington, Seattle
References: <[e-mail]>
Date: Wed, 29 Jul 92 22:42:23 GMT
Lines: 22

In article <[e-mail]> [e-mail] (David Williams) writes:
>   I was flipping through the May issue of Electronic Design, and an
>ad from Mitsubishi caught my eye.  They have a DRAM chip now available
>with built-in cache.  This looks interesting - a 1M by 4 DRAM with a
>built-in 4K by 4 SRAM cache.  Apparently, the chip has an internal bus
>that lets the SRAM cache do a line copy to/from the DRAM portion at
>64 bits.  (16 x 4bit internal bus)  Speed is claimed to be 10ns when a
>cache hit occurs, 70ns in case of a miss (actually, a miss causes a
>280ns DRAM cycle, but the SRAM can start doing stuff again in 70ns while
>the DRAM is busy)

    This is a little unclear, and if you have more detailed
information, please clarify my point.  You say that 70 ns after a cache
miss, the SRAM can start doing stuff, but the DRAM is busy for another
210 ns.  Does this mean that you will get your data in 70 ns, but the
DRAM is busy for another 210 ns because it has to write back the data you
just read out?  Or does it mean that you can initiate another request in
70 ns?  That is, you can make another request to the chip, which will be
satisfied if it is in the cache.

                        Rick Noah Zucker
                        [e-mail]