home *** CD-ROM | disk | FTP | other *** search
- Newsgroups: comp.arch
- Path: sparky!uunet!cs.utexas.edu!torn!utzoo!henry
- From: henry@zoo.toronto.edu (Henry Spencer)
- Subject: Re: CISC Microcode (was Re: RISC Mainframe)
- Message-ID: <Brus8r.2K7@zoo.toronto.edu>
- Date: Thu, 23 Jul 1992 17:50:46 GMT
- References: <13v85hINN2og@rodan.UU.NET> <GLEW.92Jul14234349@pdx007.intel.com> <Brsx7o.G69@zoo.toronto.edu> <1992Jul22.163956.57436@cc.usu.edu>
- Organization: U of Toronto Zoology
- Lines: 23
-
- In article <1992Jul22.163956.57436@cc.usu.edu> ivie@cc.usu.edu (CP/M lives!) writes:
- >> Item 3 can still be
- >> an issue, particularly on old architectures with clunky interrupt handling,
- >
- >What do you mean by "clunky interrupt handling"?
-
- Many, many CPU cycles needed to get into and out of an interrupt, so it's
- impossible to take very many of them or respond quickly to one. You have
- to figure in both hardware and software interrupt overhead; the relevant
- metric is elapsed time between stopping mainline execution and starting
- the interrupt handler *for that specific interrupt*. Time spent figuring
- out deciding who gets to handle this one, or saving and restoring registers
- so he can be invoked safely, is part of the overhead regardless of whether
- it's in software or hardware.
-
- Pretty much the inescapable minimum is two pipeline breaks plus a cycle for
- the "return from interrupt" instruction. There are CPUs that approach this
- for simple cases where the interrupt can be dealt with quickly (they do
- typically incur somewhat more overhead if the interrupt handler wants to
- run for a while and use substantial resources).
- --
- There is nothing wrong with making | Henry Spencer @ U of Toronto Zoology
- mistakes, but... make *new* ones. -D.Sim| henry@zoo.toronto.edu utzoo!henry
-