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-
- CUSTOM CHIPS
- ============
-
- You will notice that the design of the SCRAM 500 centers on four custom
- GAL (Generic Array Logic) chips which do just about everything. Each
- chip packs in the equivalent of 5 - 10 TTL devices, so you might guess
- that a few years ago this card would probably be as big as a dinner
- plate and need a cooling fan. So it is with all computer gear now -
- custom logic is the only way to fly.
-
- In addition to the space savings achieved by custom logic, there are
- other advantages -
-
- lower parts count improves fixability
- increased chip functionality simplifies troubleshooting
- design errors can be rectified in firmware
- new features can be added by chip swapping
- variations such as alternate address mapping possible
-
-
- A functional description of the SCRAM 500 Chips is detailed below.
-
-
- BERTIE
-
- BERTIE controls the AutoConfigure logic of the SCRAM 500. This chip
- describes the RAM and IO sections to the Amiga and sets RAM size and
- base offsets.
-
-
- 1 AB\ Enables AutoBoot code in EPROM to be mounted
-
- 2 SEL\ Chip Select AutoConfig space
-
- 3 RES\ Reset
-
- 4 RW\ Active write cycle
-
- 5 A1 Address 1
-
- 6 A5 Address 5
-
- 7 A4 Address 4
-
- 8 A6 Address 6
-
- 9 A2 Address 2
-
- 10 GND GND
-
- 11 A3 Address 3
-
- 12 D12 Data 12 IO
-
- 13 D13 Data 13 IO
-
- 14 D14 Data 14 IO
-
- 15 IOEN\ Latch IO space (SCSI)
-
- 16 MEMEN\ Latch memory space (Fast RAM)
-
- 17 SIZ1 RAM size option
-
- 18 SIZ0 RAM size option
-
- 19 D15 Data 15 IO
-
- 20 VCC +5 volts
-
-
-
- CYRIL 8
-
- CYRIL is the SCSI AutoBoot controller chip. This chip manages data
- transfers to the 8490V SCSI controller, Block DMA, interrupts, bus
- synchronization and disk LED.
-
-
- 1 DRQ DMA data request from SCSI chip
-
- 2 IRQ Interrupt request from SCSI chip
-
- 3 IOEN\ IO space configured OK
-
- 4 SLCT\ IO space selected
-
- 5 RES\ Reset
-
- 6 RW\ Write enable
-
- 7 UDS\ Upper Data Strobe
-
- 8 A15 Address 15
-
- 9 A14 Address 14
-
- 10 GND GND
-
- 11 A13 Address 13
-
- 12 XRDY Amiga bus signal to insert wait states
-
- 13 INT2\ Amiga bus INT2
-
- 14 DISK\ LED indicator (active low)
-
- 15 ROM\ Select AutoBoot ROM
-
- 16 DATA\ SCSI DMA select
-
- 17 SCSI\ SCSI registers select
-
- 18 IOR\ Read strobe to SCSI chip
-
- 19 IOW\ Write strobe to SCSI chip
-
- 20 VCC +5 volts
-
-
-
- GRISWOLD
-
- GRISWOLD is the master timing controller for the DRAMs. This chip
- generates RAS and CAS, refreshes the RAMs and synchronises with the
- 68000.
-
-
- 1 CLK 14\ Meg clock generated from Amiga bus
-
- 2 CLK 14\ Meg clock
-
- 3 RW\ Write strobe
-
- 4 QC Refresh counter bit 2
-
- 5 QD Refresh counter bit 3
-
- 6 MSEL\ RAM space select
-
- 7 MEMEN\ RAM space configured
-
- 8 UDS\ Upper Data Strobe
-
- 9 LDS\ Lower Data Strobe
-
- 10 GND GND
-
- 11 OE\ Enable output signals
-
- 12 SEL Mux control low selects CAS\
-
- 13 MRAS\ RAM access RAS signal
-
- 14 RFRAS\ RAM refresh RAS signal
-
- 15 CASL\ CAS lower byte
-
- 16 CASU\ CAS upper byte
-
- 17 NC no connect
-
- 18 RDY Ready for 68000 (synchronisation for refresh)
-
- 19 CLR Clear refresh counter
-
- 20 VCC +5 volts
-
-
-
- HUMPHREY
-
- HUMPHREY controls RAM operation including address decoding, bank
- selection, 1M/4M selection and XRDY operation.
-
-
- 1 RFRAS\ RAM refresh RAS cycle
-
- 2 MRAS\ RAM access RAS signal
-
- 3 RDY RAM cycle ready for data transfer
-
- 4 A19 Address 19
-
- 5 A20 Address 20
-
- 6 RW\ Write cycle
-
- 7 A21 Address 21
-
- 8 A22 Address 22
-
- 9 A23 Address 23
-
- 10 GND GND
-
- 11 AS\ Address Strobe
-
- 12 RAS3\ RAS Bank 3
-
- 13 MSEL\ RAM space decode
-
- 14 RAS2\ RAS Bank 2
-
- 15 RAS1\ RAS Bank 1
-
- 16 BRW\ Buffered WE\ signal to RAM array
-
- 17 4MEG\ Low signal selects 1M x 4 devices
-
- 18 XRDY XRDY to Amiga bus to hold off DTACK\
-
- 19 RAS0\ RAS Bank 0
-
- 20 VCC +5 volts
-
-
-
- NJJ
-
-
-