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Text File  |  1993-05-26  |  8KB  |  235 lines
  1. ;*************************************************************
  2. ;SiS ISA-Chipsatz 85C401/402 in Datei SIS401.CFG
  3. ;*************************************************************
  4.  
  5. INDEXPORT=22h
  6. DATENPORT=23h
  7.  
  8. ;*************************************************************
  9. ;Bus-Controller 85C402
  10. ;*************************************************************
  11.  
  12. ;*************************************************************
  13. INDEX=0h;  Bus/Keyboard Clock
  14. ;*************************************************************
  15.  
  16. Bit=76   ;reserved
  17. Bit=510  ;Keyboard Controller KCLK
  18.           000 = 1/6 ATCLK
  19.           001 = 1/5 ATCLK
  20.           010 = 1/4 ATCLK
  21.           011 = 1/3 ATCLK
  22.           100 = 1/5 ATCLK
  23.           101 = 1/4 ATCLK
  24.           110 = 1/3 ATCLK
  25.           111 = 1/2 ATCLK
  26. Bit=4    ;0/1 I/O-Recovery Time
  27.  
  28. Bit=3    ;8 Bit Wait States
  29.          0=4T
  30.          1=5T
  31.  
  32. Bit=2    ;16 Bit Wait States
  33.          0=1T
  34.          1=2T
  35.  
  36. Bit=10   ;Bus Clock Frequency
  37.          00=1/6 ATCLK
  38.          01=1/5 ATCLK
  39.          10=1/4 ATCLK
  40.          11=1/3 ATCLK
  41.  
  42. ;*************************************************************
  43. ;Memory-Controller 85C401
  44. ;*************************************************************
  45.  
  46. ;*************************************************************
  47. INDEX=60h;  Memory Configuration
  48. ;*************************************************************
  49. BIT=76  ;DRAM Speed
  50.            00=Slowest   (50MHz)
  51.            01=Slower    (40MHz)
  52.            10=Faster    (33MHz)
  53.            11=Fastest   (25MHz)
  54. Bit=7   ;Bit 7 also defines the first cache read cycle time of
  55.         ;                   a burst
  56.         0=3-x-x-x-Burst
  57.         1=2-x-x-x-Burst
  58.  
  59. BIT=5   ;DRAM Write CAS Pulse Width
  60.            0=2T
  61.            1=1T
  62.  
  63. BIT=43210 ;DRAM Size Configuration, (I)= Dword-Interleave
  64.           00000= B1:1M   B2:-   B3:-   B4:-    Total:1M
  65.           00001= B1:1M   B2:1M  B3:-   B4:-    Total:2M  (I)
  66.           00010= B1:1M   B2:1M  B3:2M  B4:-    Total:4M
  67.           00011= B1:1M   B2:1M  B3:4M  B4:-    Total:6M
  68.           00100= B1:1M   B2:1M  B3:2M  B4:4M   Total:8M
  69.           00101= B1:1M   B2:1M  B3:4M  B4:4M   Total:10M (I)
  70.           00110= B1:1M   B2:1M  B3:16M B4:-    Total:18M
  71.           00111= B1:2M   B2:-   B3:-   B4:-    Total:2M
  72.           01000= B1:2M   B2:2M  B3:-   B4:-    Total:4M  (I)
  73.           01001= B1:2M   B2:4M  B3:-   B4:-    Total:6M
  74.           01010= B1:2M   B2:2M  B3:4M  B4:-    Total:8M
  75.           01011= B1:2M   B2:2M  B3:4M  B4:4M   Total:12M (I)
  76.           01100= B1:2M   B2:16M B3:-   B4:-    Total:18M
  77.           01101= B1:2M   B2:2M  B3:16M B4:-    Total:20M
  78.           01110= B1:2M   B2:2M  B3:4M  B4:-    Total:24M
  79.           01111= B1:2M   B2:2M  B3:16M B4:-    Total:36M (I)
  80.           10000= B1:4M   B2:-   B3:-   B4:-    Total:4M
  81.           10001= B1:4M   B2:4M  B3:-   B4:-    Total:8M  (I)
  82.           10010= B1:4M   B2:4M  B3:4M  B4:-    Total:12M
  83.           10011= B1:4M   B2:4M  B3:4M  B4:4M   Total:16M (I)
  84.           10100= B1:4M   B2:16M B3:-   B4:-    Total:20M
  85.           10101= B1:4M   B2:4M  B3:16M B4:-    Total:24M
  86.           10110= B1:4M   B2:16M B3:16M B4:-    Total:36M
  87.           10111= B1:4M   B2:4M  B3:16M B4:16M  Total:40M (I)
  88.           11000= B1:8M   B2:-   B3:-   B4:-    Total:8M
  89.           11001= B1:8M   B2:8M  B3:-   B4:-    Total:16M (I)
  90.           11010= B1:8M   B2:8M  B3:8M  B4:-    Total:24M
  91.           11011= B1:8M   B2:8M  B3:8M  B4:8M   Total:32M (I)
  92.           11100= B1:16M  B2:    B3:-   B4:-    Total:16M
  93.           11101= B1:16M  B2:16M B3:-   B4:-    Total:32M (I)
  94.           11110= B1:16M  B2:16M B3:16M B4:-    Total:48M
  95.           11111= B1:16M  B2:16M B3:16M B4:16M  Total:64M (I)
  96.  
  97. ;*************************************************************
  98. INDEX=61h ; Cache Konfiguration
  99. ;*************************************************************
  100. BIT=7   ;0/1 Cache Enable
  101.  
  102. BIT=6   ;Write Back Enable
  103.            0=Disable (Write Through)
  104.            1=Enable (Write Back)
  105.  
  106. BIT=54  ;Cache Size
  107.            00= 32KB
  108.            01= 64KB
  109.            10=128KB
  110.            11=256KB
  111.  
  112. BIT=3   ;0/1 Cache Interleave Enable
  113.  
  114. BIT=2   ;0/1 DRAM Interleave Enable (for 2/4 banks only)
  115.  
  116. BIT=1   ;Cache Write Cycle
  117.            0=3T
  118.            1=2T
  119.  
  120. BIT=0   ;Cache Burst Read Cycle
  121.            0=1T
  122.            1=2T
  123.  
  124. ;*************************************************************
  125. INDEX=62h; Shadow
  126. ;*************************************************************
  127. BIT=7   ;0/1 Shadow RAM Read Enable
  128.  
  129. BIT=6   ;0/1 Shadow RAM Write Protection Enable
  130.  
  131. BIT=5   ;0/1 E8000h-EFFFFh Shadow RAM Enable
  132. BIT=4   ;0/1 E0000h-E7FFFh Shadow RAM Enable
  133. BIT=3   ;0/1 D8000h-DFFFFh Shadow RAM Enable
  134. BIT=2   ;0/1 D0000h-D7FFFh Shadow RAM Enable
  135. BIT=1   ;0/1 C8000h-CFFFFh Shadow RAM Enable
  136. BIT=0   ;0/1 C0000h-C7FFFh Shadow RAM Enable
  137.  
  138. ;*************************************************************
  139. INDEX=63h ; Shadow and Cache
  140. ;*************************************************************
  141. BIT=7   ;System BIOS ROM Size
  142.            0= 64K
  143.            1=128K
  144.  
  145. BIT=6   ;0/1 F0000h-FFFFFh Shadow RAM Cacheable
  146. BIT=5   ;0/1 E8000h-EFFFFh Shadow RAM Cacheable
  147. BIT=4   ;0/1 E0000h-E7FFFh Shadow RAM Cacheable
  148. BIT=3   ;0/1 D8000h-DFFFFh Shadow RAM Cacheable
  149. BIT=2   ;0/1 D0000h-D7FFFh Shadow RAM Cacheable
  150. BIT=1   ;0/1 C8000h-CFFFFh Shadow RAM Cacheable
  151. BIT=0   ;0/1 C0000h-C7FFFh Shadow RAM Cacheable
  152.  
  153. ;*************************************************************
  154. INDEX=64h; Non cacheable 1
  155. ;*************************************************************
  156. BIT=7   ;Allocation of Non-cacheable Area #1
  157.            0=Local DRAM
  158.            1=AT Bus, local DRAM is disabled
  159.  
  160. BIT=654 ;Size of Non-cacheable Area #1 (within 16 MB)
  161.            000=  0KB (disabled)
  162.            001= 64KB
  163.            010=128KB
  164.            011=256KB
  165.            100=512KB
  166.            101=  1MB
  167.            110=  2MB
  168.            111=  4MB
  169.  
  170. BIT=3   ;Allocation of Non-Cacheable Area #2
  171.            0=Local DRAM
  172.            1=AT Bus, local DRAM is disabled
  173.  
  174. BIT=210 ;Size of Non-Cacheable Area #2 (within 64 MB)
  175.            000=  0KB (disabled)
  176.            001= 64KB
  177.            010=128KB
  178.            011=256KB
  179.            100=512KB
  180.            101=  1MB
  181.            110=  2MB
  182.            111=  4MB
  183.  
  184. ;*************************************************************
  185. INDEX=65h; Non Cacheable 2
  186. ;**************************************************************
  187. BIT=76543210    ;A23-A16 of Non-Cacheable Area #1 (within 16 MB)
  188.  
  189.  
  190. ;*************************************************************
  191. INDEX=66h
  192. ;*************************************************************
  193. BIT=76543210    ;A23-A16 of Non-Cacheable Area #2 (within 64 MB)
  194.  
  195.  
  196. ;*************************************************************
  197. INDEX=67h ; Misc 1
  198. ;*************************************************************
  199. BIT=76  ;A25 and A24 of Non-Cacheable Area #2
  200.  
  201. BIT=5   ;0/1 GATE A20 Emulation
  202.  
  203. BIT=4   ;0/1 Fast Reset Emulation
  204.  
  205. BIT=3   ;Fast Reset Latency Control
  206.            0=2µs
  207.            1=6µs
  208.  
  209. BIT=2   ;Slow Refresh Enabled (1:4)
  210.            0=Normal Refresh
  211.            1=Slow Refresh
  212.  
  213. BIT=1   ;De-Turbo ON/OFF
  214.            0=Turbo
  215.            1=De-Turbo
  216.  
  217. BIT=0   ;Turbo Switch Enable
  218.            0=Always Turbo, ignores the status of Turbo switch
  219.            1=Turbo Switch enable
  220.  
  221. ;*************************************************************
  222. INDEX=68h; Misc 2
  223. ;*************************************************************
  224. BIT=7   ;0/1 Super Fast DRAM Access (only 25 MHz, without L2)
  225.  
  226. BIT=6   ;0/1 Slow CPU (DRAM-Timing < 25 MHz)
  227.  
  228. BIT=54  ;Proprietary Chip Select
  229.         00= Port E8h-EFh
  230.         01= Port C8h-CFh
  231.         10= Port 28h-2Fh
  232.         11= Turbo Indicator
  233.  
  234. BIT=43210 ; Reserved (=0)
  235.