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1989-07-20
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XDC - External Device Compiler - and
DDL - Device Definition Language
Contents:
1 Introduction:
2 External Devices
2.1 Combinatorial circuits
2.2 Asynchronous sequential logic systems
2.3 Synchronous sequential logic systems
3 Description of XDC and DDL
3.1 Call of XDC
3.2 Syntax of DDL
3.2.1 Keywords
3.2.2 Syntaxdiagrams
4 Error messages
5 Acknowledgements
1 Introduction:
XDC and DDL allow to define external devices for the register trans-
fer net simulator Sim (V4.0 and higher). With XDC it is possible to
increase the number of devices that can be simulated. It is also pos-
sible to increase the speed of the simulation if parts of a register
transfer net are combined in new, complexer components. New devices
can be combinatorial circuits, asynchronous, and synchronous sequen-
tial logic systems.
2 External Devices
Fundamental it is possible to define any given device. With synchro-
nous sequential logic systems it is necessary to consider the sequen-
tial handling of the devices (see 2.3).
2.1 Combinatorial circuits
Example of an AND device with four inputs:
device x_and;
input in1,in2,in3,in4;
output out;
{
out = in1 & in2 & in3 & in4;
}
2.2 Asynchronous sequential logic systems
Example of an asynchronous automat:
Automat graph:
___ ___
+--- / \ 1/0 / \ ---+
0/0 | | 0 | --------------> | 1 | | 1/0
+--> \___/ \___/ <--+
A |
| |
0/0 | | 0/0
| |
| V
___ ___
+--- / \ 1/1 / \ ---+
1/1 | | 3 | <-------------- | 2 | | 0/0
+--> \___/ \___/ <--+
Definition:
device auto;
input in;
output out;
state s;
{
switch (s) {
case 0:
if (in & 1)
s = 1;
break;
case 1:
if (~in & 1)
s = 2;
break;
case 2:
if (in & 1) {
s = 3;
out = 1;
}
break;
case 3:
if (~in & 1) {
s = 0;
out = 0;
}
break;
}
}
2.3 Synchronous sequential logic systems
With sysnchronous sequential logic systems the value of the input
leads have to be buffered. Due to the forced sequencing of the devices
the input values must not be assigned directly to the outputs. If this
is done, a second register that is connected to the output of the first
will read the new but wrong value.
Example of a positive-edge-triggered D-Register:
device x_reg;
input c,d;
output q;
state s;
{
if (c & 1)
q = s;
else
s = d;
}
3 Description of XDC and DDL
XDC transforms the device definition to C source code which must be
compiled afterwards. Up to now only the AZTEC compiler is tested.
Generally spoken, the compiler must generate code using 16-bit-
integers with LARGE DATE (AZTEC: +D) memory model. For the LATTICE
compiler the file xcomp have to be changed.
3.1 Call of XDC
For the usage of XDC a AZTEC compiler and linker is needed. The direc-
tory, in which XDC lies, must contain the following files:
xcomp, sim.h, sim_msg.h
XDC is started by the following statement:
Execute xcomp <device>
The file, containing the device definition, must have the name
<device>.x. .x must not be given on the call of xcomp.
xcomp generates a file <device>. This file is the new external device.
This means this new device can be used in a VLI. The input and output
lead name have to be given in the sequence of their definition in
<device>.x. The file <device> should be copied to the directory that
contains the simulator.
3.2 Syntax of DDL
3.2.1 Keywords
The DDL uses the following keywords:
BREAK CASE DEFAULT DEVICE ELSE
IF INPUT OUTPUT STATE SWITCH
The keyword can be written in capitals or non-capitals (also mixed).
3.2.2 Syntaxdiagrams
file:
--> device_definition -->
device_definition:
--> DEVICE --> identifier --> ';' --> declaration_list --+
|
+------------------------<---------------------------+
|
+--> '{' --> statement_list --> '}' -->
comment:
--> '/*' ---+----------------+--> '*/' -->
A |
+-- character <--+
declaration_list:
--> input_declaration_list --> output_declaration_list --+
|
+-------------------------<--------------------------+
|
+--> state_declaration_list --+-->
| A
+--------------->-------------+
input_declaration_list:
--+--> input_declaration --+-->
A |
+------------<-----------+
input_declaration:
--> INPUT --> identifier_list --> ';' -->
output_declaration_list:
--+--> output_declaration --+-->
A |
+-------------<-----------+
output_declaration:
--> OUTPUT --> identifier_list --> ';' -->
state_declaration_list:
--+--> state_declaration --+-->
A |
+------------<-----------+
state_declaration:
--> STATE --> identifier_list --> ';' -->
identifier_list:
--+--> identifier --+-->
A |
+------ ',' <-----+
identifier:
--> letter --+------->------+-->
A |
+<-- letter <--+
| |
+---- digit <--+
letter:
--+--> 'A' ---+-->
| . A
| . |
| |
+--> 'Z' -->+
| |
+--> 'a' -->+
| . |
| . |
| |
+--> 'z' -->+
| |
+--> '_' ---+
digit:
--+--> '0' --+-->
| . A
| . |
| |
+--> '9' --+
statement_list:
--+--> statement --+-->
A |
+--------<-------+
statement:
--+--> switch_statement ------>+-->
| A
+--> if_statement ---------->+
| |
+--> assignment_statement -->+
| |
+----------> ';' ------------+
assignment_statement:
--> identifier --> '=' --> expression --> ';' -->
expression:
--+--> expression -------------------------------+-->
| A
+--> '~' --> expression ---------------------->+
| |
+--> constant -------------------------------->+
| |
+--> identifier ------------------------------>+
| |
+--> '(' --> expression --> ')' -------------->+
| |
+--> expression --> operator --> expression ---+
operator:
--+--> '>' --->+-->
| A
+--> '<' --->+
| |
+--> '>=' -->+
| |
+--> '<=' -->+
| |
+--> '==' -->+
| |
+--> '!=' -->+
| |
+--> '&' --->+
| |
+--> '|' --->+
| |
+--> '^' --->+
| |
+--> '+' --->+
| |
+--> '-' --->+
| |
+--> '>>' -->+
| |
+--> '<<' ---+
if_statement:
--> IF --> '(' --> expression --> ')' --> if_else_statement_list--+
|
+-----------------------------<-------------------------------+
|
+--> ELSE --> if_else_statement --+-->
| A
+----------------->---------------+
if_else_statement_list:
--+--> statement -----------------------+-->
| A
+--> '{' --> statement_list --> '}' --+
switch_statement:
--> SWITCH --> '(' --> expression --> ')' --> switch_statement_list -->
switch_statement_list:
--> '{' --+--> case_statment --+---+--> default_statement --+--> '}' -->
A | | A
+----------<---------+ +------------>-----------+
case_statement:
--> CASE --> constant --> ':' --+--> statement_list --+--+
| A |
+---------->----------+ |
|
+--------------------------<-------------------------+
|
+--> BREAK --> ';' --+-->
| A
+--------------------+
default_statement:
--> DEFAULT --> ':' --+--> statement_list --+---+--> BREAK --+-->
| A | A
+---------->----------+ +------>-----+
constant:
--+--> hexadecimal_constant --+-->
| A
+--> decimal_constant-------+
hexadecimal_constant:
+----------<---------+
V |
--+--> '0x' --+---+---+--> digit --+---+-->
| A | A
+--> '0X' --+ +--> 'A' --->+
| . |
| . |
| |
+--> 'F' --->+
| |
+--> 'a' --->+
| . |
| . |
| |
+--> 'f' ----+
decimal_constant:
--+--> '0' -----------------------------+-->
| A
+--> positive_digit --+--> digit --+--+
A |
+------<-----+
positive_digit:
--+--> '1' --+-->
| . A
| . |
| |
+--> '9' --+
4 Error messages
There are three classes of errors:
a) parse errors without description
b) parse errors with description
'=' expected
'(' expected
')' expected
'{' expected
'}' expected
';' expected
':' expected
constant expected
lead name expected
c) semantical errors
BREAK outside of SWITCH
CASE outside of SWITCH
DEFAULT outside of SWITCH
no CASE behind DEFAULT
missing CASE
duplicate CASE
duplicate DEFAULT
already defined lead name
undefined lead
device name differs from file name
no memory
Error should be corrected from the start to the end because there are
often succeeding errors. Succeeding error occur mostly with the clas-
ses a) and b), seldom with c).
5 Acknowledgements
Sim, XDC, and DDL owe to Klaus-Dieter Renner whose idea and design of
a register transfer net simulator and a device definition language
gives the stimulation for my programs, and to Michael Koch for beta-
testing and his suggestions of new features.
