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Path: senator-bedfellow.mit.edu!bloom-beacon.mit.edu!news.kodak.com!news-nysernet-16.sprintlink.net!206.229.87.26!news-east.sprintlink.net!news-peer.sprintlink.net!news-peer-east.sprintlink.net!news.sprintlink.net!rill.news.pipex.net!pipex!sun4nl!surfnet.nl!tudelft.nl!elektron.et.tudelft.nl!delphi.et.tudelft.nl!einstein.et.tudelft.nl!offerman From: offerman@einstein.et.tudelft.nl (Aad Offerman) Newsgroups: comp.sys.ibm.pc.hardware.chips,comp.sys.ibm.pc.hardware.systems,comp.sys.ibm.pc.hardware.misc,comp.ibm.pc.hardware,comp.sys.ibm.pc.misc,comp.sys.intel,comp.answers,news.answers Subject: Personal Computer CHIPLIST 9.9.4 part 4 of 5 Supersedes: <6m1n7o$5m1$1@delphi.et.tudelft.nl> Followup-To: poster Date: 5 Jul 1998 15:12:16 GMT Organization: Delft University of Technology, Dept. of Electrical Engineering Lines: 1849 Approved: news-answers-request@MIT.EDU Expires: 30 December 1998 00:00:00 MET Message-ID: <6no54g$19o$1@delphi.et.tudelft.nl> References: <6no0uc$ule$1@delphi.et.tudelft.nl> Reply-To: offerman@einstein.et.tudelft.nl NNTP-Posting-Host: einstein.et.tudelft.nl Summary: This list contains the various CPUs and NPXs and their features, used in the IBM PC, IBM PC/XT, IBM PC/AT, IBM PS/2 and compatibles, and the differences between them. Keywords: PC, CPU, NPX X-Newsreader: NN version 6.5.0 #2 (NOV) Xref: senator-bedfellow.mit.edu comp.sys.ibm.pc.hardware.chips:233248 comp.sys.ibm.pc.hardware.systems:70870 comp.sys.ibm.pc.hardware.misc:120459 comp.sys.ibm.pc.misc:103248 comp.sys.intel:154418 comp.answers:32006 news.answers:134131 Archive-name: pc-hardware-faq/chiplist/part4 Last-modified: 1998/07/05 Version: 9.9.4 2.42 Intel Pentium CPU 2-issue 5-stage superscalar with 8-stage pipelined FPU (Floating Point Unit). Intel i80486 CPU upward instruction compatible. Multiprocessor support. Upgrading: adding another Intel Pentium CPU. Parity checking at busses. Branch prediction (BTB: Branch Target Buffer). 8 kbyte instruction cache, 8 kbyte data cache (Harvard architecture). Both 2-way set-associative, write-back, no write-allocate. 32 bit internal data bus (CPU - MMU (Memory Management Unit, including cache)) 64 bit external data bus (MMU (Memory Management Unit, including cache) - memory). 32 bit address bus. Package: 296 pin PGA (Pin Grid Array). Label: processor type, clock speed, A80502133: 133 MHz Pentium, stepping and quality, SY022/SSS: SY022: lithography mask number, s-spec (part characteristics): SK, SU, SX, SY, SZ, S: Standard voltage (3.135 - 3.6 V), V (VRE): narrowed voltages 3.4 - 3.6 V, S: Standard timing, M: Minimum Valid MD timing, S: Standard configuration, U: Uniprocessor only, embossed iPP mark: carried by all Pentium CPU's at 90 MHz and faster, most 75 MHz Pentium CPU's carry only the i75 mark, 90 MHz and faster Pentium CPU's with the i75 mark are most likely fake, iCOMP index, serial number, 6044482-0591: number and serial number, country of manufacture, MALAY: Malayasia. In October 1994 Dr. Thomas R. Nicely, Professor of Mathematics at the Lynchburg College, Lynchburg, Virginia (nicely@acavax.lynchburg.edu), reported a bug present in the FPU of all Intel Pentium CPUs. The double precision part of the mantissa is not computed correctly when dividing in some areas of the mantissa space of the divisor. The bug is fixed in Intel Pentium CPUs produced after November 1994. 2.42.1 Intel Pentium P5 CPU 60 MHz (Intel Pentium 510\60 CPU): 5 V, March 1993, 17-13 W, iCOMP 510. 66 MHz (Intel Pentium 567\66 CPU): 5 V, 16-13 W, iCOMP 567, 64.5 SPECint92, 56.9 SPECfp92 (First 66 MHz CPUs had heat troubles and were released as 60 MHz items). Package: 273 pin PGA (Pin Grid Array) (Socket 4: 273 pins, 5 V). Technology: 0.8 micron biCMOS. 3.1E6 transistors. Die size: 18 x 16 mm. ID: step level Ax: DH = 0x05 (family ID), DL = 0x0X (model ID, revision), step level B1: DH = 0x05 (family ID), DL = 0x13 (model ID, revision), step level C1: DH = 0x05 (family ID), DL = 0x15 (model ID, revision), step level D1: DH = 0x05 (family ID), DL = 0x17 (model ID, revision). CPUID: step level Ax: family = 0x5, model = 0, step level Bx: family = 0x5, model = 1. Model 1, revision 7: FDIV bug fixed. 60 MHz: 80500. 60, 66 MHz: 80501. 2.42.2 Intel Pentium P54C CPU Upgrading: Intel Pentium P54M OverDrive (2 CPUs co-operating), Intel Pentium P54CT CPU. 50/75 MHz (Intel Pentium 610\75 CPU) (notebooks, P54T): 3.3 V, August 1994, package: 320 pin TCP, iCOMP 610. 60/90 MHz (Intel Pentium 735\90 CPU): 3.3 V, March 1994, iCOMP 735. 66/100 MHz (Intel Pentium 815\100 CPU): 3.3 V, March 1994, iCOMP 815. Package: 296 pin PGA (Pin Grid Array) (Socket 5: 320 pins, 3.3 V). Technology: 4-layer metal, 0.6 micron biCMOS. 3.1E6 transistors. Die size: 12 x 13 mm. 60/120 MHz (Intel Pentium 1000\120 CPU, Intel Pentium P54CQS CPU): no multi-processor features, 3.3 V, March 1995, iCOMP 1000, step level C2. Package: 296 pin PGA (Pin Grid Array) (Socket 5). Technology: 0.35 micron CMOS. 3.1E6 transistors. Die size: 90 mm2. Intel Pentium P54CS CPU. 66/133 MHz (Intel Pentium 1110\133 CPU): package: 296 pin PGA (Pin Grid Array) (Socket 5), iCOMP 1110. 60/150 MHz: 3.3 V, iCOMP 1195. 66/166 MHz: 3.3 V, iCOMP 1340. 66/200 MHz: 3.3 V. Package: 296 pin PGA (Pin Grid Array) (Socket 7). Technology: 0.35 micron CMOS. 3.1E6 transistors. Die size: 90 mm2. The multiplier can be 1.5, 2, 2.5, or 3. ID: step level A: DH = 0x05 (family ID), DL = 0x2X (model ID, revision), step level B1: DH = 0x05 (family ID), DL = 0x21 (model ID, revision), step level B3: DH = 0x05 (family ID), DL = 0x22 (model ID, revision), step level B5: DH = 0x05 (family ID), DL = 0x24 (model ID, revision), step level C1: DH = 0x05 (family ID), DL = 0x25 (model ID, revision), step level C2 (120 MHz): DH = 0x05 (family ID), DL = 0x25 (model ID, revision), P54CQS, 120 MHz: DH = 0x05 (family ID), DL = 0x25 (model ID, revision), P54LM, 2.9 V, step level Ax: DH = 0x05 (family ID), DL = 0x25 (model ID, revision). CPUID: family = 0x5, model = 0x2. Model 2, revision 5: FDIV bug fixed. 60, 66 MHz: 80501. 50/75, 60/90, 66/100, 60/120, 66/133 MHz: 80502. Embedded Processor Module: EMBMOD133: 66/133 MHz Pentium with 82430HX PCIset. 2.43 Intel OverDrive CPU for Intel Pentium CPU 2.43.1 Intel Pentium P54M CPU Pentium OverDrive processor for Intel Pentium P54C CPU. Technology: CMOS. ID: DH = 0x25 (model ID, family ID), DL = 0x2X (revision). 2.43.2 Intel Pentium OverDrive CPU Pentium OverDrive processor for Intel Pentium P5 CPU. 60/120 and 66/133 MHz (P5T, PODP5V120/133): for 60 and 66 MHz systems, iCOMP 877/978. 3.3 V core (voltage regulator), 5 V I/O. Package: 273 pin PGA (Pin Grid Array) (Socket 4). Technology: 0.8 micron CMOS. 3.1E6 transistors. Pentium P54CT(A) OverDrive processor for Intel Pentium P54C CPU. 50/125 MHz (PODP3V125): for 50/75 MHz systems, iCOMP 1070. 60/150 MHz (PODP3V150): for 60/90 MHz systems, iCOMP 1176. 66/166 MHz (PODP3V166): for 66/100 MHz systems, iCOMP 1308. 3.3 V. Voltages: 3.3 V: 3.135 - 3.600 V. Package: 320 pin PGA (Pin Grid Array) (Socket 5/7). Technology: 0.35 micron CMOS. 3.1E6 transistors. Die size: 90 mm2. 2.44 AMD K5 CPU (K86 series) Intel Pentium CPU compatible. X86 to RISC Operation (ROP) translation. Superscalar: 5-stage, 3 integer pipelines, FP pipeline. Cache: 16 kbyte instruction with predecode unit, 8 kbyte data (Harvard architecture), MESI architecture. Dynamic, block oriented, branch prediction with speculative execution. Package: 296 pin SPGA (Pin Grid Array) (Socket 7). Technology: 3.3 V, 3-layer metal, 0.5 micron CMOS (Fab 25, Texas), 0.35 micron CMOS (first quarter 1996). 2.44.1 AMD 5k86 K5 CPU (K86 series) AMD K5-PR75 CPU (SSA, model 0): 50/75 MHz, March 1996, die size: 177 mm2. AMD K5-PR90 CPU (SSA, model 0): 60/90 MHz. AMD K5-PR100 CPU (SSA, model 0): 66/100 MHz. AMD K5-PR120 CPU (5k86, model 1): 60/90 MHz. AMD K5-PR133 CPU (5k86, model 1): 66/100 MHz. AMD K5-PR150 CPU (5k86, model 2): 60/105 MHz. AMD K5-PR166 CPU (5k86, model 2): 66/116 MHz, March 1997. AMD K5-PR200 CPU (5k86, model 3): 66/133 MHz, never released. No longer manufactured from mid 1997. 3.52 V. Technology: 0.35 micron. 4.3E6 transistors. Die size: 161 mm2. The multiplier can not be changed. 2.44.2 AMD 5k86 SSA/5 CPU (K86 series) Pre-release AMD 5k86 K5 CPU: more internal wait states, incomplete BTB (Branch Target Buffer). Features: VME, I/O Breakpoints, TSC (Time Stamp Counter), Machine Check. 133 MHz: May 1996. Step level: 0x50. 2.45 Cyrix 586 CPU Intel Pentium CPU compatible. Clock doubled/tripled. 16 kbyte unified cache: write-back, 4-way set-associative. Power management: SMM (System Management Mode), hardware suspend, stop-clock, FPU auto-idle. 50 MHz. 100 MHz (announced: third quarter 1995). 120 MHz. Not available anymore due to compatibility problems. 3.3 V, 5 V I/O. Superscalar: 2-issue, 7-stage. Branch prediction, branch target cache. Load/store unit. FPU: 4 64 bit write buffers. Package: 296 pin PGA. Technology: 0.5 micron CMOS (IBM, SGS-Thomson). DIR0 register: 0x30. Cyrix M1 CPU. 2.45.1 Cyrix Cx5x86 CPU Primary cache: 16 kbyte unified, write-back, 4-way set-associative. Power management: SMM (System Management Mode), hardware suspend, stop clock, FPU auto-idle. 50/100, 33/100 (Cyrix Cx5x86-100GP/QP CPU): 3.45 V, July 1995. 40/120 (Cyrix Cx5x86-120GP/QP CPU): 3.45 V. The multiplier can be 2 or 3. In general practice, even faster than Intel's Pentium Pro CPUs (Cyrix optimized for 16 bit code, Intel optimized the Pentium and Pentium Pro CPUs for 32 bit code). Package: 168 pin PGA (Pin Grid Array) (GP), 208 pin QFP (Quad Flat Package) (QP). 1.9E6 transistors. Die size: 144 mm2. 2.46 NexGen Nx586/Nx587 CPU chipset Intel Pentium CPU instruction compatible, no FPU (Floating Poin Unit). RISC (Reduced Instruction Set Computer): RISC86: interpreting (hardware) Intel Pentium CPU instruction set. Runs internally at 4 V; Compatibility with 5 V motherboard provided through the bus interface chip. 16 kbyte instruction cache, 16 kbyte data cache (Harvard architecture). External level 2 cache controller for 256 kbyte or 1 Mbyte. NexGen Nx586 CPU: 60 MHz, 66 MHz. NexGen Nx587 NPX: 60 MHz, 66 MHz. March 1994. NexGen NxVL Vesa Local Bus interface: 60 MHz, 66 Mhz. NexGen NxPCI PCI Bus interface: October 1995. Superscalar: 2 integer units, FP adder (2 cycles), FP multiplier (2 cycles). Branch prediction. NexGen Nx586 CPU: 4 V, 9 W, 3.5E6 transistors, die size: 118 mm2, 0.5 micron CMOS. NexGen Nx587 NPX: 4 V, 1.1 W, 0.7E6 transistors, 0.5 micron CMOS. NexGen NxVL Vesa Local Bus interface: 5 V, 1.0 W, 0.5 micron CMOS. 70 MHz (PR75): September 1994. 80 MHz: September 1994. 90 MHz: September 1994. 100 MHz. 133 MHz: December 1994. Manufactured by IBM. 2.47 Intel Pentium Pro P6 CPU Upward compatible with all previous iapx CPUs (RISC core with X86 translation). Superpipelined superscalar: 3-issue, 12-stage, instruction pool, fetch/decode unit, dispatch/execution unit (2 AGU (Address Generation Unit): 1 load, 1 store, 1 JEU (Jump Execution Unit), 2 IEU (Integer Execution Unit), 1 FEU (Floating Execution Unit)), retire unit. ECC (Error Correcting Code). Fault Analysis & Recovery. Functional Redundancy Checking. Multi-branch prediction, data flow analysis, speculative execution. Level 1 cache: 8 kbyte instruction, 8 kbyte data (Harvard architecture). Level 2 cache: 256/512 kbyte or 1 Mbyte, MESI architecture, custom SRAM. 4 Gbyte cachable main memory. Multi-processor support. 2 or 4 Intel Pentium Pro CPUs can co-operate in a SMP (Symmetric Multi-Processor) environment. The speed-up of a 2-CPU configuration is excellent. The speed-up of a 4-CPU configuration is relatively poor, probably due to too small caches causing too many cache flushes. 60/120 MHz. 66/133 MHz (engineering sample): 256 kbyte level 2 cache, 2.9 V, 3.1 V, 14 W. 60/150 MHz: 256 kbyte level 2 cache, 3.1 V, November 1995, 23.0 W. Technology: 0.6 micron biCMOS, precharged domino logic. 5.5E6 transistors. Die size: 306 mm2. 66/166 MHz: 512 kbyte level 2 cache, November 1995, 27.5 W. 60/180 MHz: 256 kbyte level 2 cache, November 1995, 24.8 W. 66/200 MHz: 256 kbyte level 2 cache, 3.3/3.5 V, November 1995, 27.3 W. 66/200 MHz: 512 kbyte level 2 cache, November 1995, 32.6 W. 3.3 V. Package: 387 pin CPGA (Ceramic Pin Grid Array) (Socket 8). This package contains two dies: the processor and the level 2 cache (dual-cavity package), interconnected by the DIB (Dual Independent Bus). Technology: 0.35 micron CMOS. 5.5E6 transistors. Die size: 195 mm2. ID: DH = 0x06 (model ID, family ID), DL = 0xXX (revision). Pentium Pro and Pentium II processors contain a bug in the FPU (Floating Point Unit) (Dan-0411). The conversion of certain large negative numbers into integers sometimes fails to detect an overflow. Software work-arounds are available. 66/200 MHz: 1 Mbyte level 2 cache, 3.3 V, August 1997, 43 W. 66/200 MHz: 1 Mbyte level 2 cache, 3.2 V (VID (Voltage Identification) to be ignored), August 1997, 40 W. Voltages: 3.1 V: 2.945 - 3.255 V, 3.2 V: 3.1 - 3.3 V, 3.3 V: 3.135 - 3.465 V, 3.5 V: 3.325 - 3.675 V. Technology: 0.35 micron biCMOS. The multiplier can be 2.5, 3, 3.5, or 4. 2.47.1 Intel Pentium Pro P6L CPU Intel Pentium Pro P6 CPU without level 2 cache. 2.48 Intel OverDrive P6 CPU 2.48.1 Intel OverDrive P6T CPU P6 Microarchitecture Core (Pentium II Deschutes). 300 MHz: 23.8 W (announced). 333 MHz: 26.3 W (announced). 2.5 V core, 3.3 V I/O. Voltages: 2.5 V: 2.375 - 2.625 V, 3.3 V: 3.135 - 3.465 V. Package: 387 pin PGA (Pin Grid Array) (Socket 8). Technology: 0.25 micron CMOS. 7.5E6 transistors. Die size: 131 mm2. ID: DH = 0x16 (model ID, family ID), DL = 0xXX (revision). 2.49 IBM 6x86 CPU Cyrix 6x86 CPUs. 2.49.1 IBM 6x86 CPU IBM 266x86-2V2100GB CPU: 50/100 MHz. IBM 266x86-2V2110GB CPU: 55/110 MHz. IBM 266x86-2V2120GB CPU: 60/120 MHz. IBM 266x86-2V2133GB CPU: 66/133 MHz. March 1996. 3.3 V. CPUID: family=0x5, model=0x3, step level=0. IBM 6x86-P120+ CPU (IBM 266x86-2V2P120GE CPU): 50/100 MHz, 3.3 V core, 5 V tolerant I/O. IBM 6x86-P133+ CPU (IBM 266x86-2V2P133GE CPU): 55/110 MHz, 3.3 V core, 5 V tolerant I/O. IBM 6x86-P150+ CPU (IBM 266x86-2V2P150GE CPU): 60/120 MHz, 3.3 V core, 5 V tolerant I/O. IBM 6x86-P150+ CPU (IBM 266x86-2V7P150GE CPU): 60/120 MHz, 3.5 V core, 5 V tolerant I/O. IBM 6x86-P166+ CPU (IBM 266x86-2V2P166GE CPU): 66/133 MHz, 3.3 V core, 5 V tolerant I/O. IBM 6x86-P166+ CPU (IBM 266x86-2V7P166GE CPU): 66/133 MHz, 3.5 V core, 5 V tolerant I/O. IBM 6x86-P200+ CPU (IBM 266x86-2V7P200GE CPU): 75/150 MHz, 3.5 V core, 5 V tolerant I/O. November 1996. Package: 296 pin SPGA (Pin Grid Array) (P54C socket compatible). DIR0 register: 0x31, DIR1 register: 0x1X / 0x2X. 2.49.2 IBM 6x86L CPU Low power version (25 % reduction) of the IBM 6x86 CPU. 2.8 V core, 3.3 V I/O, 5 V tolerant I/O. IBM 6x86L-P120+ CPU: 50/100 MHz. IBM 6x86L-P133+ CPU: 55/100 MHz. IBM 6x86L-P150+ CPU (IBM 266x86L-2VAP150GB CPU): 60/120 MHz. IBM 6x86L-P166+ CPU (IBM 266x86L-2VAP166GB CPU): 66/133 MHz. IBM 6x86L-P200+ CPU (IBM 266x86L-2VAP200GB CPU): 75/150 MHz, technology: 5-layer metal, 0.44 micron IBM CMOS. This CPU uses two power supplies: one supply (2.8 V) is for the core, and the other (3.3 V) is for the I/O interface. Package: 296 pin SPGA (Pin Grid Array) (Socket 7 compatible). DIR0 register: 0x31, DIR1 register: 0x2X. 2.50 Cyrix 6x86 CPU Pentium Pro class CPU (RISC core with X86 translation). In general practice, even faster than Intel's Pentium Pro CPUs (Cyrix optimized for 16 bit code, Intel optimized the Pentium and Pentium Pro CPUs for 32 bit code). However, due to the slow FPU, the performance of floating point intensive applications like the game Quake is low. Due to the first chips' sensitivity for reflections on the busses, Microsoft decided to turn off the primary cache for Window NT 4.0 for pre revision 2.7 chips. Registered Windows NT 4.0 users can obtain a processor replacement from Cyrix, or download a patch. Superpipelined superscalar: 2-issue, 7-stage; 2 integer units, FPU (Floating Point Unit). Features: register renaming, out-of-order execution, data dependancy removal, multi-branch prediction, speculative execution. TLB (Translation Look-aside Buffer): 128-entry L1, 8-entry victim. BTB (Branch Target Buffer): 256-entry, 4-way set-associative, 512-entry branch history table. 16 kbyte unified cache: write-back/write-through, 4-way set-associative, dual-ported, MESI architecture. Pipelined burst-mode reads and writes. 256 byte instruction cache: fully-associative. Multiprocessing support: SLiC/MP, OpenPIC interrupt architecture. Selectable 2x/3x clock multiplier. Power management: SMM (System Management Mode), Suspend Mode, FPU auto-idle. Cyrix 6x86 CPU: 3.3 V (C016) or 3.52 V (C028) core, or voltage switching supporting both, 5 V tolerant I/O, from revision 2.7 less power consumption. 40/80 MHz (Cyrix 6x86-PR90+ CPU): 3.3 V. 50/100 MHz (Cyrix 6x86-PR120+GP CPU): 3.3 V. 55/110 MHz (Cyrix 6x86-PR133+GP CPU): 3.3 V. 60/120 MHz (Cyrix 6x86-PR150+GP CPU): 3.3 or 3.52 V. 66/133 MHz (Cyrix 6x86-PR166+GP CPU): 3.3 or 3.52 V. 75/150 MHz (Cyrix 6x86-PR200+ CPU): 3.52 V. Technology: 0.65 micron CMOS. 3.0E6 transitors. Die size: 210 mm2. Cyrix M1 CPU. Cyrix 6x86L CPU (low power): 2.8 V core, 3.3 V I/O. 50/100 MHz (Cyrix 6x86L-PR120+ CPU). 55/110 MHz (Cyrix 6x86L-PR133+ CPU). 60/120 MHz (Cyrix 6x86L-PR150+ CPU). 66/133 MHz (Cyrix 6x86L-PR166+ CPU). 75/150 MHz (Cyrix 6x86L-PR200+ CPU): technology: 0.44 micron CMOS. Technology: 0.5 micron CMOS. 3.0E6 transistors. Die size: 169 mm2. Package: 296 pin PGA (Pin Grid Array) (Socket 7), 296 pin CPGA (Ceramic Pin Grid Array) (Socket 7). Cyrix M1R CPU. 2.51 NexGen Nx686 CPU Pentium Pro class CPU (RISC core with X86 translation). Cache: 16 kbyte instruction, 32 kbyte data (Harvard architecture). Level 2 cache controller. 180 MHz. Technology: 5-layer metal, 0.35 micron IBM CMOS. 6E6 transistors. 2.52 Intel MMX technology In 1994 Intel started the NSP initiative (Native Signal Processing), but that project failed due to software problems. In 1995 the MMX project was started. MMX (Matrix Math eXtensions, Multi-Media eXtensions): 57 SIMD instructions (Single-Instruction, Multiple-Data) for audio, video, and communication. Multi-media code of applications need to be rewritten and recompiled to take advantage of the MMX instruction set. The MMX technology has been licenced to AMD and Cyrix. The KNI technology (Katmai New Instructions, "MMX2"), adding another 70 instructions for 3D applications, will be available at the first quarter of 1999. Intel MMX WWW server: http://www.mmx.com/ Dedicated multi-media chips: Philips: TriMedia: VLIW (Very Long Instruction Word), Chromatic Research: Mpact: a combined 486 and Mpact processor by SGS-Thomson will be available in the second quarter of 1998, also produced by Toshiba and LG Semicon, Samsung. 4 to 10 times faster than MMX processors, prices around $50. 2.53 Intel Pentium/MMX P55C CPU Two MMX execution units. 16 kbyte instruction cache, 16 kbyte data cache (Harvard architecture). 66/166 MHz: January 1997. 66/200 MHz: January 1997. 66/233 MHz: June 1997. 66/266 MHz (announced: end 1997). The multiplier can be 2, 2.5, 3, or 3.5. 2.8 V, 3.3 V I/O. Both Intel MMX processors and the Cyrix 6x86MX CPU use the FPU for the MMX implementation, resulting in tens of stall cycles while switching between integer, FPU, and MMX code. Embedded Processor Module: EMBMOD166: 66/166 MHz Pentium/MMX with 82430HX PCIset, announced: first quarter 1998. Runs MMX aware multi-media applications about 60 % faster than ordinary Intel Pentium CPU. Package: 296 pin PPGA (Plastic Pin Grid Array) (Socket 7). Technology: 4-layer metal, 0.35 micron CMOS. 4.5E6 transistors. Die size: 141 mm2. 2.54 Intel Mobile Pentium/MMX CPU Two MMX execution units. 66/133 MHz. 50/150 MHz. 66/166 MHz. 66/200 MHz. 2.45 V, 3.3 V I/O. 66/166 MHz: January 1998, 2.9 W. 66/200 MHz: September 1997, 3.4 W. 66/233 MHz: September 1997, 3.9 W. 66/266 MHz: 2.0 V, January 1998, 5.3 W. 4.5E6 transistors. Die size: 95 mm2. 1.8 V, 2.5 V I/O (Voltage Reduction Technology). Tillamook. Package: Mobile Module, 320 pin TCP (Tape Carrier Packaging). Technology: 5 layer metal, 0.25 micron CMOS. 2.55 Intel Pentium/MMX OverDrive CPU Pentium/MMX P54CTB OverDrive processor for Intel Pentium CPUs. 2.8 V core (voltage regulator), 3.3 V I/O. 50/125 MHz: for 75, 100 MHz systems. 60/150 MHz: for 90, 120 MHz systems. 66/166 MHz (BPODPMT66X166): for 75 (to 50/125), 90 (to 60/150), 100, 133 MHz systems. 60/180 MHz (BPODPMT66X180): for 75 (to 50/150), 90, 120, 150 MHz systems, August 1997. 66/200 MHz (BPODPMT66X200): for 100, 133, 166 MHz Socket 7 systems, August 1997. Voltages: 3.3 V: 3.135 - 3.6 V. Package: 320 pin PGA (Pin Grid Array) (Socket 5/7). Technology: 4-layer metal, 0.35 micron CMOS. 4.5E6 transistors. Die size: 141 mm2. 2.56 Intel Pentium II CPU 2.56.1 Intel Pentium II CPU Pentium Pro class CPU with MMX technology. Level 1 cache: 16 kbyte instruction, 16 kbyte data (Harvard architecture), non-blocking. Level 2 cache: 512 kbyte, 4-way set-associative, non-blocking, BSRAM. 512 Mbyte cachable main memory. SMP (Symmetric Multi-Processor) support for 2 CPUs through GTL+ bus. Two MMX execution units. 66/233 MHz: April 1997, 34.8 W, iCOMP 2.0 267, SPECint95 9.38, SPECfp95 7.4, Intel Media Benchmark 364.13. 66/266 MHz: April 1997, 38.2 W, iCOMP 2.0 303, SPECint95 10.7, SPECfp95 8.17, Intel Media Benchmark 412.31. 66/300 MHz: ECC (Error Correcting Code), 43.0 W, iCOMP 2.0 332, SPECint95 11.9, SPECfp95 8.82, Intel Media Benchmark 459.08. 2.8 V core, 3.3 V I/O. Voltages: 2.8 V: 2.73 - 2.9 V, 3.3 V: 3.135 - 3.465 V. From July 1997 the secondary cache is supplied with ECC (Error Correcting Code). Package: 242 pin SEC module (Single Edge Contact) (Slot 1). The SEC module consists of a PCB containing the processor chip and the level 2 cache chips. Compared to the Intel Pentium Pro P6 CPU that combines the processor die and level 2 cache die in a single package (dual-cavity package), the DIB (Dual Independent Bus) is clocked at only half the speed. The clock multiplier can be 3.5, 4, 4.5, 5. Technology: 4 layer metal, 0.35 micron CMOS. 7.5E6 transitors in core. Die size: 203 mm2. Pentium Pro and Pentium II processors contain a bug in the FPU (Floating Point Unit) (Dan-0411). The conversion of certain large negative numbers into integers sometimes fails to detect an overflow. Software work-arounds are available. Klamath. 2.56.2 Intel Pentium II CPU P6 Microarchitecture Core. Dynamic Execution: multiple branch prediction, dataflow analysis, speculative execution. MMX. Level 1 cache: 16 kbyte instruction, 16 kbyte data (Harvard architecture), non-blocking. Level 2 cache: 512 kbyte, 4-way set-associative, non-blocking, BSRAM. 4 Gbyte cachable main memory (512 Mbyte by step level dA0, 333 MHz version). ECC (Error Correcting Code). SMP (Symmetric Multi-Processor) support for 2 CPUs (Nightshade architecture). 66/333 MHz: January 1998, 23.6 W, iCOMP 2.0 366, SPECint95 13.0, SPECfp95 9.55, Intel Media Benchmark 498.79. 2.0 V core, 3.3 V I/O. Voltages: 2.0 V: 1.93 - 2.1 V, 3.3 V: 3.135 - 3.465 V. 100/350 MHz: April 1998, 24.5 W, iCOMP 2.0 386, SPECint95 13.9, SPECfp95 11.20, Intel Media Benchmark 534.61. 100/400 MHz: April 1998, 27.9 W, iCOMP 2.0 440, SPECint95 15.8, SPECfp95 12.40, Intel Media Benchmark 601.10. 100/450 MHz: announced: July 1998. The multiplier can not be changed. 2.0 V core, 3.3 V I/O. Voltages: 2.0 V: 1.9 - 2.1 V, 3.3 V: 3.135 - 3.465 V. ID (333 MHz): step level dA0: family ID 6, model ID 5, revision 0, step level dA1: family ID 6, model ID 5, revision 1. Package: 242 pin SEC module (Single Edge Contact) (Slot 1). Technology: 5 layer metal, 0.25 micron CMOS. 7.5E6 transitors in core. Die size: 130.9 mm2. On-die thermocouple for temperature monitoring. Deschutes. 2.56.3 Intel Pentium Celeron CPU Low-end Intel Pentium II CPU for Basic PC. P6 Microarchitecture Core. Dynamic Execution: multiple branch prediction, dataflow analysis, speculative execution. MMX. Level 1 cache: 16 kbyte instruction, 16 kbyte data (Harvard architecture), non-blocking. Level 2 cache: 0/128 kbyte, 4-way set-associative, non-blocking, BSRAM. No multi-processor support. 66/266 MHz: no level 2 cache, April 1998, 16.7 W, iCOMP 2.0 213, Business Winstone 98 14.7, Intel Media Benchmark 305.36, 3D Winbench 98 437. 66/300 MHz: no level 2 cache, June 1998. 66/333 MHz (announced: fourth quarter 1998). 66/300 MHz (Mendocino): 128 kbyte level 2 cache, announced: third quarter 1998, also in 370 pin Socket. 66/333 MHz (Mendocino): 128 kbyte level 2 cache, announced: fourth quarter 1998, also in 370 pin Socket. The multiplier can not be changed. 2.0 V. Voltages: 2.0 V: 1.9 - 2.1 V. Package: SEPP (Single Edge Processor Package) (Slot 1). Technology: 5 layer metal, 0.25 micron CMOS. 7.5E6 transitors in core. Die size: 130.9 mm2. Covington. 2.56.4 Intel Mobile Pentium II CPU P6 Microarchitecture Core. Dynamic Execution: multiple branch prediction, dataflow analysis, speculative execution. MMX. Level 1 cache: 16 kbyte instruction, 16 kbyte data (Harvard architecture), non-blocking. Level 2 cache: 512 kbyte, 4-way set-associative, non-blocking, BSRAM. 4 Gbyte cachable main memory. ECC (Error Correcting Code). 66/233 MHz: April 1998, 10.6 W. 66/266 MHz: April 1998, 12.1 W. 66/300 MHz: announced: end 1998. 66/333 MHz: announced: begin 1999. 1.7 V. Voltages: 1.7 V: 1.58 - 1.82 V. Package: Mobile Module, Mini Cartridge. Technology: 5 layer metal, 0.25 micron CMOS. 7.5E6 transitors in core. Die size: 130.9 mm2. 2.56.5 Intel Pentium II Xeon CPU P6 Microarchitecture Core. Dynamic Execution: multiple branch prediction, dataflow analysis, speculative execution. MMX. PSE36 addressing mode (part of Intel's Extended Server Memory Architecture): up to 64 Gbyte of addressable main memory. Level 1 cache: 16 kbyte instruction, 16 kbyte data (Harvard architecture), non-blocking. Level 2 cache: 512 kbyte or 1/2 Mbyte, 4-way set-associative, non-blocking, BSRAM. The level 2 cache runs at the same speed as the processor core, like at the Intel Pentium Pro CPU. ECC (Error Correcting Code). Multi-processor support (4-CPU with 450NX chipset, 8-CPU (announced: fourth quarter 1998): Saber architecture, Corollary Profusion chipset). At the introduction, a bug in 4-CPU 450NX chipset based systems was discovered, which delayed the introduction of these systems. Management functions accessible through SMBus: ROM containing type and stepping data, thermal information, additional information can be added by OEM, temperature sensor. 100/400 MHz: 512 kbyte or 1 Mbyte L2 cache, June 1998, 30.8 W. 100/450 MHz (announced: September 1998): 2 Mbyte L2 cache, 38.1 W. 100/500 MHz (announced: begin 1999). 2.0 V, 3.3 V I/O. Package: 330 pin SEC module (Single Edge Contact) (Slot 2). Technology: 5 layer metal, 0.25 micron CMOS. 7.5E6 transitors in core. Die size: 130.9 mm2. Deschutes. 2.56.6 Intel Katmai CPU Intel Pentium II CPU with KNI instruction set (Katmai New Instructions). 100/450 MHz. 100/500 MHz. Announced: begin 1999. Package: Slot 1. Technology: 5 layer metal, 0.25 micron CMOS, later 0.18 micron (second half 1999). Plans for mobile version canceled in May 1998. 2.56.7 Intel announcements Dixon: Mendocino version for low-cost notebooks, 266 MHz, announced: fourth quarter 1998. Dual-processor modules for Slot 2 systems (DP Ready, Camino chipset). Willamette: successor Intel Pentium II CPU series, 600 MHz, 0.18 micron, later 0.13 micron. Coppermine: mobile version of Willamette, 100/450 and 100/500 MHz, AC/DC powering (Geyserville technology), 0.18 micron technology, announced: end 1999. Tanner: Katmai, 100/500 MHz, multi-processor support (4-CPU: Lion32 architecture), Slot 2, announced: first quarter 1999. P7, Merced: 64 bit architecture (IA-64), EPIC (Explicit Parallel Instruction Computing, narrow VLIW (Very Long Instruction Word)), multi-processor support (4-CPU with 460GX chipset: Lion64 architecture), 600 MHz, 133 MHz external bus, Slot M (64/128 bits), announced: mid 2000, 14E6 transistors, die size: 300 mm2, 0.25 micron, later 0.18 micron, 800 MHz, copper, successor (2002): 0.13 micron. 2.57 AMD K6 CPU Pentium Pro class CPU with MMX technology. Based on the NexGen Nx686 CPU design. Intel Pentium/MMX P55C CPU pin compatible. Dual processor support. Optimized for 16 bit code. Superscalar: 6-stage, 7 execution units: load, store, 2 integer, FPU, branch, MMX. Features: X86 to RISC86 instruction translation, instruction predecoding, out-of-order execution, speculative execution, central Instruction Control Unit. Branch prediction: 8192-entry branche history table, 16-entry BTB (Branch Target Buffer), 16-entry return address stack. 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture). Instruction cache: 2-way set-associative, 32 bytes per line, single cycle access. Data cache: write-back, 2-way set-associative, 32 bytes per line, simultanious load and store in single cycle, MESI architecture. Model 6. 66/166 MHz (PR166): 2.9 V core, 3.3 V I/O, April 1997. 60/180 MHz: 2.9 V. 66/200 MHz (PR200): 2.9 V core, 3.3 V I/O, April 1997. 66/233 MHz (PR233): 3.3/3.2 V core, 3.3 V I/O, April 1997. Technology: 5-layer metal, 0.35 micron C4 CMOS. 8.8E6 transistors, from which 3E6 for the cache. Die size: 162 mm2. Model 7. 66/233 MHz: January 1998. 66/266 MHz: January 1998. 66/300 MHz: April 1998. 2.2 V core, 3.3 V I/O. Technology: 0.25 micron CMOS. 8.8E6 transistors, from which 3E6 for the cache. Die size: 68 mm2. Package: 321 pin PGA (Pin Grid Array) (Socket 7). 100/300 MHz. 100/350 MHz (announced: third quarter 1998). 100/400 MHz (announced: fourth quarter 1998). 2.2 V core, 3.3 V I/O. Package: 321 pin PGA (Pin Grid Array) (Socket 7+). 2.57.1 AMD K6-2 CPU 3DNow! technology: 3D multi-media instruction set (21 instructions). Two MMX execution units. Model 8. 66/266 MHz: May 1998. 66/300 MHz: May 1998. 66/333 MHz: May 1998. 100/300 MHz. 100/350 MHz (announced: third quarter 1998): Socket 7+. 100/400 MHz (announced: fourth quarter 1998): Socket 7+. 2.2 V core, 3.3 V I/O. Package: 321 pin CPGA (Ceramic Pin Grid Array) (Socket 7). Technology: 5 layer metal, 0.25 micron CMOS. 9.3E6 transistors. Die size: 68 mm2. K6-3D, Chompers. Model 9: 256 kbyte level 2 cache. 100/350 MHz (announced: fourth quarter 1998). 100/400 MHz (announced: fourth quarter 1998). 2.2 V core, 3.3 V I/O. Technology: 0.25 micron CMOS. 9.3E6 transistors. Die size: 135 mm2. Sharptooth. 2.57.2 AMD announcements K6-3: K6-2 with on-board level 2 cache. K7: announced: begin 1999, Slot A (Intel Slot 1 compatible) or EV6 (DEC Alpha CPU compatible). 2.58 IBM 6x86MX CPU Cyrix 6x86MX CPU. 2.59 Cyrix 6x86MX CPU Pentium Pro class CPU with MMX technology. Intel Pentium/MMX P55C CPU pin compatible. 64 kbyte unified cache: 4-way set-associative, 32 bytes per line. 256 byte instruction line cache: 8-entry, fully-associative, 32 bytes per line. Superscalar: register renaming, out-of-order execution, speculative execution. Branch prediction: 512-entry branch target cache, 4-way set-associative, 1024-entry branch history cache. TLB (Translation Look-aside Buffer): 16-entry L1, direct mapped, dual-ported, 384-entry L2, direct mapped, dual-ported. Optimized for 32 bit code. 66/133 MHz (Cyrix 6x86MX-PR166+ CPU): May 1997. 66/166 MHz (Cyrix 6x86MX-PR200+ CPU). 75/188 MHz (Cyrix 6x86MX-PR233+ CPU). 66/200 MHz. The multiplier can be 2, 2.5, 3, or 3.5. Dual voltage: 2.8 V core, 3.3 V I/O. 83/208 MHz (Cyrix 6x86MX-PR266 CPU): March 1998, 2.9 V core, 3.3 V I/O. 75/225 MHz (Cyrix 6x86MX-PR300 CPU): April 1998, 0.25 micron IBM CMOS. 100/250 MHz (Cyrix 6x86MX-PR333 CPU): announced: third quarter 1998. Package: 296 pin PGA (Pin Grid Array) (P54C socket compatible). Technology: 5-layer metal, 0.35 micron CMOS (IBM and SGS-Thomson). 6E6 transistors. Die size: 194 mm2. M2. 2.59.1 Cyrix announcements Cayenne: announced: 1998, own 3D multi-media instruction set. 2.60 Centaur IDT WinChip C6 CPU Intel Pentium/MMX P55C CPU compatible. Cache: 32 kbyte data, 32 kbyte instruction. 50/150 MHz: 3.3 V, never produced. 60/180 MHz. 66/200 MHz. 75/225 MHz. 3.3 or 3.52 V. Package: 296 pin PGA (Pin Grid Array) (Socket 7). Technology: 0.35 micron CMOS. 5.4E6 transistors. Die size: 88 mm2. 2.60.1 Centaur IDT WinChip C6+ CPU 53 additional "X86" instructions. Announced: second half 1998. 83/266 MHz: 3.3 V. 100/300 MHz: 2.5 V. Technology: 0.35 micron CMOS. 5.8E6 transistors. Die size: 91 mm2. 100/300 MHz. Technology: 0.25 micron CMOS. 5.8E6 transistors. Package: 296 pin PGA (Pin Grid Array) (Socket 7+). 2.60.2 Centaur IDT WinChip-2-3D C6+ CPU WinChip C6+ with 3DNow! technology. 66/266 MHz (announced: second half 1998). 100/300 MHz (announced: second half 1998). Technology: 0.35 micron CMOS. 100/300 MHz (announced: fourth quarter 1998). Technology: 0.25 micron CMOS. Package: 296 pin PGA (Pin Grid Array) (Socket 7+). 2.61 Multi-Media CPU 2.61.1 Cyrix MediaGX CPU The Cyrix MediaGX CPU together with the MediaGX Cx5510 companion chip implements a complete PC system including 64 bit FPM / EDO DRAM controller (maximum 128 Mbyte in 4 banks), ISA and PCI bus, video and audio. Core: superscalar, BTB (Branch Target Buffer), decoupled load/store unit. FPU (Floating Point Unit). Primary cache: 16 kbyte unified, write-back, 4-way set-associative, 1024 lines of 16 bytes. VSA Virtual VGA: supports all VGA and VESA modes, up to 1280 x 1024 x 8 and 1024 x 768 x 16 BPP, supports all 256 raster operations, accelerated BitBLT's, Line Draw, Text, to be connected to TFT (Thin Film Transistor) flat panel or RAMDAC (RAM Digital to Analog Converter)). VSA Audio Controller: SoundBlaster II, Pro and 16 compatible, FM synthesis, MPU-401 MIDI interface, audio sampling with data formatting, upgradable to hardware wave table. Power management: Enhanced SMM (System Management Mode), stop clock, suspend mode, Cx5510 notebook power management, scratchpad RAM for SMM (System Management Mode) and graphics, private link to Cx5510 for monitoring system activity. Package: Cyrix MediaGX CPU: 352 pin BGA (Ball Grid Array), MediaGX Cx5510 chip: 208 pin MQFP (Metal Quad Flat Package). 60/120 MHz (Cyrix Cx5gx86-120 CPU). 66/133 MHz (Cyrix Cx5gx86-133 CPU): February 1997. 3.3 V. Cyrix MediaGXi CPU. 66/150 MHz (Cyrix Cx5gx86-150 CPU). 66/166 MHz (Cyrix Cx5gx86-166 CPU): June 1997. 60/180 MHz (Cyrix Cx5gx86-180 CPU): June 1997. 2.5 V. Technology: Cyrix MediaGX CPU: 0.5 micron TLM CMOS, 3.3 - 3.6 V, 2.4E6 transistors, die size: 134 mm2, MediaGX Cx5510 chip: 3-layer metal, 0.6 micron CMOS, 3.3 V. 2.4E6 transistors. Die size: 160 mm2. Used in Compaq Pressario 2000. 2.62 DEC Alpha CPU 2.62.1 DEC DECchip-210 Alpha CPU RISC (Reduced Instruction Set Computer). 64 bit architecture. 64/128 bit data bus. Superscalar: 2 64 bit integer units, floating point unit. 21064-AA: 150 MHz: 3.3 V, February 1992, 200 MHz: external speed: 25, 50, 100 MHz, 3.3 V, end 1992, 35 W, 1.7E6 transistors, die size: 234 mm2. 21064-AA: 2 level cache, 250 MHz: 3.3 V, June 1994, 300 MHz: 3.3 V, June 1994. 21064: 166 MHz: November 1994, 233 MHz: November 1994. 21066: 21064 with PCI controller, DRAM/VRAM controller, graphics interface, 166 MHz, 7W, 200 MHz. 21068: low cost 21066, 66 MHz, December 1993, 20 W, 100 MHz, December 1993. Used in DEC Alpha AXP. 2.62.2 DEC DECchip-211 Alpha CPU 21164A: 433 MHz, 500 MHz. 21164PC (DEC, Mitsubishi): MVI multi-media instruction set (Motion Video Picture), 8 kbyte data cache, 16 kbyte instruction cache (Harvard architecture), maximum 4 Mbyte level 2 cache, 3.4E6 transistors, die size: 137 mm2, 400 MHz: March 1997, 466 MHz: March 1997, 533 MHz: March 1997, SPECint95 14.3, SPECfp95 17.0. 266 MHz: September 1994, 9.3E6 transitors, die size: 314 mm2. 300 MHz: September 1994, 9.3E6 transitors, die size: 314 mm2. 400 MHz. 466 MHz. 500 MHz: 16 kbyte level 1 cache, 96 kbyte level 2 cache, 9E6 transistors. 533 MHz. 600 MHz (announced). Manufactured by DEC, Mitsubishi, and Samsung. 2.62.3 DEC DECchip-212 Alpha CPU 21264: March 1998, 15.2E6 transitors, 0.35 micron CMOS, MVI multi-media instruction set (Motion Video Picture), >800 MHz (announced: fourth quarter 1998): 0.25 micron CMOS, 1000 MHz (announced: 2000): 0.18 micron CMOS. 2.63 MIPS CPU 2.63.1 MIPS R4000 CPU RISC (Reduced Instruction Set Computer). 64 bit data bus. 64 bit address bus. data and address bus are multiplexed. 8 kbyte instruction cache, 8 kbyte data cache (Harvard architecture): both direct mapped. MIPS R4000MC/R4000SC CPU: secondary external cache controller (128 bit bus). 100 MHz: 5V. LSI Logic LR4000PC CPU: 50 MHz, 0.7 micron CMOS. LSI Logic LR4000MC CPU. LSI Logic LR4000SC CPU: internal / external clock rate selectable 1/2, 1/3, 1/4, 100 MHz maximum. 1.1E6 transistors. Also available from NEC, IDT and Toshiba. 2.63.2 MIPS R4200 CPU 16 kbyte instruction cache, 8 kbyte data cache (Harvard architecture): both direct mapped. 80 MHz: 3.3 V (also available from NEC). 1.3E6 transistors. 2.63.3 MIPS R4400 CPU 16 kbyte instruction cache, 16 kbyte data cache (Harvard architecture): both direct mapped. MIPS R4400MC/R4400SC CPU: secondary external cache controller (128 bit bus). 100 MHz: 5 V. 100 MHz: 3.3 V. 133 MHz: 5 V. 133 MHz: 3.3 V. 150 MHz: 5 V. 150 MHz: 3.3 V. 200 MHz: 3.3 V, May 1994. Also available from NEC, IDT and Toshiba. 2.63.4 MIPS Orion R4600 CPU Designed by QED. 16 kbyte instruction cache, 16 kbyte data cache (Harvard architecture): both 2-way set-associative. 100 MHz: 5 V (also available from IDT). 100 MHz: 3.3 V (also available from Toshiba). 133 MHz: April 1994. 150 MHz. 2.63.5 MIPS R10000 CPU 275 MHz. 2.63.6 MIPS announcements H1. H2. 2.64 IBM, Motorola PowerPC CPU RISC (Reduced Instruction Set Computer). 64 bit architecture. In June 1998 the PowerPC consortium fell apart. Motorola bought the IBM part of the Sommerset PowerPC development center in Austin, Texas. 2.64.1 IBM, Motorola PowerPC 401 CPU Embedded microprocessor. 20 MHz. 25 MHz. 33 MHz. 3.3 V. Third quarter 1994. 2.64.2 IBM, Motorola PowerPC 601 CPU For personal computers. 64 bit external data bus. 32 bit address bus. 32 kbyte cache. 50 MHz: 3.6 V, April 1993. 60 MHz. 66 MHz: 3.6 V, April 1993, 9 W. 80 MHz: 3.6 V, fourth quarter 1994, 85 SPECint92, 105 SPECfp92, 8 W, used in Apple Power Macintosh and IBM RS/6000, 100 MHz: November 1994, 4 W, IBM 0.5 micron CMOS. 135 MHz (announced: fourth quarter 1994). POWER (Performance Optimization With Enhanced RISC). 2.8E6 transistors. Die size: 120 mm2. MC98601. 2.64.3 IBM, Motorola PowerPC 602 CPU For advanced consumer electronics, handheld computers. 66 MHz: February 1995. 2.64.4 IBM, Motorola PowerPC 603 CPU For notebooks. Low power. 8 kbyte cache. 50 MHz: October 1993. 66 MHz: 3.3 V, October 1993. 80 MHz: October 1993, 75 SPECint92, 85 SPECfp92. 1.6E6 transistors. Die size: 83 mm2. Troubles running SoftPC; probably a 603+ will be developed by Apple. 2.64.5 IBM, Motorola PowerPC 603e CPU 16 kbyte cache. 100 MHz: October 1995, 1.2 W. 120 MHz: October 1995. 240 MHz. 300 MHz (Motorola). 2.6E6 transistors. Die size: 98 mm2. 2.64.6 IBM, Motorola PowerPC 604 CPU For high performance desktop computers, workstations. 75 MHz: 3.3 V, December 1994. 100 MHz: 3.3 V, December 1994. 120 MHz: 3.3 V, SPECint92 180, SPECfp92 180. 133 MHz: 3.3 V, SPECint92 200. Package: ceramic QFP (Quad Flat Package), ceramic BGA (Ball Grid Array). 3.3 V. 3.6E6 transistors. Die size: 13 x 15 mm. Technology: 0.5 micron CMOS. 2.64.7 IBM, Motorola PowerPC 604e CPU 166 MHz. 200 MHz. 225 MHz. 233 MHz. 300 MHz: April 1997. 332 MHz: April 1998. 5.1E6 transistors. Die size: 148 mm2. 2.64.8 IBM, Motorola PowerPC 615 CPU 80X86 interpreter (hardware). Intel ODP CPU pin compatible. Announced: fourth quarter 1994. 2.64.9 IBM, Motorola PowerPC 620 CPU For servers. 64 bit data bus. 64 bit address bus. Units: 2 integer, 2 floating point, 2 branch, jump. 32 kbyte instruction cache. POWER2 (Performance Optimization With Enhanced RISC 2). 71.5 MHz: 126 SPECint92, 260 SPECfp92. 130 MHz: 3.3 V. 133 MHz: October 1994. 150 MHz: 3.3 V. 2.64.10 IBM, Motorola PowerPC 630 CPU 64 bit data bus. 64 bit address bus. Multi-chip CPU: core, cache, controller. POWER3 (Performance Optimization With Enhanced RISC 3). Technology: IBM 7S copper CMOS. IBM. 2.64.11 IBM, Motorola PowerPC 750 CPU 266 MHz. 275 MHz: January 1998. 300 MHz: 32 kbyte data cache, 32 kbyte instruction cache, 2.7 V, March 1998, 7.3 W, SPECint92 13.2, SPECfp92 8.5, 6.35E6 transistors, IBM 0.25 micron 6S CMOS. 350 MHz. 400 MHz (demo IBM): technology: IBM C7 CMOS. 480 MHz (demo IBM): technology: IBM 7S copper CMOS. 500 MHz (announced): IBM copper CMOS. G3. 2.65 Sun Sparc CPU RISC (Reduced Instruction Set Computer). Texas Instruments SuperSPARC CPU (Viking). Texas Instruments SuperSPARC II CPU (announced). Texas Instruments UltraSPARC CPU (announced). Fujitsu MicroSPARC II CPU. Ross/Fujitsu Hypersparc CPU. Sparc Ultra: 250 MHz, end 1995. Sparc Ultra IIi: 270 MHz, 300 MHz, 333 MHz, March 1998. Sparc Ultra II: 336 MHz, March 1998. Sparc Ultra III (announced: 1999): 600 MHz, technology: TI 0.18 micron CMOS. 2.66 HP PA CPU (Precision Architecture) RISC (Reduced Instruction Set Computer). HP invested over $1,000,000,000 in this CPU and agreed with Intel to co-operate in the development of a new 64 bit RISC CPU using this architecture. HP PA-7200 CPU. HP PA-8000 CPU: 180 MHz. HP PA-8200 CPU: 240 MHz, March 1998. HP PA-8500 CPU: announced: end 1998. 2.67 Java CPU 2.67.1 Sun microJava 701 CPU 2.68 Motorola CPU In this section the Motorola CPU series, used in the Apple Macintosh personal computers and the Commodore Amiga home computers are described. Bit numbering: small endian. Byte numbering: big endian. 2.68.1 Motorola MC6800 CPU 8 bit data bus. 16 bit address bus. 1 MHz. 2 MHz. August 1974. 68E3 transistors. 2.68.2 Motorola MC6802 CPU Motorola MC6800 CPU with extra features: 256 byte scratch pad at location 0, internal clock oscillator. Hitachi 6802W CPU: Motorola MC6802 CPU. 2.68.3 Motorola MC68HC11 CPU Motorola MC6802 CPU with extra features: some 16 bit instructions, on-board peripherals. 2.68.4 Motorola MC6809 CPU Optimized for high level languages. Motorola MC6809E CPU: external clock input for external sync. 2.68.5 Motorola MC68000 CPU 16 bit data bus. 24 bit address bus. September 1979. Used in Atari ST, Commodore Amiga, Apple Lisa, Macintosh. 2.68.6 Motorola MC68008 CPU 8 bit data bus. 20 bit address bus. Motorola MC68000 CPU instruction compatible. Same core as Motorola MC68000 CPU. 1983. 2.68.7 Motorola MC68302 CPU Integrated Multi-Protocol CPU. Motorola MC68000/MC68008 CPU core. System Integration Block: independent DMA, on-chip 1152 byte DPRAM, 3 timers including watchdog, on-chip clock generator with output, low power stand-by modes, 4 programmmable chip selects, programmable address mapping, parallel I/O ports with interrupt capability, interrupt controller, bus arbitration logic. Communications proccessor: RISC processor (Reduced Instruction Set Computer), 3 independent full duplex SCCs, supporting HDLC/SDLC, UART, BISYNC, DDCMP, V.110 rate adaption, transfer mode protocols, supporting user configureable protocols using microcode, 6 serial DMA channels, Flexible Physical Interface, using IDL, GCI, PCM, NMSI, SCP for synchronous communications, 2 serial management controllers to support GCI and IDL. 16.667 MHz. 2.68.8 Motorola MC68010 CPU Motorola MC68000 CPU upward instruction compatible: more instructions, more instructions with restart capabilities after interrupts. Motorola MC68000 CPU pin compatible. 1984. 2.68.9 Motorola MC68340 microprocessor Embedded version of Motorola MC68010 CPU. Included features: 2 DMA channels, 2 serial I/O channels, 2 multiple mode 16 bit timers, 4 programmable chip select signals, system failure protection. 16.78 MHz: 5 V. Package: 144 pin CQFP (Ceramic Quad Flat Package), 145 pin PGA (Pin Grid Array). 2.68.10 Motorola MC68020 CPU Motorola MC6800 CPU / Motorola MC68010 CPU upward instruction compatible. Extra features: extra instructions (32 bit multiplication and division), extra addressing modes. Modes: user mode, supervisor mode. 32 bit data bus. 32 bit address bus. 256 byte instruction cache. MMU (Memory Management Unit): Motorola MC68851 Paged MMU, 16 byte burst mode. NPX: Motorola MC68881 NPX or faster Motorola MC68882 NPX. 16.67 MHz. 20 MHz. 25 MHz. 33.33 MHz. Motorola MC68020RC CPU. Motorola MC68020RL CPU. Motorola MC68020RP CPU. Motorola MC68020FC CPU. Motorola MC68020FE CPU. 1982. Used in Amiga, Apple Macintosh, Sun3. 2.68.11 Motorola MC68030 CPU 256 byte instruction cache, 256 byte data cache (Harvard architecture). MMU (Memory Management Unit), 16 byte burst mode. NPX: Motorola MC68881 NPX or faster Motorola MC68882 NPX. 25 MHz. 50 MHz. Motorola MC68030RC CPU. Motorola MC68030RL CPU. Motorola MC68030RP CPU. Motorola MC69030FE CPU. 1987. 270E3 transistors. Used in Amiga 3000 and 4000, Sun3, NeXT, Atari TT030, Atari Falcon 030, Apple Macintosh and PowerBook. 2.68.12 Motorola MC68040 CPU MMU (Memory Management Unit), FPU (Floating Point Unit), pipelined, clock doubled. 4 kbyte instruction cache, 4 kbyte data cache (Harvard Architecture). 20 MHz: September 1990. 25 MHz: January 1991. 33 MHz: January 1991. 40 MHz. 1.2E6 transistors. Die size: 153 mm2. Used in Amiga 4000, Apple Macintosh, NeXT. 2.68.13 Motorola MC68LC040 CPU Motorola MC68040 CPU without MMU (Memory Management Unit) and FPU (Floating Point Unit). Used in Apple Macintosh, QXL. 2.68.14 Motorola MC68040V CPU Low power version (3.3 V) of the Motorola MC68040 CPU, no FPU (Floating Point Unit). Used in DraCo, Apple Powerbook. 2.68.15 Motorola MC68050 CPU Never released. 2.68.16 Motorola MC68060 CPU 32 bit data bus. 32 bit address bus. Enhanced FPU (Floating Point Unit). Power management. 8 kbyte instruction cache, 8 kbyte data cache (Harvard architecture). Cache line bursts. 16 byte burst mode. 3.3 V. Superscalar. Branch Target Buffer (BTB). Branch prediction and elimination. 40 MHz: April 1994. 50 MHz: April 1994. 66 MHz: April 1994. 2.3E6 transitors. Used in DraCo, Amiga accelerator boards. Compiled, Copyright 1993 - 1998, by A. Offerman. Permission to use, copy, or distribute this document in a non-commercial way for non-commercial use is hereby granted, provided that this copyright and permission notice appear in all copies. All other rights reserved. This document is provided "as is" without expressed or implied warranty. The specific products and their respective manufacturers are not to be taken as endorsements of, nor commercials for, the manufacturer.