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misctips.txt
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1994-09-10
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BLOBSTOP V1.0
misctips.txt
****************************************************************************
September 1, 1994
Here's a bunch of odd ball items that you might find helpful:
1. In case anybody is wondering who turns up the speed, one of the last
things the boot module does is to put the CoCo into the 2 Mhz mode.
2. If you have test code within a device driver and you want it to send
you a "signal", try poking values into the border register at $FF9A.
OS9 won't mind a bit.
3. If your disassembler is the type that misses IRQ routines and prints
them as a bunch of fcbs, try this trick: a. Disassemble the code.
b. Put in long branch subroutines (lbsr) to the beginning of each IRQ
routine that the disassembler missed. The best place to do this is in
the last instructions that the disassembler picked up:
.
.
.
decb
bne L004b
clrb
rts
* end of code here
Becomes:
.
.
.
decb
bne L004b note that the lbsrs are in a "path of
clrb execution"
lbsr D0100 branch to IRQ#1 that disa missed
lbsr D02f0 branch to NMI that disa missed
lbsr D01a0 branch to IRQ#2 that disa missed
rts
* end of code
c. Assemble the code with asm. d. Disassemble the resulting object
code. e. Remove the statements that you added. Remember that the
offset labels to code after your inserted code will no longer be valid
as offsets from the start of the module. If you have no labels after
the place where your lbsrs were, then this will not be a problem.
f. Presto, fully disassembled code!
3. The magnetic zones on a disk tend to repel or attract each other
depending on their respective polarities, just like little magnets.
Thus, the ones and zeros on a disk tend to "move" a bit depending on
the adjacent bits. If pronounced enough, this effect can lead to read
errors. This is particularly true on the inner (high #) tracks where
the bits are closer together. Write precompensation is a process in
which the position of the bits is shifted during writes to compensate
for the natural "wandering" of the bits. As Kevin Darling mentioned
in his book "Inside OS9 Level II" (p 3-5-3), cc3disk never activates
the 1773's built in write precomp circuits. However, I found unused,
leftover code in cc3disk that is designed to activate write precomp.
Talk about skeletons in the closet! Perhaps future patches could
renable precomp on the inner tracks. A small improvement in read
relability could be realized especially by those using older drives.
4. If you are experiencing I/O errors with a MPI, especially with the
buffered mode of the SCII, try changing IC1 on the older MPI or IC2
on the newer MPI. These chips handle the E clock and some other signals.
I have seen a case in which a bad chip caused some of the address lines
to bounce with transitions of the E clock -> bad news!
5. The owner's manual of my Disto SCII has a mistake in table 2. The
register addresses are listed backwards. Here's the corrections:
Table 2 - SCII registers
Location Description
Hex Dec
FF77 65399 FF76 mirror
FF76 65398 write: D0 = 0 FDC write operation *1
= 1 FDC read operation *1
D1 = 0 normal mode
= 1 buffered mode
D2 = 0 normal NMI
= 1 masked NMI
D3 = 0 no FIRQ (masked)
= 1 FIRQ enabled
read: D7 = FDC INTRQ status (inverted)
FF75 65397 FF74 mirror
FF74 65396 Read/Write buffer *2
*1: In the buffered mode.
*2: Any write to $FF76 or $FF77 clears the buffer counter.
Note that the data buffer mirror allows std and ldd for pseudo
16 bit transfers.
Also, there are a few corrections needed to the SCII schematic set:
On V1.3:
a. There should be an inverter in series with the line that leads
to the counter (between pin 18 of U6 and pin 1 of U7). This is
the small "hack" that you see on the "wrong" side of the PC board
near the CoCo connector.
b. The address line pins of U6 should read: 1,3,5,7,2,4,6,8 not
8,7,6,5,4,3,2,1 as given.
On V1.4:
c. Pin 1 of U8 should be shown connected to GND not VCC.
On both versions:
d. Pin 10 of U8 connects to pin 12 of U13, NOT to pin 13 of U13.
6. Concerning GIME S0-S2 hacks: Four signals are produced by IC9 on the
CoCo3 motherboard. They are SCS (which helps decode I/O devices),
CTS (which turns on the cartridge ROM), ROM (which turns on the
motherboard ROM), and the signal which decodes the PIAs which I'll
call PIA. These signals belong to two different groups.
a. Address Decoding Signals (ADS). SCS and PIA belong to this
group. These signals are used in conjunction with the address
lines to decode an address. The E clock is then used to actually
turn on the device.
b. Chip Select Signals (CSS). CTS and ROM belong to this group.
When these signals are active, the devices turn on regardless
of the E clock.
The problem many hackers see with all this is that CTS and ROM do not
APPEAR to be gated with E (unless the GIMEs do this internally). So, a
ROM device could start outputting junk onto the data bus without checking
E. Since ROMs tend to be a bit slow, this could cause a collision on the
data bus. The result is a BLOB causer.
As a solution, many hackers rigged U9 so that ALL FOUR signals were
gated with the E clock. This is fine and well for CTS and ROM, but I
don't think this is a good idea for SCS and PIA. The ADS signals
should be stable BEFORE E becomes high in order to give the address
decoding logic enough time to stablize prior to E becoming high. If
SCS changes with E, a logic race condition could occur in some CoCo
accessories. This could cause I/O glitches.
So, I suggest that any E gating hacks should be confined to CTS and
ROM. A 74LS157 (or 74ACT157 if you want the best) should do the job
nicely (E clk to A/B select; A inputs go to VCC; B inputs go to CTS and
ROM; outputs are new, gated CTS and ROM).
Since CTS is hardly ever used under OS9, but ROM is used for every
interrupt, you can try a simpler hack that affects the ROM on the
motherboard only. Using an inverter, make an inverted E clock and then
route this signal to pin 22 (OE, active low) of the ROM. Be sure and
remember to cut the trace that currently grounds pin 22.
As a final note, all of this address decoding appears to have been
done correctly with the SAM chip in the CoCo2. However, without knowing
how the GIME generates S0-S2, we can't be sure that it is done correctly
in the CoCo3. Note that the GIME probably does SOME additional
processing of these signals. For example, R/W is probably taken into
account to prevent the CPU from trying to write to a ROM and thereby
creating the mother of all bus collisions. If the GIME does indeed
consider E and R/W properly in developing S0-S2, then no hack should
be needed at all. Gating SCS with E, as most "improper" hacks do, delays
the enable of the 1773 chip by a few nanoseconds. This could affect
the 1773 BLOB problem. Thus, many S0-S2 hacks may appear to fix GIME
problems, when in fact, the 1773 was the problem all along.
Time spent with a logic analyzer could settle this issue once and
for all.
-----------------------------------------------------------------------------
Well, I hope this stuff helps somebody out there. Happy CoCoing!
Michael Shell