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Text File  |  1989-12-07  |  33KB  |  563 lines
  1. ;
  2. ;        DMA  Channel 0-3  Registers
  3. ;
  4. dma0_addr          equ       000h       ; for write -- base and current address
  5.                                         ; for read  -- current address
  6. dma0_count         equ       001h       ; for write -- base and current W count
  7.                                         ; for read  -- current word count
  8. dma1_addr          equ       002h       ; for write -- base and current address
  9.                                         ; for read  -- current address
  10. dma1_count         equ       003h       ; for write -- base and current W count
  11.                                         ; for read  -- current address
  12. dma2_addr          equ       004h       ; for write -- base and current address
  13.                                         ; for read  -- current address
  14. dma2_count         equ       005h       ; for write -- base and current W count
  15.                                         ; for read  -- current word count
  16. dma3_addr          equ       006h       ; for write -- base and current address
  17.                                         ; for read  -- current address
  18. dma3_count         equ       007h       ; for write -- base and current W count
  19.                                         ; for read  -- current W count
  20. dma03_status       equ       008h       ; read only
  21.                                         ; bit 0 = 1 channel 0 has reached TC
  22.                                         ; bit 1 = 1 channel 1 has reached TC
  23.                                         ; bit 2 = 1 channel 2 has reached TC
  24.                                         ; bit 3 = 1 channel 3 has reached TC
  25.                                         ; bit 4 = 1 channel 0 request
  26.                                         ; bit 5 = 1 channel 1 request
  27.                                         ; bit 6 = 1 channel 2 request
  28.                                         ; bit 7 = 1 channel 3 request
  29. dma03_command      equ       08h        ; write only, for channel 0-3
  30.                                         ; bit 0 = memory-to memory enable+
  31.                                         ; bit 1 = channel 0 address hold enable+
  32.                                         ; bit 2 = controller enable-
  33.                                         ; bit 3 = normal-/compressed+ timing
  34.                                         ; bit 4 = fixed-/rotating+ priority
  35.                                         ; bit 5 = late-/extended+ write selection
  36.                                         ; bit 6 = DREQ active low+/high-
  37.                                         ; bit 7 = DACK active low-/high+
  38. dma03_smask        equ       00ah       ; single mask reg, write only
  39.                                         ; bit 1,0 --> for select channel mask bit
  40.                                         ;     00  --> select channel 0
  41.                                         ;     01  --> select channel 1
  42.                                         ;     10  --> select channel 2
  43.                                         ;     11  --> select channel 3
  44.                                         ; bit 2 = 0 clear mask bit
  45.                                         ;       = 1 set mask bit
  46. dma03_mode         equ       00bh       ; mode register, write only
  47.                                         ; bit 0,1 = channel select
  48.                                         ;         = 00 select channel 0
  49.                                         ;         = 01 select channel 1
  50.                                         ;         = 10 select channel 2
  51.                                         ;         = 11 select channel 3
  52.                                         ; bit 2,3 = 00 verify transfer
  53.                                         ;         = 01 write transfer
  54.                                         ;         = 10 read transfer
  55.                                         ;         = 11 reserved
  56.                                         ; bit 4-7 = reserved = 0
  57. dma03_clear        equ       00ch       ; clear byte pointer, write only
  58. dma03_reset        equ       00dh       ; same as hardware reset, write only
  59. dma03_clrmsk       equ       00eh       ; clears the mask bits of channel 0-3
  60.                                         ; enabling them to accept dma requests
  61. dma03_amask        equ       00fh       ; mask reg, write only
  62.                                         ; bit 0 = 0 clear channel 0 mask bit
  63.                                         ;       = 1 set channel 0 mask bit
  64.                                         ; bit 1 = 0 clear channel 1 mask bit
  65.                                         ;       = 1 set channel 1 mask bit
  66.                                         ; bit 2 = 0 clear channel 2 mask bit
  67.                                         ;       = 1 set channel 2 mask bit
  68.                                         ; bit 3 = 0 clear channel 3 mask bit
  69.                                         ;       = 1 set channel 3 mask bit
  70.                                         ; bit 4-7 = don't care
  71.                                         ; bit 0,1 --> for select channel mask bit
  72.                                         ; bit 2 = 0 clear mask bit
  73.                                         ;       = 1 set mask bit
  74. ;
  75. ;        PIC(8259) control port
  76. ;
  77. pic1_port1         equ       020h       ; A0 set to 0
  78.                                         ; for ocw2
  79.                                         ; bit 0-2: L0, L1, L2 -- interrupt level
  80.                                         ;          when bit 6 (SL) = 1
  81.                                         ; bit 3,4 = 0, 0
  82.                                         ; bit 5-7: R, SL, EOI -- for select each
  83.                                         ; function (R, EOI) or combinations
  84.                                         ; R: rotate, EOI: end of interrupt
  85.                                         ; for ocw3
  86.                                         ; bit 0-2: RIS, RR, P
  87.                                         ; bit 3,4 = 0, 1
  88.                                         ; bit 5,6: SMM, ESMM -- Special Mask Mode
  89.                                         ; if ESMM = 1 and SMM = 1 enter S. M. M.
  90.                                         ; if ESMM = 1 and SMM = 0 revert to Normal
  91.                                         ; when ESMM = 0, SMM has no effect
  92.                                         ; Enable Special Mask Mode
  93.                                         ; if ESMM = 1 enable SMM = 1 or 0
  94.                                         ; if ESMM = 0 SMM = x
  95. pic1_port2         equ       021h       ; A0 set to 1
  96.                                         ; sets and clears the mask bits in the
  97.                                         ; IMR. bit 0-7: M0-M7 represent the 8
  98.                                         ; mask bits
  99. ;
  100. ;        DEVICE and POINT DEVICES
  101. ;
  102. device_offset      equ       022h       ;device drive far call offset
  103. device_segment     equ       024h       ;device drive far call segment
  104. pd_flag1           equ       026h       ;pointing device flag
  105.                                         ;bit 7 -- command in progress
  106.                                         ;bit 6 -- resend
  107.                                         ;bit 5 -- ack
  108.                                         ;bit 4 -- error
  109.                                         ;bit 3 -- reserved, 0
  110.                                         ;bit 2-0 -- index count
  111. pd_flag2           equ       027h       ;pointing device flag
  112.                                         ;bit 7 -- device drive far call flag
  113.                                         ;bit 6-3 -- reserved
  114.                                         ;bit 2-0 -- package size
  115.                                         ; 1 - enable watch dog = timer count
  116. ;
  117. ;   Programmable Interval Timer
  118. ;
  119. pit_ch0            equ       040h       ; port address of timer 0(16 bit)
  120. pit_ch1           equ         041h    ; port address of timer 1(16 bit)
  121. pit_ch2            equ       042h       ; port address of timer 2(16 bit)
  122. pit02_ctrl         equ       043h       ; control word register for timer 0, 1, 2, write only
  123.                                         ; bit 0    = 0, count in binary
  124.                                         ;            1, count in BCD
  125.                                         ; bits 3-1 = mode number (00h - 05h)
  126.                                         ; bits 5,4 = read/write
  127.                                         ;      00  - counter latch command
  128.                                         ;      01  - read/load low byte
  129.                                         ;      10  - read/load high byte
  130.                                         ;      11  - read/load low byte,then high byte
  131.                                         ; bits 7,6 = counter select
  132.                                         ;      00  - select timer 0
  133.                                         ;      01  - select timer 1
  134.                                         ;      10  - select timer 2
  135.                                         ;      11  - read-back command(for read)
  136.                                         ;  *   Read-back command format :
  137.                                         ;  Bit
  138.                                         ; ------------------------------------------
  139.                                         ;   5   = 0  Latch count of selected counter(s)
  140.                                         ;   4   = 0  Latch status of selected counter(s)
  141.                                         ;   3   = 1  Select counter 2
  142.                                         ;   2   = 1  Select counter 1
  143.                                         ;   1   = 1  Select counter 0
  144.                                         ;   0   reserved = 0
  145. kb_port            equ       060h       ; input/output buffer for KB and AUX
  146. cmd_status_8042    equ       064h       ; 8042 command port
  147.                                         ; for write operation
  148.                                         ;   bit 7 = reserved = 0
  149.                                         ;   bit 6 = IBM translate mode
  150.                                         ;   bit 5 = disable_/enable- AUX device
  151.                                         ;   bit 4 = disable+/enable- KB
  152.                                         ;   bit 3 = reserved = 0
  153.                                         ;   bit 2 = system flag
  154.                                         ;   bit 1 = enable AUX interrupt
  155.                                         ;   bit 0 =
  156.                                         ; for read operation
  157. ;
  158. ;    system control port
  159. ;
  160. sysb_ctrl          equ       061h       ; system control port B
  161.                                         ; for write operation
  162.                                         ;   bit 0 = timer 2 gate
  163.                                         ;   bit 1 = speaker data enable
  164.                                         ;   bit 2 = -enable parity check
  165.                                         ;   bit 3 = -enable channel check
  166.                                         ;   bit 4 = reserved
  167.                                         ;   bit 5 = reserved
  168.                                         ;   bit 6 = reserved = 0
  169.                                         ;   bit 7 = reserved
  170.                                         ; for read operation
  171.                                         ;   bit 0 = timer 2 gate
  172.                                         ;   bit 1 = speaker data enable
  173.                                         ;   bit 2 = -enable parity check
  174.                                         ;   bit 3 = -enable channel check
  175.                                         ;   bit 4 = toggle with each refresh request
  176.                                         ;   bit 5 = timer 2 output
  177.                                         ;   bit 6 = channel check
  178.                                         ;   bit 7 = parity error
  179. ;status_c       equ        85h    ; read/write
  180.                     ; same as port_c(328H)
  181. ;status_speed       equ        86h    ; bit 7-6    speed status
  182.                     ;   1 1        smart
  183.                     ;   0 1         Top speed
  184.                     ;   0 0         none of above
  185.                     ; bit 5        Weitek 3167 Math coprocessor
  186.                     ; bit 4        for 1100/25/20C
  187.                     ;        1 : 1100/25
  188.                     ;        0 : 1100/20C
  189.                     ;            for MSAT/16/20
  190.                     ;            1 : MSAT/20
  191.                     ;            0 : MSAT/16
  192.                     ; bit 3        for 1100/25/20C only
  193.                     ;        1 : cache on
  194.                     ;        0 : cache off
  195.                     ; bit 2        0 : RAM BIOS good
  196.                     ;        1 : RAM BIOS bad
  197.                     ; bit 1        0 : RAM VIDEO good
  198.                     ;        1 : RAM VIDEO bad
  199.                     ; bit 0        0 : console exist
  200.                     ;               1 : console unexist
  201. ;status_d       equ         88h    ; R/W
  202.                     ; bit 7         0 : not in setup
  203.                     ;        1 : in setup
  204.                     ; bit 6         0 : non CONNER
  205.                     ;        1 : CONNER WDD for 2nd WDD
  206.                     ; bit 5         0 : non CONNER
  207.                     ;        1 : CONNER WDD for 1st WDD
  208.                     ; bit 4        0 : 1st WDD active
  209.                     ;        1 : 2nd WDD active
  210.                     ; bit 3         reserved
  211.                     ; bit 2        0 : cache good
  212.                     ;        1 : cache bad
  213.                     ; bit 1         status bit 1 of port_D
  214.                     ; bit 0         0 : jump F000:FFF0H
  215.                     ;               1 : clod start
  216. port_c           equ           328h    ; write only
  217.                     ; bit 7-5    speed parameter(valid when bit 2 = 1)
  218.                                         ;   000         6 MHZ
  219.                                         ;   001         8 MHZ
  220.                                         ;   xxx         bigger value, more fast 
  221.                     ; bit 4         1 : flush cache memory
  222.                     ;               0 :  
  223.                     ; bit 3        1 : enable cache system
  224.                     ;         0 : disable cache system
  225.                     ; bit 2        speed select
  226.                     ;        1 : enable speed change
  227.                     ;        0 : disable speed change
  228.                     ; bit 1        1 : enable RAM BIOS write 
  229.                     ;        0 : disable RAM BIOS Write
  230.                     ; bit 0        1 : enable RAM BIOS 
  231.                     ;        0 : disable RAM BIOS
  232. port_d           equ           329h    ; write only
  233.                      ; bit 1         fast gate A20
  234.                     ;             0 : off gate A20
  235.                     ;           1 : on gate A20
  236. ;
  237. ;     RT/CMOS control port
  238. ;
  239. cmos_addr          equ        070h      ; cmos address register
  240.                                         ;   address       function
  241.                                         ; -----------   ------------
  242.                                         ;     00h          Seconds
  243.                                         ;     01h       Second Alarm
  244.                                         ;     02h          Minutes
  245.                                         ;     03h       Minute Alarm
  246.                                         ;     04h           Hours
  247.                                         ;     05h        Hour Alarm
  248.                                         ;     06h        Day of Week
  249.                                         ;     07h       Date of Month
  250.                                         ;     08h           Month
  251.                                         ;     09h           Year
  252.                                         ;     0Ah     Status Register A
  253.                                         ;     0Bh     Status Register B
  254.                                         ;     0Ch     Status Register C
  255.                                         ;     0Dh     Status Register D
  256. cmos_data          equ        071h      ; cmos data register
  257. ;
  258. ; DMA Page Register
  259. ;
  260. dma_ch0           equ        087h       ; dma channel 0
  261. dma_ch1           equ        083h       ; dma channel 1, for diagnostic
  262. dma_ch2           equ        081h       ; dma channel 2
  263. dma_ch3           equ        082h       ; dma channel 3
  264. dma_ch4           equ        08fh       ; dma channel 4, for refresh memory
  265. dma_ch5           equ        08bh       ; dma channel 5
  266. dma_ch6           equ        089h       ; dma channel 6
  267. dma_ch7           equ        08ah       ; dma channel 7
  268. ;
  269. pic2_port1         equ       0a0h       ; A0 set to 0
  270.                                         ; for ocw2
  271.                                         ; bit 0-2: L0, L1, L2 -- interrupt level
  272.                                         ;          when bit 6 (SL) = 1
  273.                                         ; bit 3,4 = 0, 0
  274.                                         ; bit 5-7: R, SL, EOI -- for select each
  275.                                         ; function (R, EOI) or combinations
  276.                                         ; R: rotate, EOI: end of interrupt
  277.                                         ; for ocw3
  278.                                         ; bit 0-2: RIS, RR, P
  279.                                         ; bit 3,4 = 0, 1
  280.                                         ; bit 5,6: SMM, ESMM -- Special Mask Mode
  281.                                         ; if ESMM = 1 and SMM = 1 enter S. M. M.
  282.                                         ; if ESMM = 1 and SMM = 0 revert to Normal
  283.                                         ; when ESMM = 0, SMM has no effect
  284.                                         ; Enable Special Mask Mode
  285.                                         ; if ESMM = 1 enable SMM = 1 or 0
  286.                                         ; if ESMM = 0 SMM = x
  287. pic2_port2         equ       0a1h       ; A0 set to 1
  288.                                         ; sets and clears the mask bits in the
  289.                                         ; IMR. bit 0-7: M0-M7 represent the 8
  290.                                         ; mask bits
  291. ;
  292. ;        DMA  Channel 4-7  Registers
  293. ;
  294. dma4_addr          equ       0c0h       ; for write -- base and current address
  295.                                         ; for read  -- current address
  296. dma4_count         equ       0c2h       ; for write -- base and current W count
  297.                                         ; for read  -- current word count
  298. dma5_addr          equ       0c4h       ; for write -- base and current address
  299.                                         ; for read  -- current address
  300. dma5_count         equ       0c6h       ; for write -- base and current W count
  301.                                         ; for read  -- current address
  302. dma6_addr          equ       0c8h       ; for write -- base and current address
  303.                                         ; for read  -- current address
  304. dma6_count         equ       0cah       ; for write -- base and current W count
  305.                                         ; for read  -- current word count
  306. dma7_addr          equ       0cch       ; for write -- base and current address
  307.                                       ; for read  -- current address
  308. dma7_count         equ       0ceh       ; for write -- base and current W count
  309.                                         ; for read  -- current W count
  310. dma47_status       equ       0d0h       ; read only
  311.                                         ; bit 0 = 1 channel 4 has reached TC
  312.                                         ; bit 1 = 1 channel 5 has reached TC
  313.                                         ; bit 2 = 1 channel 6 has reached TC
  314.                                         ; bit 3 = 1 channel 7 has reached TC
  315.                                         ; bit 4 = 1 channel 4 request
  316.                                         ; bit 5 = 1 channel 5 request
  317.                                         ; bit 6 = 1 channel 6 request
  318.                                         ; bit 7 = 1 channel 7 request
  319. dma47_command      equ       0d0h       ; write only, for channel 4-7
  320.                                         ; bit 0 = memory-to memory enable+
  321.                                         ; bit 1 = channel 0 address hold enable+
  322.                                         ; bit 2 = controller enable-
  323.                                         ; bit 3 = normal-/compressed+ timing
  324.                                         ; bit 4 = fixed-/rotating+ priority
  325.                                         ; bit 5 = late-/extended+ write selection
  326.                                         ; bit 6 = DREQ active low+/high-
  327.                                         ; bit 7 = DACK active low-/high+
  328. dma47_smask        equ       0d4h       ; single mask reg, write only
  329.                                         ; bit 1,0 --> for select channel mask bit
  330.                                         ;     00  --> select channel 4
  331.                                         ;     01  --> select channel 5
  332.                                         ;     10  --> select channel 6
  333.                                         ;     11  --> select channel 7
  334.                                         ; bit 2 = 0 clear mask bit
  335.                                         ;       = 1 set mask bit
  336. dma47_mode         equ       0d6h       ; mode register, write only
  337.                                         ; bit 1,0 = channel select
  338.                                         ;         = 00 select channel 4
  339.                                         ;         = 01 select channel 5
  340.                                         ;         = 10 select channel 6
  341.                                         ;         = 11 select channel 7
  342.                                         ; bit 3,2 = 00 verify transfer
  343.                                         ;         = 01 write transfer
  344.                                         ;         = 10 read transfer
  345.                                         ;         = 11 reserved
  346.                                         ; bit 7-4 = reserved = 0
  347. dma47_clear        equ       0d8h       ; clear byte pointer, write only
  348. dma47_reset        equ       0dah       ; same as hardware reset, write only
  349. dma47_clrmsk       equ       0dch       ; clears the mask bits of channel 0-3
  350.                                         ; enabling them to accept dma requests
  351. dma47_amask        equ       0deh       ; mask reg, write only
  352.                                         ; bit 0 = 0 clear channel 4 mask bit
  353.                                         ;       = 1 set channel 4 mask bit
  354.                                         ; bit 1 = 0 clear channel 5 mask bit
  355.                                         ;       = 1 set channel 5 mask bit
  356.                                         ; bit 2 = 0 clear channel 6 mask bit
  357.                                         ;       = 1 set channel 6 mask bit
  358.                                         ; bit 3 = 0 clear channel 7 mask bit
  359.                                         ;       = 1 set channel 7 mask bit
  360.                                         ; bit 4-7 = don't care
  361.                                         ; bit 0,1 --> for select channel mask bit
  362.                                         ; bit 2 = 0 clear mask bit
  363.                                         ;       = 1 set mask bit
  364. ;
  365. ;        Math Coprocessor I/O port
  366. ;
  367. math_0             equ       0f0h       ; clare math coprocessor '-busy'
  368. math_1             equ       0f1h       ; reset math coprocessor
  369. ;
  370. ; hard disk port
  371. ;
  372.  
  373. ;
  374. ; Game I/O port
  375. ;
  376. game_io0           equ         200h
  377. game_io1           equ         201h
  378. game_io2           equ         202h
  379. game_io3           equ         203h
  380. game_io4           equ         204h
  381. game_io5           equ         205h
  382. game_io6           equ         206h
  383. game_io7           equ         207h
  384. ;
  385. ;        Parallel Port
  386. ;
  387. paral3_data        equ         278h     ; parallel port 3 data address
  388. paral3_status      equ         279h     ; parallel port 3 status address
  389. paral3_ctrl        equ         37ah     ; parallel port 3 conttol address
  390. paral2_data        equ         378h     ; parallel port 2 data address
  391. paral2_status      equ         379h     ; parallel port 2 status address
  392. paral2_ctrl        equ         37ah     ; parallel port 2 control address
  393. paral1_data        equ         3bch     ; parallel port 1 data address
  394. paral1_status      equ         3bdh     ; parallel port 1 status address
  395. paral1_ctrl        equ         3beh     ; parallel port 1 control address
  396. ;
  397. ;        Serial Port 1
  398. ;
  399.                                         ; i/o addr.   register selected         DLAB state
  400.                                         ; ---------   -----------------         ----------
  401.                                         ; xf8h        TX buffer                 0 (write)
  402.                                         ; xf8h        RX buffer                 0 (read)
  403.                                         ; xf8h        divisor latch LSB         1
  404.                                         ; xf9h        divisor latch MSB         1
  405.                                         ; xf9h        interrupt enable reg      0
  406. ;
  407. tx_buf2            equ         2f8h     ;transmitter holding register
  408.                                         ;
  409. int_ena2           equ         2f9h     ;interrupt enable register
  410.                                         ;
  411. int_iden2          equ         2fah     ;interrupt identification register
  412.                                         ;
  413. line_ctrl2         equ         2fbh     ;line control register
  414.                                         ;
  415. modem_ctrl2        equ         2fch     ;modem control register
  416.                                         ;
  417. line_status2       equ         2fdh     ;line status register
  418.                                         ;
  419. modem_status2      equ         2feh     ;modem status register
  420.                                         ;bit 7 -- reserved
  421. tx_buf1            equ         3f8h     ;transmitter holding register
  422.                                         ;bit 0~7 -- data bit 0~7
  423. int_ena1           equ         3f9h     ;interrupt enable register
  424.                                         ;bit 7 - 4 -- reserved
  425.                                         ;bit 3 -- receive modem status
  426.                                         ;bit 2 -- receive line status
  427.                                         ;bit 1 -- Tx holding register empty
  428.                                         ;bit 0 -- receive data available
  429. int_iden1          equ         3fah     ;interrupt identification register
  430.                                         ;bit 7 - 3 = 0
  431.                                         ;bit 1 - 2 -- interrupt id
  432.                                         ;bit 0 = 0 -- interrupt pending
  433.                                         ; id = 1 1 -- receive line status
  434.                                         ;      1 0 -- receive data available
  435.                                         ;      0 1 -- transmit holding empty
  436.                                         ;      0 0 -- modem status
  437.                                         ;
  438. line_ctrl1         equ         3fbh     ;line control register
  439.                                         ;bit 7 -- DLAB
  440.                                         ;bit 6 -- set break
  441.                                         ;bit 5 -- stick parity
  442.                                         ;bit 4 -- even parity
  443.                                         ;bit 3 -- parity enable
  444.                                         ;bit 2 -- # of stop bit
  445.                                        ;bit 1, 0 -- word length
  446. modem_ctrl1        equ         3fch     ;modem control register
  447.                                         ;bit 7 - 5 = 0
  448.                                         ;bit 4 -- loop
  449.                                         ;bit 3 -- out 2
  450.                                         ;bit 2 -- out 1
  451.                                         ;bit 1 -- RTS
  452.                                         ;bit 0 -- DTR
  453. line_status1       equ         3fdh     ;line status register
  454.                                         ;bit 7 = 0
  455.                                         ;bit 6 -- Tx shift register empty
  456.                                         ;bit 5 -- Tx holding register empty
  457.                                         ;bit 4 -- break interrupt
  458.                                         ;bit 3 -- FE
  459.                                         ;bit 2 -- PE
  460.                                         ;bit 1 -- OE
  461.                                         ;bit 0 -- data ready
  462. modem_status1      equ         3feh     ;modem status register
  463.                                         ;bit 7 -- data carrier
  464.                                         ;bit 6 -- RI
  465.                                         ;bit 5 -- DSR
  466.                                         ;bit 4 -- CTS
  467.                                         ;bit 3 -- delta data carrier
  468.                                         ;bit 2 -- trailing edge RI
  469.                                         ;bit 1 -- delta DSR
  470.  
  471. ;
  472. ;    diagnostic port
  473. ;
  474. diag_port1      equ          3bch    ; for BIOS team
  475. diag_port2      equ          378h    ;    
  476. diag_port3      equ          300h    ; for debug board    
  477. diag_port4      equ          080h    ; for debug board
  478.                                         ;bit 0 -- delta CTS
  479. ;
  480. ;        Disk Controller Ports
  481. ;
  482. hd_ctrl           equ          3f6h    ; fixed disk contrl register
  483.                     ;  bit 7 - 3      reserved = 0
  484.                     ;  bit 2          reset
  485.                     ;  bit 1      enable IREQ
  486.                     ;  bit 0      reserved = 0
  487. hd_alt             equ        3f6h      ; fixed disk alternate status
  488.                     ;   same as status register
  489. hd_port0       equ          1f0h    ; data register
  490. hd_port1       equ          1f1h    ; error reg./write precomp reg    
  491. hd_port2       equ          1f2h    ; sector count register
  492. hd_port3       equ          1f3h    ; sector number register
  493. hd_port4       equ          1f4h    ; cylinder low register
  494. hd_port5       equ          1f5h    ; cylinder high register
  495. hd_port6       equ          1f6h    ; device/head
  496. hd_port7       equ          1f7h    ; status reg./command register
  497.                     ;  bit 7      busy
  498.                     ;  bit 6      Ready
  499.                     ;  bit 5      write fault
  500.                     ;  bit 4      seek completed
  501.                     ;  bit 3      data request
  502.                     ;  bit 2      data corrected
  503.                     ;  bit 1      index
  504.                     ;  bit 0      error status
  505. ;
  506. ;      Diskette Controller Ports
  507. ;
  508. dsk_sta_b          equ         3f1h     ; reserved
  509. sdisk_outreg       equ         3f2h     ; digital output register
  510.                                         ; bit 0 -- drive select = 0 -- drive A
  511.                                         ;                       = 1 -- drive B
  512.                                         ; bit 1 -- reserved
  513.                                         ; bit 2 -- diskette function reset
  514.                                         ; bit 3 -- enable diskette int. and dma
  515.                                         ; bit 4 -- drive A motor enable
  516.                                         ; bit 5 -- drive B motor enable
  517.                                         ; bit 6 -- reserved
  518.                                         ; bit 7 -- reserved
  519. main_status        equ         3f4h     ; main status register
  520.                                         ; bit 7 = RQM -- request to master
  521.                                         ; bit 6 = DIO -- data input/output
  522.                                         ;         = 1 -- data tranfer from FDC
  523.                                         ;                data reg. to processor
  524.                                         ;         = 0 -- in reverse order above
  525.                                         ; bit 5 = NDM -- non-DMA mode
  526.                                         ; bit 4 = CB  -- diskette controller
  527.                                         ;                busy = 1 -- FDC busy
  528.                                         ; bit 3 -- reserved
  529.                                         ; bit 2 -- reserved
  530.                                         ; bit 1 = DBB -- diskette drive B busy
  531.                                         ;                =1 -- FDD busy
  532.                                         ; bit 0 = DAB -- diskette drive a busy
  533.                                         ;                =1 -- FDD busy
  534. data_reg           equ         3f5h     ; FDC data register(read/write)
  535. sdisk_inreg        equ         3f7h     ;digital input register
  536.                                         ; for read
  537.                                         ;   bit 7  --  diskette change
  538.                                         ;              1  -  active
  539.                                         ;              0  -  inactive
  540.                                         ;   bit 6  --  write gate(for WDD)
  541.                                         ;   bit 5  --  head select 3(for WDD)
  542.                                         ;   bit 4  --  head select 2(for WDD)
  543.                                         ;   bit 3  --  head select 1(for WDD)
  544.                                         ;   bit 2  --  head select 0(for WDD)
  545.                                         ;   bit 1  --  drive select 1(for WDD)
  546.                                         ;   bit 0  --  drive select 0(for WDD)
  547.                                         ; for write
  548.                                         ;  bit 7-2  -  reserved
  549.                                         ;  bit 1-0  -  select data rate
  550.                                         ;      00   -  500K data rate
  551.                                         ;      01   -  300 data rate
  552.                                         ;      10   -  250K data rate
  553.                                         ;    else   -  reserved
  554.  
  555. ;
  556. ;
  557. line_ctrl3         equ       3220h
  558. line_ctrl4         equ       3228h
  559. line_ctrl5         equ       4220h
  560. line_ctrl6         equ       4228h
  561. line_ctrl7         equ       5220h
  562. line_ctrl8         equ       5228h
  563.