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1990-01-04
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Appendix C
╔════════════════════════════════════════════════════════╗
║ The specification of Acer BIOS I/O Port Definitions ║
╚════════════════════════════════════════════════════════╝
Contents
--------
A. System I/O Address Map ................................ AT Compatible
B. System I/O Port Definitions ........................... AT Compatible
C. Acer 1100/20/16 model I/O port definition .........1100/20/16 special
D. Acer 1100/25/20C/33 model I/O port definition..1100/25/20c/33 special
E. Acer 1125S model I/O port definition ...................1125S special
F. Acer 1170( 486 AT ) model I/O port definition ...........1170 special
G. Acer 1100SX (p9) model I/O port definition ............1100SX special
H. Acer 1100LX model I/O port definition .................1100LX special
I. Acer 1105 (M1209) model I/O port definition .............1105 special
J. Acer A1, A2 (M1207) model I/O port definition ........A1, A2 special
A. System I/O Address Map
┌─────────────┬─────────────────────────────────────────┬─────────────────┐
│ Port addr. │ Description │ Comment │
├─────────────┼─────────────────────────────────────────┼─────────────────┤
│ 000h - 01Fh │ DMA Controller 1 │ │
│ 020h - 021h │ Interrupt Controller 1, 8259A, Master │ │
│ 022h - 023h │ NEAT chip set controller │For NEAT system │
│ 022h - 023h │ M1209 chip set controller │For 1105 system │
│ 040h - 043h │ System timer │ │
│ 060h │ Keyboard, Auxiliary device │ │
│ 061h │ System control port B │ │
│ 064h │ Keyboard, Auxiliary device │ │
│ 070h - 071h │ RTC/CMOS and NMI Mask │ │
│ 080h - 09Fh │ DMA page Register │ │
│ 0A0h - 0A1h │ Interrupt Controller 2, 8259A, Slave │ │
│ 0C0h - 0DFh │ DMA Controller 2 │ │
│ 0F0h - 0FFh │ Math coprocessor │ │
│ 1ECH - 1EFH │ GC113 Memory Control Register (G2) │For 1100LX only │
│ 1F0H - 1F7H │ Fixed Disk Controller │ │
│ 200h - 207h │ Game port │ │
│ 278h - 27Bh │ Parallel port 3 │ │
│ 2F8h - 2FFh │ Asynchronous communication (RS232C), 2 │ │
│ 35FH │ System control register │For 1100LX only │
│ 36FH │ System control register │For 1100LX only │
│ 378h - 37Bh │ Parallel port 2 │ │
│ 3B4H - 3B5H │ Video Subsystem │ │
│ 3BAH , 3BFH │ .. │ │
│ 3C0H - 3C5H │ .. │ │
│ 3C6H - 3C9H │ Video Digit/Analog Convert │ │
│ 3CAH - 3CCH │ Video Subsystem │ │
│ 3CEH - 3CFH │ Video Subsystem │ │
│ 3D4H - 3D5H │ .. │ │
│ 3D9H - 3DAH │ .. │ │
│ 3BCh - 3BEh │ Parallel port 1 │ │
│ 3F8h - 3FFh │ Asynchronous communication (RS232C), 1 │ │
│ 3F0H - 3F7H │ Diskette Drive Controller │ │
│ 46E8H │ Setup Control Register │ VGA control port│
│ 102H │ Global Enable Register │ VGA control port│
│ 103H │ Extended Enable Register │ VGA control port│
│ 104H │ Global ID Register │ VGA control port│
├─────────────┼─────────────────────────────────────────┼─────────────────┤
│ 02XAH │ Page Frame base address │ M1207 chip set │
│ 02XBH │ ID Code of EMS (R) │ I/O port │
│ 02X8/02X9H │ Page Register 0 for SET 0 │ │
-- to be continued --
│ 42X8/42X9H │ Page Register 1 for SET 0 │ M1207 chip set │
│ 82X8/82X9H │ Page Register 2 for SET 0 │ I/O port │
│ C2X8/C2X9H │ Page Register 3 for SET 0 │ │
│ 12X8/12X9H │ Page Register 0 for SET 1 │ │
│ 52X8/52X9H │ Page Register 1 for SET 1 │ │
│ 92X8/92X9H │ Page Register 2 for SET 1 │ │
│ D2X8/D2X9H │ Page Register 3 for SET 1 │ │
│ 12XAH │ Page Register Data │ │
│ FC80H │ System Clock/Cycle Control Register │ │
│ FC81H │ Memory Control Register 1 │ │
│ FC82H │ Memory Control Register 2 │ │
│ FC83H │ Shadow RAM Control Register 1 │ │
│ FC84H │ Shadow RAM Control Register 2 │ │
│ FC85H │ Extend System Control Register │ │
│ FC86H │ Plannar Control Register 1 │ │
│ FC87H │ Enable Configuration Register Access │ │
│ FC89H │ Refresh Cycle Option Select │ │
└─────────────┴─────────────────────────────────────────┴─────────────────┘
B. System I/O Port Definitions
┌─────────────────────────────────────────────────────────────────────────┐
│ DMA Channel 0-3 Controller (see 8237A data sheet)│
│ │
│ Port 00h For write -- CH0 base and current address │
│ For read -- CH0 current address │
│ │
│ Port 01h For write -- CH0 base and current word count │
│ For read -- CH0 current word count │
│ │
│ Port 02h For write -- CH1 base and current address │
│ For read -- CH1 current address │
│ │
│ Port 03h For write -- CH1 base and current word count │
│ For read -- CH1 current address │
│ │
│ Port 04h For write -- CH2 base and current address │
│ For read -- CH2 current address │
│ │
│ Port 05h For write -- CH2 base and current word count │
│ For read -- CH2 current word count │
│ │
│ Port 06h For write -- CH3 base and current address │
│ For read -- CH3 current address │
│ │
│ Port 07h For write -- CH3 base and current word count │
│ For read -- CH3 current word count │
│ │
│ Port 08h Read Status Register / Write Command Register │
│ │
│ Bit WRITE operation(for channel 0-3) │
│ ---------------------------------------- │
│ 7 DACK active low-/high+ │
│ 6 DREQ active low+/high- │
│ 5 Late-/extended+ write selection │
│ 4 Fixed-/rotating+ priority │
│ 3 Normal-/compressed+ timing │
│ 2 Controller enable- │
│ 1 Channel 0 address hold enable+ │
│ 0 Memory-to memory enable+ │
│ │
│ │
│ │
│ │
│ │
│ -- to be continued -- │
│ │
│ Bit READ operation │
│ ---------------------------------------- │
│ 7 = 1 channel 3 request │
│ 6 = 1 channel 2 request │
│ 5 = 1 channel 1 request │
│ 4 = 1 channel 0 request │
│ 3 = 1 channel 3 has reached TC │
│ 2 = 1 channel 2 has reached TC │
│ 1 = 1 channel 1 has reached TC │
│ 0 = 1 channel 0 has reached TC │
│ │
│ │
│ Port 09h Request Register (WRITE ONLY)│
│ │
│ Port 0Ah Single Mask Register Bit (WRITE ONLY)│
│ Bit │
│ ------------------------------------------ │
│ 2 = 0 clear mask bit │
│ = 1 set mask bit │
│ 1,0 for select channel mask bit │
│ = 00 select channel 0 │
│ = 01 select channel 1 │
│ = 10 select channel 2 │
│ = 11 select channel 3 │
│ Port 0Bh Mode Register, (WRITE ONLY)│
│ Bit │
│ ------------------------------------------ │
│ 7-4 Reserved = 0 │
│ 3,2 = 00 verify transfer │
│ = 01 write transfer │
│ = 10 read transfer │
│ = 11 reserved │
│ 1,0 Channel Select │
│ = 00 select channel 0 │
│ = 01 select channel 1 │
│ = 10 select channel 2 │
│ = 11 select channel 3 │
│ │
│ Port 0Ch Clear Byte Pointer Flip-Flop (WRITE ONLY)│
│ │
│ Port 0Dh Read Temporary Register / Write Master Clear │
│ │
│ Port 0Eh Clears the mask bits of channel 0-3 │
│ Enabling them to accept DMA requests │
│ │
│ │
│ -- to be continued -- │
│
│ Port 0Fh All Mask Register Bits (WRITE ONLY)│
│ Bit │
│ ------------------------------------------ │
│ 7-4 = don't care │
│ 3 = 0 clear channel 3 mask bit │
│ = 1 set channel 3 mask bit │
│ 2 = 0 clear channel 2 mask bit │
│ = 1 set channel 2 mask bit │
│ 1 = 0 clear channel 1 mask bit │
│ = 1 set channel 1 mask bit │
│ 0 = 0 clear channel 0 mask bit │
│ = 1 set channel 0 mask bit │
│ │
└─────────────────────────────────────────────────────────────────────────┘
┌─────────────────────────────────────────────────────────────────────────┐
│ DMA Channel 4-7 Registers (see 8237A data sheet)│
│ --------------------------- │
│ │
│ Port C0h For write -- CH4 base and current address │
│ For read -- CH4 current address │
│ │
│ Port C2h For write -- CH4 base and current word count │
│ For read -- CH4 current word count │
│ │
│ Port C4h For write -- CH5 base and current address │
│ For read -- CH5 current address │
│ │
│ Port C6h For write -- CH5 base and current word count │
│ For read -- CH5 current address │
│ │
│ Port C8h For write -- CH6 base and current address │
│ For read -- CH6 current address │
│ │
│ Port CAh For write -- CH6 base and current word count │
│ For read -- CH6 current word count │
│ │
│ Port CCh For write -- CH7 base and current address │
│ For read -- CH7 current address │
│ │
│ Port CEh For write -- CH7 base and current word count │
│ For read -- CH7 current word count │
│ │
│ Port D0h Read Status Register / Write Command Register │
│ │
│ Bit WRITE operation(for channel 4-7) │
│ ---------------------------------------- │
│ 7 DACK active low-/high+ │
│ 6 DREQ active low+/high- │
│ 5 Late-/extended+ write selection │
│ 4 Fixed-/rotating+ priority │
│ 3 Normal-/compressed+ timing │
│ 2 Controller enable- │
│ 1 Channel 0 address hold enable+ │
│ 0 Memory-to memory enable+ │
│ │
│ │
│ │
│ │
│ │
│ │
│ │
│ -- to be continued -- │
│ Bit READ operation │
│ --------------------------------------- │
│ 7 = 1 channel 7 request │
│ 6 = 1 channel 6 request │
│ 5 = 1 channel 5 request │
│ 4 = 1 channel 4 request │
│ 3 = 1 channel 7 has reached TC │
│ 2 = 1 channel 6 has reached TC │
│ 1 = 1 channel 5 has reached TC │
│ 0 = 1 channel 4 has reached TC │
│ │
│ Port D2h Request Register (WRITE ONLY)│
│ │
│ Port D4h Single Mask Register Bit (WRITE ONLY)│
│ Bit │
│ ------------------------------------------ │
│ 2 = 0 clear mask bit │
│ = 1 set mask bit │
│ 1,0 For select channel mask bit │
│ = 00 --> select channel 4 │
│ = 01 --> select channel 5 │
│ = 10 --> select channel 6 │
│ = 11 --> select channel 7 │
│ │
│ Port D6h Mode Register (WRITE ONLY)│
│ Bit │
│ ------------------------------------------ │
│ 7-4 Reserved = 0 │
│ 3,2 = 00 verify transfer │
│ = 01 write transfer │
│ = 10 read transfer │
│ = 11 reserved │
│ 1,0 Channel Select │
│ = 00 select channel 4 │
│ = 01 select channel 5 │
│ = 10 select channel 6 │
│ = 11 select channel 7 │
│ │
│ Port D8h Clear Byte Pointer Flip-Flop (WRITE ONLY)│
│ │
│ Port DAh Read Temporary Register / Write Master Clear │
│ │
│ Port DCh Clears the Mask Bits of Channel 0-3 │
│ Enabling them to accept DMA requests │
│ │
│ │
│ │
│ -- to be continued -- │
│ │
│ Port DEh All Mask Register Bits (WRITE ONLY)│
│ Bit │
│ ------------------------------------------ │
│ 7-4 Don't care │
│ 3 = 0 clear channel 7 mask bit │
│ = 1 set channel 7 mask bit │
│ 2 = 0 clear channel 6 mask bit │
│ = 1 set channel 6 mask bit │
│ 1 = 0 clear channel 5 mask bit │
│ = 1 set channel 5 mask bit │
│ 0 = 0 clear channel 4 mask bit │
│ = 1 set channel 4 mask bit │
│ │
│ DMA page registers │
│ ------------------ │
│ │
│ Port 87h DMA Channel 0 │
│ Port 83h DMA Channel 1 │
│ Port 81h DMA Channel 2 │
│ Port 82h DMA Channel 3 │
│ Port 8Fh DMA Channel 4 │
│ Port 8Bh DMA Channel 5 │
│ Port 89h DMA Channel 6 │
│ Port 8Ah DMA Channel 7 │
└─────────────────────────────────────────────────────────────────────────┘
┌─────────────────────────────────────────────────────────────────────────┐
│ Interrupt Controller (see 8259A data sheet)│
│ -------------------- │
│ Port 20h A0 set to 0 │
│ For OCW2 │
│ bit 0-2: L0, L1, L2 -- interrupt level │
│ when bit 6 (SL) = 1 │
│ bit 3,4 = 0, 0 │
│ bit 5-7: R, SL, EOI -- for select each │
│ function (R, EOI) or combinations │
│ R: rotate, EOI: end of interrupt │
│ For OCW3 │
│ bit 0-2: RIS, RR, P │
│ bit 3,4 = 0, 1 │
│ bit 5,6: SMM, ESMM -- Special Mask Mode │
│ If ESMM = 1 and SMM = 1 enter S. M. M. │
│ If ESMM = 1 and SMM = 0 revert to Normal │
│ When ESMM = 0, SMM has no effect │
│ Enable Special Mask Mode │
│ If ESMM = 1 enable SMM = 1 or 0 │
│ If ESMM = 0 SMM = x │
│ Port 21h A0 set to 1 │
│ Sets and clears the mask bits in the IMR. │
│ Bit 7-0: M7-M0 represent the 8 mask bits │
│ │
│ Port A0h A0 set to 0 │
│ For OCW2 │
│ bit 0-2: L0, L1, L2 -- interrupt level │
│ when bit 6 (SL) = 1 │
│ bit 3,4 = 0, 0 │
│ bit 5-7: R, SL, EOI -- for select each │
│ Function (R, EOI) or combinations │
│ R: rotate, EOI: end of interrupt │
│ For OCW3 │
│ bit 0-2: RIS, RR, P │
│ bit 3,4 = 0, 1 │
│ bit 5,6: SMM, ESMM -- Special Mask Mode │
│ If ESMM = 1 and SMM = 1 enter S. M. M. │
│ If ESMM = 1 and SMM = 0 revert to Normal │
│ When ESMM = 0, SMM has no effect │
│ Enable Special Mask Mode │
│ If ESMM = 1 enable SMM = 1 or 0 │
│ If ESMM = 0 SMM = x │
│ Port A1h A0 set to 1 │
│ Sets and clears the mask bits in the IMR. │
│ Bit 7-0: M7-M0 represent the 8 mask bits │
└─────────────────────────────────────────────────────────────────────────┘
┌─────────────────────────────────────────────────────────────────────────┐
│ System Timer (see 8254 data sheet)│
│ ------------ │
│ │
│ Port 40h port address of timer 0 (16 bit) │
│ │
│ Port 41h port address of timer 1 (16 bit) │
│ │
│ Port 42h port address of timer 2 (16 bit) │
│ │
│ Port 43h control word register for timer 0,1 and 2 (WRITE ONLY)│
│ Bit │
│ ------------------------------------------ │
│ 7,6 Counter select │
│ = 00 - Select timer 0 │
│ = 01 - Select timer 1 │
│ = 10 - Select timer 2 │
│ = 11 - Read-back command (for READ operation) │
│ * Read-back command format : │
│ Bit │
│ ------------------------------------------ │
│ 5 = 0 Latch count of selected counter(s)│
│ 4 = 0 Latch status of selected counters │
│ 3 = 1 Select counter 2 │
│ 2 = 1 Select counter 1 │
│ 1 = 1 Select counter 0 │
│ 0 reserved = 0 │
│ 5,4 Read/write │
│ 00 - counter latch command (for READ │
│ operation) │
│ 01 - Read/Write low byte │
│ 10 - Read/Write high byte │
│ 11 - Read/Write low byte, then high byte │
│ 3-1 Mode number (00h - 05h) │
│ 0 = 0 count in binary │
│ = 1 count in BCD │
│ │
└─────────────────────────────────────────────────────────────────────────┘
┌─────────────────────────────────────────────────────────────────────────┐
│ 8042 (8041) Keyboard Controller (see 8042 (8041) data sheet)│
│ ------------------------------- │
│ │
│ Note: (1) 8042 support the PS/2 MOUSE and KEYBOARD SECURITY │
│ │
│ (2) 8041 doesn't support the PS/2 MOUSE and KEYBOARD SECURITY │
│ (used for supporting the standard PC/AT-compatible machine)│
│ │
│ (3) Auxiliary Device means the PS/2 MOUSE │
│ │
│ Port 60h Input/Output Buffer for Keyboard and Auxiliary Device │
│ (System control port A) │
│ │
│ * The output buffer is an 8-bit READ ONLY register at Port 60h. │
│ When the output buffer is read, the 8042 uses it to send │
│ information to the system microprocessor. │
│ THE INFORMATION CAN BE SCAN CODES RECEIVED FROM KEYBOARD, DATA │
│ FROM AN AUXILIARY DEVICE, or DATA BYTES THAT RESULT FROM A │
│ COMMAND FROM THE SYSTEM MICROPROCESSOR. │
│ │
│ * The input buffer is an 8-bit WRITE ONLY register at Port 60h. │
│ When the input buffer is written, a flag is set that indicates a│
│ data write.DATA WRITTEN TO PORT 60H IS SENT TO THE KEYBOARD │
│ UNLESS THE 8042 IS EXPECTING A DATA BYTE FOLLOWING A 8042 │
│ COMMAND. Data should be written to the 8042 input buffer only │
│ if the input buffer full bit (bit 1) of Status Port 64h = 0. │ │
│ │
│ Port 64h 8042 Command Port (WRITE) │
│ │
│ * 8042 commands written through port 64h : │
│ . 20-3F read 8042 RAM │
│ # . 20 read 8042 command byte │
│ . 60-7F write 8042 RAM │
│ # . 60 write 8042 command byte │
│ . A4 test password installed │
│ . A5 load security │
│ . A6 enable security │
│ . A7 disable auxiliary device interface │
│ . A8 enable auxiliary device interface │
│ . A9 interface test for auxiliary device 'clock' │
│ and 'data' line │
│ # . AA self test │
│ # . AB interface test for keyboard 'clock'& 'data' line │
│ # . AC reserved (8041: diagonstic dump) │
│ # . AD disable keyboard interface │
│ # . AE enable keyboard interface │
│ │
│ -- to be continued -- │
│ # . C0 read input port │
│ . C1 poll input port low - port 1 bit 0-3, │
│ in status bits 4-7 │
│ . C2 poll input port low - port 1 bit 4-7, │
│ in status bits 4-7 │
│ # . D0 read output port │
│ # . D1 write output port │
│ NOTE: Bit 0 of output port is connected to │
│ system reset. This bit should not be │
│ written low │
│ . D2 write keyboard output buffer │
│ . D3 write auxiliary device output buffer │
│ . D4 write auxiliary device │
│ # . E0 read test inputs │
│ # . F0-FF pulse output port │
│ │
│ Note: (1) The commands that are not marked '#' are not supported by 8041│
│ │
│ (2) The definitions of the command byte (for command 20h & 60h): │
│ Bit For 8042 | For 8041 │
│ ------------------------------------+-------------------------│
│ 7 Reserved = 0 | the same as 8042 │
│ 6 IBM translate mode | the same as 8042 │
│ = 1, 8042 translates the | │
│ incoming scan code to scan | │
│ code set 1. | │
│ = 0, 8042 passes the | │
│ keyboard scan codes | │
│ without translation. | │
│ 5 Disable auxiliary device | IBM PC mode │
│ = 1, disable | = 1, PC keyboard │
│ | interface │
│ = 0, enable | = 0, PC/AT keyboard │
│ | interface │
│ 4 Disable keyboard | the same as 8042 │
│ = 1, disable | │
│ = 0, enable | │
│ 3 Reserved = 0 | Disable inhibit switch │
│ | = 1, disable │
│ | = 0, enable │
│ 2 System flag | the same as 8042 │
│ 1 Enable auxiliary interrupt | Reserved = 0 │
│ = 1, enable | │
│ 0 Enable keyboard interrupt | the same as 8042 │
│ = 1, enable | │
│ │
│ │
│ │
│ │
│ -- to be continued -- │
│ Port 64h 8042 Status Port (READ) │
│ │
│ Bit For 8042 | For 8041 │
│ ----------------------------------+--------------------------- │
│ 7 Parity error | Parity error │
│ 6 General time out | Receive time out │
│ 5 Auxiliary output buffer full | Transmit time out │
│ 4 Inhibit switch | Inhibit switch │
│ 3 Command/data | Command/data │
│ 2 System flag | System flag │
│ 1 Input buffer full | Input buffer full │
│ 0 Output buffer full | Output buffer full │
│ ----------------------------------+--------------------------- │
│ │
│ * PROGRAMMING CONSIDERATION │
│ │
│ . port 64h (status register) can be read at any time │
│ . port 60h should be READ ONLY when the output buffer full │
│ bit in the status register is a 1 │
│ . the auxiliary output buffer full bit in the status register │
│ indicates that the data in port 60h came from the auxiliary │
│ device. this bit is valid only when the output buffer full │
│ bit is a 1 │
│ . port 60h and 64h should be written only when the status │
│ register input buffer full bit and the output buffer full bit │
│ is 0. │
│ . the devices connected to the 8042 should be disabled before │
│ initiating a command that generates output. if output is │
│ generated, any value in the output buffer is overwritten │
│ . an external latch is used to hold the level sensitive IRQ │
│ until an i/o read from address 60h is executed by the system │
│ │
└─────────────────────────────────────────────────────────────────────────┘
┌─────────────────────────────────────────────────────────────────────────┐
│ Real Time Clock / CMOS (see NS146818 data sheet)│
│ ---------------------- │
│ │
│ Port 70h RT/CMOS RAM address and NMI Mask │
│ │
│ Bit │
│ ------------------------------------------ │
│ 7 NMI (WRITE ONLY) │
│ = 0, enable NMI │
│ = 1, disable, NMI is masked off. │
│ This bit is set to 0 by a Power-on reset. │
│ 6 Reserved │
│ 5-0 RT/CMOS RAM address │
│ │
│-------------------------------------------------------------------------│
│ │
│ Port 71h RT/CMOS data port │
│ │
│ * To read RT/CMOS contents, OUT to port 70h to determine │
│ address first, then read from port 71h. │
│ * To write data into RT/CMOS, first determine address by │
│ port 70h, then OUT data to port 71h. │
│ * When performing I/O operations to the RT/CMOS RAM Port 70H │
│ and 71H, interrupts should be inhibited to avoid having │
│ interrupt routines change the CMOS address register before │
│ data is read or write. │
│ * Software sequence for NMI: │
│ The power-on default of the NMI mask is 1 ( NMI disabled). │
│ POST initializes the parity check and channel check state. │
│ Enable NMI and immediately read Port 70H. │
│ * When writing Port 70H to enable/disable an NMI, a read to │
│ Port 70H must be accessed immediately. │
│ │
│NOTE: │
│ The data of CMOS refer to cmos.spc │
│ │
└─────────────────────────────────────────────────────────────────────────┘
┌─────────────────────────────────────────────────────────────────────────┐
│ Hard Disk Control Port │
│ ---------------------- │
│ 1F0h Data Register R/W │
│ 1F1h Error Register R │
│ bit 7 BBK -- bad block mark │
│ bit 6 UNC -- non_correctable data │
│ bit 5 reserved │
│ bit 4 IDNF -- ID not found │
│ bit 3 reserved │
│ bit 2 ABRT -- abort │
│ bit 1 TK0 -- track 0 not found │
│ bit 0 reserved │
│ 1F2h Sector Count Register R/W │
│ The register defines the number of sectors of data │
│ to be read or written. │
│ 1F3h Sector Number Register R/W │
│ This register contains the starting sector nimber │
│ for any disk access. │
│ 1F4h Cylinder Low R/W │
│ The register contains the low order 8 bits of the │
│ starting cylinder number for any disk access. │
│ 1F5h Cylinder High R/W │
│ The register contains the two high order bits of │
│ the starting cylinder number for any disk access. │
│ │
│ 1F6h SDH Register R/W │
│ This register contains the drive and head numbers. │
│ bit 7 reserved │
│ bit 6 0 │
│ bit 5 1 │
│ bit 4 DRV -- drvier selected │
│ 0 -- Fixed disk C │
│ 1 -- Fixed disk D │
│ bit 3 - 0 Head no. │
│ 1F7h Status Register R │
│ This register contains the drive/controller status. │
│ bit 7 busy │
│ bit 6 Ready │
│ bit 5 write fault │
│ bit 4 seek completed │
│ bit 3 data request │
│ bit 2 data corrected │
│ bit 1 index │
│ bit 0 error status │
│ │
│ -- to be continued -- │
│ Command Register W │
│ bit 76543210 command │
│ 0001XXXX recalibrate │
│ 001000LR read sector(s) │
│ 001100LR write sector(s) │
│ 0100000R read ver sector │
│ 01010000 format track │
│ 0111XXXX seek │
│ 10010000 exec. drv diag │
│ 10010001 init drv. params │
│ 1110PPPP power commands │
│ 11100100 read setor buffer │
│ 11101000 write sector buffer │
│ 11101100 identify drive │
│ note: │
│ L -- long bit │
│ R -- retry bit │
│ P -- valid bit for power command │
│ │
│ 3F6h Alternate Status Register R │
│ This register contains the same informatios as the │
│ Status Register in the Task File. │
│ │
│ Digital Output Register W │
│ bit 7 - 3 reserved = 0 │
│ bit 2 s/w reset │
│ bit 1 enable IREQ │
│ bit 0 reserved = 0 │
│ │
│ 3F7h Drive Address Register R │
│ This register loops back the drive select and head │
│ select addresses of currently selected drive. │
│ bit 7 reserved │
│ bit 6 WTG -- write gate │
│ bit 5 - 2 -- HS3 - HS0 │
│ 0011 -- head 3 select │
│ 0010 -- head 2 select │
│ 0001 -- head 1 select │
│ 0000 -- head 0 select │
│ bit 1 DS1 -- drive 1 select │
│ bit 0 DS0 -- drive 0 select │
└─────────────────────────────────────────────────────────────────────────┘
┌─────────────────────────────────────────────────────────────────────────┐
│ Parallel ports │
│ -------------- │
│ │
│ Line printer interface via Intel 8255 with │
│ control signals at base I/O address +2 │
│ status signals at base I/O address +1 │
│ data signals at base I/O address │
│ │
│ ┌──── For 1100SX ────┐ │
│ Port 3BCh-3BEh Parallel Printer Port 1 ├─> Parallel port 3 │ │
│ │ │ │
│ Port 378h-37Ah Parallel Printer Port 2 ├─> Parallel port 1 │ │
│ │ │ │
│ Port 278h-27Ah Parallel Printer Port 3 ├─> Parallel port 2 │ │
│ └─────────────────────┘ │
│ │
│ Control : (3BEh for printer 1, 37Ah for printer 2, 27Ah for printer 3)│
│ (For 1100SX : .. 3 .. 1 .. 2)│
│ Bit │
│ ------------------------------------------ │
│ 4 +IRQ7 enable (interrupt on -ACK true to false) │
│ 3 +SELECT IN (true for printer select) │
│ 2 -INITIALIZE (minimum 50 microsecond true to false pulse) │
│ 1 +AUTO FEED (true makes printer LF after CR) │
│ 0 +STROBE (1/2 microsecond minimum false to true pulse)│
│ │
│ Status : (3BDh for printer 1, 379h for printer 2, 279h for printer 3) │
│ (For 1100SX : .. 3 .. 1 .. 2) │
│ Bit │
│ ------------------------------------------ │
│ 7 -BUSY (true indicates printer may not accept data) │
│ 6 -ACK (false indicates printer ready to accept another │
│ byte) │
│ 5 +PE (true indicates paper out conditions) │
│ 4 +SELECT (true means printer selected) │
│ 3 -ERROR (false means error condition detected) │
│ │
│ Data : (3BCh for printer 1, 378h for printer 2, 278h for printer 3) │
│ (For 1100SX : .. 3 .. 1 .. 2) │
│ │
└─────────────────────────────────────────────────────────────────────────┘
┌─────────────────────────────────────────────────────────────────────────┐
│ Serial Ports │
│ ------------ │
│ │
│ Port 3F8h-3FFh -- Serial Port 1 x = 3 for port 1 │
│ Port 2F8h-2FFh -- Serial Port 2 = 2 for port 2 │
│ │
│ I/O address register selected DLAB state │
│ ----------------------------------------------------------- │
│ xF8h TX buffer 0(write) │
│ xF8h RX buffer 0(read) │
│ xF8h Divisor latch LSB 1 │
│ xF9h Divisor latch MSB 1 │
│ xF9h Interrupt enable register 0 │
│ xFAh Interrupt identification register │
│ xFBh Line control register │
│ xFCh Modem control register │
│ xFDh Line status register │
│ xFEh Modem status register │
│ xFFh Reserved │
│ │
│ Port xF8h - Transmitter Holding Register │
│ Bit │
│ ------------------------------------------ │
│ 7 Data bit 7 │
│ 6 Data bit 6 │
│ 5 Data bit 5 │
│ 4 Data bit 4 │
│ 3 Data bit 3 │
│ 2 Data bit 2 │
│ 1 Data bit 1 │
│ 0 Data bit 0 │
│ │
│ Port xF8h - Receiver Buffer Register │
│ Bit │
│ ------------------------------------------ │
│ 7 Data bit 7 │
│ 6 Data bit 6 │
│ 5 Data bit 5 │
│ 4 Data bit 4 │
│ 3 Data bit 3 │
│ 2 Data bit 2 │
│ 1 Data bit 1 │
│ 0 Data bit 0 │
│ │
│ │
│ │
│ -- to be continued -- │
│ Port xF8h - Divisor Latch LSB │
│ Bit │
│ ------------------------------------------ │
│ 7 Bit 7 │
│ 6 Bit 6 │
│ 5 Bit 5 │
│ 4 Bit 4 │
│ 3 Bit 3 │
│ 2 Bit 2 │
│ 1 Bit 1 │
│ 0 Bit 0 │
│ │
│ Port xF9h - Divisor Latch MSB │
│ Bit │
│ ------------------------------------------ │
│ 7 Bit 7 │
│ 6 Bit 6 │
│ 5 Bit 5 │
│ 4 Bit 4 │
│ 3 Bit 3 │
│ 2 Bit 2 │
│ 1 Bit 1 │
│ 0 Bit 0 │
│ │
│ Port xF9h - Interrupt Enable Register │
│ Bit │
│ ------------------------------------------ │
│ 7-4 Reserved = 0 │
│ 3 Enable receive modem status interrupt │
│ 2 Enable receive line status interrupt │
│ 1 Enable TX holding register empty interrupt │
│ 0 Enable the received-data-available interrupt │
│ │
│ Port xFAh - Interrupt Indentification Register │
│ Bit │
│ ------------------------------------------ │
│ 7-3 Reserved = 0 │
│ 2-1 Interrupt ID │
│ 0 = 0 if interrupt pending │
│ │
│ Bit Priority Interrupt Interrupt Interrupt │
│ 2,1 Level Type Source Reset Control │
│ ---------------------------------------------------------------------- │
│ 1 1 highest receiver line overrun error, reading the line │
│ status parity error, status register │
│ framing error, │
│ break interrupt │
│ │
│ 0 1 second received data receiver data reading the receiver│
│ available available buffer register │
│ │
│ -- to be continued -- │
│ 1 0 third transmitter transmitter read the IIR (if │
│ holding register holding reg. source of interrupt)│
│ empty empty or writing into the │
│ THR │
│ │
│ 0 0 fourth modem status clear to send, reading the modem │
│ data set ready, status register │
│ ring indicator, │
│ received line │
│ signal detect │
│ │
│ Port xFBh - Line Control Register │
│ Bit │
│ --------------------------------------- │
│ 7 Divisor latch access bit │
│ 6 Set break │
│ 5 Stuck parity │
│ 4 Even parity select │
│ 3 Parity enable │
│ 2 Number of stop bits │
│ 1-0 Word length (bit) │
│ = 00 5 bits │
│ = 01 6 bits │
│ = 10 7 bits │
│ = 11 8 bits │
│ │
│ Port xFCh - Modem Control Register │
│ Bit │
│ --------------------------------------- │
│ 7-5 Reserved = 0 │
│ 4 Loop │
│ 3 Out 2 │
│ 2 Out 1 │
│ 1 Request to send │
│ 0 Data terminal ready │
│ Port xFDh - Line Status Register │
│ Bit │
│ --------------------------------------- │
│ 7 Reserved = 0 │
│ 6 TX shift register empty │
│ 5 Transmitter holding register empty │
│ 4 Break interrupt │
│ 3 Framing error │
│ 2 Parity error │
│ 1 Overrun error │
│ 0 Data ready │
│ │
│ -- to be continued -- │
│ │
│ Port xFEh - Modem Status Register │
│ Bit │
│ --------------------------------------- │
│ 7 Data carrier detect │
│ 6 Ring indicator │
│ 5 Data set ready │
│ 4 Clear to sent │
│ 3 Delta data carrier detect │
│ 2 Trailing edge ring indicator │
│ 1 Delta data set ready │
│ 0 Delta clear to send │
│ │
└─────────────────────────────────────────────────────────────────────────┘
┌─────────────────────────────────────────────────────────────────────────┐
│ Diskette ports │
│ -------------- │
│ │
│ Port 3F2h -- Digital output register │
│ Bit │
│ --------------------------------------- │
│ 7,6 Reserved │
│ 5 Drive B motor enable │
│ 4 Drive A motor enable │
│ 3 Enable diskette interrupt and DMA │
│ 2 Diskette function reset │
│ 1 Reserved │
│ 0 Drive select = 0 -- drive A │
│ = 1 -- drive B │
│ │
│ Port 3F4h -- main status register │
│ Bit │
│ -----------------------------------------------------------------│
│ 7 Request for Master (RQM) │
│ Data register is READY to send or receive data │
│ To or from the processor │
│ 6 Data Input/Output (DIO) │
│ = 1 data transfer is from FDC data register to │
│ processor │
│ = 0 data transfer is from processor to FDC data │
│ register │
│ 5 Non-DMA Mode (NDM) │
│ 4 Diskette Controller Busy (CB) │
│ = 1 FDC Busy │
│ 3,2 Reserved = 0 │
│ 1 Diskette drive B busy (DBB) │
│ = 1 -- FDD B Busy │
│ 0 Diskette drive A busy (DAB) │
│ = 1 -- FDD A Busy │
│ │
│ Port 3F5h FDC data register (READ/WRITE) │
│ │
│ Port 3F6h Fixed Disk Register │
│ Bit │
│ ------------------------------------------------------ │
│ 7-4 Reserved │
│ 3 = 0 Enable reduced write current │
│ = 1 Enable head select 3 │
│ 2 = 1 Enable reset fixed disk function │
│ 1 = 0 Enable fixed disk interrupt │
│ 0 Reserved │
│ │
│ * This register is assigned two addresses, 3F6h (primary) and 376h│
│ (secondary). This is a four-bit write only register. │
│ │
│ -- to be continued -- │
│ │
│ Port 3F7h Digital Input Register │
│ │
│ Bit READ operation │
│ ----------------------------------------------- │
│ 7 Diskette change │
│ = 1 active │
│ = 0 inactive │
│ 6-1 Reserved │
│ 0 -high density select │
│ ----------------------------------------------- │
│ │
│ Bit WRITE operation │
│ ----------------------------------------------- │
│ 7-2 Reserved │
│ 1,0 Select data rate (KBit/Second) │
│ = 00 500K (1.2M disk in 1.2M drive) │
│ = 01 300K (360K disk in 1.2M drive) │
│ = 10 250K (360K disk in 360K drive) │
│ Else reserved │
│ │
└─────────────────────────────────────────────────────────────────────────┘
┌─────────────────────────────────────────────────────────────────────────┐
│ Monochrome Graphics and printer adapter │
│ --------------------------------------- │
│ │
│ Port 3B4h MGA index register (WRITE ONLY)│
│ │
│ Port 3B5h MGA data register (READ/WRITE)│
│ │
│ Port 3B8h MGA display mode control (WRITE ONLY)│
│ Bit │
│ ---------------------------------------------------------------- │
│ 7 = 1 Page 1 (Start display at B8000h) │
│ = 0 Page 0 (start display at B0000h) (DEFAULT)│
│ * This bit select the active display buffer on the │
│ graphics card. │
│ 6 Reserved │
│ 5 = 1 turn on the screen blinker │
│ = 0 Turn off the text blinker (DEFAULT)│
│ * This blinker has no effect on the cursor. │
│ Every character whose attribute indicates blinking │
│ will now blink. │
│ 4 Reserved │
│ 3 = 1 Activate the screen │
│ = 0 Blank the screen │
│ * This bit is uesful when changing modes. By keeping the │
│ screen blank for a period of time, the change from text│
│ to graphics mode can be done without any screen bounce.│
│ 2 Reserved │
│ 1 = 1 Graphics mode │
│ = 0 Text mode (DEFAULT)│
│ * The 6845 must be reprogrammed each time this bit │
│ changes value. │
│ 0 Reserved │
│ │
│ Port 3B9h Set light pen flip flop (WRITE ONLY)│
│ │
│ Port 3BAh Display status port (READ ONLY)│
│ Bit │
│ ---------------------------------------------------------------- │
│ 7 = 1 Active display │
│ This information is useful when software wants to │
│ make sure that the screen is blanked) │
│ = 0 Vertical retrace (screen is temporarily blanked) │
│ 6,4 Reserved │
│ │
│ │
│ │
│ │
│ -- to be continued -- │
│ 3 = 1 Dots on │
│ = 0 Dots off │
│ * This bit can be used as a software check point to │
│ verify that the monochrome display is receiving an │
│ active video signal. │
│ 2,1 Reserved │
│ 0 = 1 SYNC (screen is temporaily blanked) │
│ = 0 Normal used │
│ │
│ Port 3BBh Reset light pen flip flop (WRITE ONLY)│
│ │
│ Port 3BFh Configuration switch (WRITE ONLY)│
│ Bit │
│ ---------------------------------------------------------------- │
│ 1 = 1 Bring page 1 into the memory map and allows the │
│ setting of page bit. │
│ = 0 Mask page 1 (B8000h-BFFFFh)out of memory and │
│ prevent setting the page bit (bit 7 of port 3B8h) │
│ (DEFAULT)│
│ 0 = 1 Allows the setting │
│ = 0 Prevents the setting of graphics mode thru bit 1 │
│ of Display Mode Control (3B8h) (DEFAULT)│
│ │
└─────────────────────────────────────────────────────────────────────────┘
┌─────────────────────────────────────────────────────────────────────────┐
│ Color Graphics Adapter │
│ ---------------------- │
│ │
│ Port 3D4h CGA index register (WRITE ONLY)│
│ │
│ Port 3D5h CGA data register (READ/WRITE)│
│ │
│ Port 3D8h CGA display mode control (WRITE ONLY)│
│ Bit │
│ ---------------------------------------------------------│
│ 7,6 Reserved │
│ 5 Enable blink │
│ 4 640 * 200 mono (select mode 6) │
│ 3 Enable video │
│ 2 B & w │
│ 1 Graphics (select mode 4,5) │
│ 0 80 * 25 alpha │
│ │
│ Port 3D9h CGA border control (WRITE ONLY)│
│ Bit │
│ ---------------------------------------------------------│
│ 7,6 Reserved │
│ 5 320 * 200 palette select (for modes 4,5) │
│ 4 Alternate intensity (mode 4,5) │
│ 3-0 Background color (for mode 4,5,6 and 11) │
│ │
│ Port 3DAh CGA status (READ ONLY)│
│ Bit │
│ ---------------------------------------------------------│
│ 7-4 Reserved │
│ 3 Vertical sync. │
│ 2,1 Reserved │
│ 0 Display enable (0) │
│ │
├─────────────────────────────────────────────────────────────────────────┤
│ │
│ Port 200h-207h Game I/O Ports 0-7 │
│ │
├─────────────────────────────────────────────────────────────────────────┤
│ │
│ Port 80h Used as a diagnostic-checkpoint port or register. │
│ (300h) This port corresponds to a read/write register in the │
│ DMA │
│ * This port is used by POST during power up. │
│ │
└─────────────────────────────────────────────────────────────────────────┘
┌─────────────────────────────────────────────────────────────────────────┐
│ Math Coprocessor Controls (WRITE ONLY)│
│ ------------------------- │
│ │
│ Port F0h * An 8-bit out command to this port will clear the latched │
│ Math Coprocessor '-busy' signal. The '-busy' signal will │
│ be latched if the coprocessor asserts its '-error' signal│
│ while it is busy. The data output should be zero. │
│ │
│ Port F1h * An 8-bit output command to this port will reset the │
│ Math Coprocessor. The data output should be zero. │
│ │
├─────────────────────────────────────────────────────────────────────────┤
│ Port 61h System Control Port B │
│ --------------------- │
│ WRITE (output) operation: │
│ Bit │
│ -----------------------------------------------------------│
│ 7-4 Reserved │
│ 3 -Enable I/O Channel Check │
│ 2 -Enable RAM Parity Check │
│ 1 +Speaker Data Enable │
│ 0 +Timer 2 Gate to Speaker │
│ │
│ READ (input) operation: │
│ Bit │
│ -----------------------------------------------------------│
│ 7 +RAM Parity Check │
│ = 1 A memory parity error has occurred. │
│ * A NMI will occur if NMI is enabled. │
│ * The error bit can be reset by toggling output │
│ port 61h,bit 2, to a 1 and then back to 0. │
│ 6 +I/O Channel Check │
│ * A NMI will occur if NMI is enabled. │
│ * The error bit can be reset by toggling output │
│ port 61h, bit 3, to a 1 and then back to 0. │
│ 5 Timer 2 channel output │
│ Reflects the level of the Timer 2 output │
│ 4 Refresh detect │
│ Toggles every 15 µsec, indicating normal │
│ activity. │
└─────────────────────────────────────────────────────────────────────────┘
C. Acer 1100/20/16 model I/O port definition :
┌─────────────────────────────────────────────────────────────────────────┐
│ │
│ Port 28h System Control Port C (WRITE ONLY)│
│ Bit │
│ ---------------------------------------------------------------- │
│ 7-4 Speed Parameter │
│ (higher value --> more delay, lower speed) │
│ │
│ 3 Reserved │
│ │
│ 2 Speed Select │
│ = 1 Enable speed change, │
│ system speed depends on Speed Parameter │
│ = 0 Full speed (don't care speed parameter) │
│ │
│ 1 RAM BIOS write enable <─┐ ┌─────────────────────────┐│
│ = 1 Enable write to RAM │ │ = 00 ROM BIOS ││
│ = 0 Disable ├─┤ = 01 RAM BIOS ││
│ 0 RAM BIOS enable │ │ = 10 ROM read,RAM write ││
│ = 1 Enable RAM BIOS │ │ = 11 RAM BIOS read/write││
│ = 0 Disable RAM BIOS <─┘ └─────────────────────────┘│
│ │
│ Port 329h System Control Port D (WRITE ONLY)│
│ │
│ Bit 1 = 1 Bypass │
│ = 0 Force Gate A20 to low │
│ │
│ Other Bit -- Reserved │
│ │
│ * Gate A20 is a special design for AT-compatibles. In real │
│ address mode, it prevents address line A20 from being set, │
│ maintaining compatibility with 8088 programs. When in │
│ protected mode, Gate A20 allows addressing above the 1 MB │
│ range. │
│ * As it is traditionally implemented by a low-performance 8042, │
│ we now offer another way to do it. But for our machines with │
│ Fast Gate A20, while this Gate is LOW, the original │
│ programming skill for 8042's Gate A20 still works. And then │
│ this Fast Gate deserves as a better choice, especially for │
│ enormous swaping between Real and Protected modes. │
│ │
└─────────────────────────────────────────────────────────────────────────┘
D. Acer 1100/25/20C/33 model I/O port definition :
┌─────────────────────────────────────────────────────────────────────────┐
│ │
│ Port 328h System Control Port C (WRITE ONLY)│
│ Bit │
│ ---------------------------------------------------------------- │
│ 7-5 Speed Parameter │
│ (higher value --> more delay, lower speed) │
│ │
│ 4 Flush cache │
│ │
│ 3 Cache control │
│ = 1 cache enabled │
│ = 0 cache disabled │
│ │
│ 2 Speed Select │
│ = 1 Enable speed change, │
│ system speed depends on Speed Parameter │
│ = 0 Full speed (don't care speed parameter) │
│ │
│ 1 RAM BIOS write enable <─┐ ┌─────────────────────────┐│
│ = 1 Enable write to RAM │ │ = 00 ROM BIOS ││
│ = 0 Disable ├─┤ = 01 RAM BIOS ││
│ 0 RAM BIOS enable │ │ = 10 ROM read, RAM write││
│ = 1 Enable RAM BIOS │ │ = 11 RAM BIOS read/write││
│ = 0 Disable RAM BIOS <─┘ └─────────────────────────┘│
│ │
│ │
│ Port 329h System Control Port D (WRITE ONLY)│
│ │
│ Bit 1 = 1 Bypass │
│ = 0 Force Gate A20 to low │
│ │
│ Other Bit -- Reserved │
│ │
│ * Gate A20 is a special design for AT-compatibles. In real │
│ address mode, it prevents address line A20 from being set, │
│ maintaining compatibility with 8088 programs. When in │
│ protected mode, Gate A20 allows addressing above the 1 MB │
│ range. │
│ * As it is traditionally implemented by a low-performance 8042, │
│ we now offer another way to do it. But for our machines with │
│ Fast Gate A20, while this Gate is LOW, the original │
│ programming skill for 8042's Gate A20 still works. And then │
│ this Fast Gate deserves as a better choice, especially for │
│ enormous swaping between Real and Protected modes. │
│ │
│ * PROGRAMMING CONSIDERATION │
│ │
│ . Cache system is supported by INT 16h in BIOS : │
│ │
│ INT 16h : AH = F4h, AL = 1 -- Cache On │
│ INT 16h : AH = F4h, AL = 2 -- Cache Off │
│ │
└─────────────────────────────────────────────────────────────────────────┘
E. Acer 1125S model I/O port definition :
┌─────────────────────────────────────────────────────────────────────────┐
│ System Control Ports │
│ -------------------- │
│ │
│ Port 326h System Control Port D (READ/WRITE)│
│ │
│ Memory bank disable/enable register │
│ │
│ Bit │
│ ---------------------------------------------------------│
│ 7 Disable/enable bank 7 │
│ = 1 Disable bank 7 memory │
│ = 0 Enable bank 7 memory │
│ │
│ 6 Disable/enable bank 6 │
│ = 1 Disable bank 6 memory │
│ = 0 Enable bank 6 memory │
│ │
│ 5 Disable/enable bank 5 │
│ = 1 Disable bank 5 memory │
│ = 0 Enable bank 5 memory │
│ │
│ 4 Disable/enable bank 4 │
│ = 1 Disable bank 4 memory │
│ = 0 Enable bank 4 memory │
│ │
│ 3 Disable/enable bank 3 │
│ = 1 Disable bank 3 memory │
│ = 0 Enable bank 3 memory │
│ │
│ 2 Disable/enable bank 2 │
│ = 1 Disable bank 2 memory │
│ = 0 Enable bank 2 memory │
│ │
│ 1 Disable/enable bank 1 │
│ = 1 Disable bank 7 memory │
│ = 0 Enable bank 7 memory │
│ │
│ 0 Disable/enable bank 0 │
│ = 1 Disable bank 0 memory │
│ = 0 Enable bank 0 memory │
│ │
-- To be continued --
│ │
│ Port 327h System Control Port E (READ/WRITE)│
│ │
│ Bit │
│ ---------------------------------------------------------│
│ 7 COM port assign │
│ = 1 COM2 = 2F8h │
│ = 0 COM1 = 3F8h │
│ │
│ 6,5 Parallel Port Selection │
│ = 00 LPT1 │
│ = 01 LPT2 │
│ = 10 LPT3 │
│ = 11 Parallel port disable │
│ │
│ 4 Serial Port 1 Enable/Disable │
│ = 1 Disable │
│ = 0 Enable │
│ 3 Serial Port 2 Enable/Disable │
│ = 1 Disable │
│ = 0 Enable │
│ 2 Hard Disk Driver Enable/Disable │
│ = 1 Disable │
│ = 0 Enable │
│ 1 Floppy Driver Enable/Disable │
│ = 1 Disable │
│ = 0 Enable │
│ 0 Move out memory Enable/Disable │
│ = 1 Disable move out memory │
│ = 0 Enable move out memory │
│ │
│ │
│ │
│ │
│ │
│ │
-- To be continued --
│ Port 328h System Control Port C (WRITE ONLY)│
│ Bit │
│ ---------------------------------------------------------------- │
│ 7-5 Speed Parameter │
│ (higher value --> more delay, lower speed) │
│ │
│ 4 Flush cache │
│ │
│ 3 Cache control │
│ = 1 cache enabled │
│ = 0 cache disabled │
│ │
│ 2 Speed Select │
│ = 1 Enable speed change, │
│ system speed depends on Speed Parameter │
│ = 0 Full speed (don't care speed parameter) │
│ │
│ 1 RAM BIOS write enable <─┐ ┌─────────────────────────┐│
│ = 1 Enable write to RAM │ │ = 00 ROM BIOS ││
│ = 0 Disable ├─┤ = 01 RAM BIOS ││
│ 0 RAM BIOS enable │ │ = 10 ROM read, RAM write││
│ = 1 Enable RAM BIOS │ │ = 11 RAM BIOS read/write││
│ = 0 Disable RAM BIOS <─┘ └─────────────────────────┘│
│ │
│ │
│ Port 329h System Control Port D (WRITE ONLY)│
│ │
│ Bit 1 = 1 Bypass │
│ = 0 Force Gate A20 to low │
│ │
│ Other Bit -- Reserved │
│ │
│ * Gate A20 is a special design for AT-compatibles. In real │
│ address mode, it prevents address line A20 from being set, │
│ maintaining compatibility with 8088 programs. When in │
│ protected mode, Gate A20 allows addressing above the 1 MB │
│ range. │
│ * As it is traditionally implemented by a low-performance 8042, │
│ we now offer another way to do it. But for our machines with │
│ Fast Gate A20, while this Gate is LOW, the original │
│ programming skill for 8042's Gate A20 still works. And then │
│ this Fast Gate deserves as a better choice, especially for │
│ enormous swaping between Real and Protected modes. │
│ │
│ * PROGRAMMING CONSIDERATION │
│ │
│ . Cache system is supported by INT 16h in BIOS : │
│ │
│ INT 16h : AH = F4h, AL = 1 -- Cache On │
│ INT 16h : AH = F4h, AL = 2 -- Cache Off │
└─────────────────────────────────────────────────────────────────────────┘
F. Acer 1170( 486 AT ) model I/O port definition :
┌─────────────────────────────────────────────────────────────────────────┐
│ Port 328h System Control Port C (WRITE ONLY)│
│ │
│ Bit │
│ ----------------------------------------------- │
│ 7 = 1 0fc000-0ffffffh as on board DRAM │
│ and cacheable │
│ = 0 0fc000-0ffffffh as not on board DRAM │
│ and uncacheable │
│ 6 = 1 Enable I/O recovery │
│ = 0 Disable I/O recovery │
│ 5 = 1 Select IRQ 5 as printer interrupt │
│ = 0 Select IRQ 7 as printer interrupt │
│ 3-4 = Reserved │
│ 2 = 1 Enable CPU down speed │
│ 0 Full speed │
│ 1 = 1 Enable move out memory │
│ = 0 Disable move out memory │
│ 0 = 1 Enable RAMBIOS │
│ = 0 Disable RAMBIOS │
│ │
│ Port 329h System Control Port D (WRITE ONLY)│
│ │
│ Bit 1 = 1 Bypass │
│ = 0 Force Gate A20 to low │
│ Other Bit -- Reserved │
│ │
│ Port 32Ah System Speed (WRITE ONLY)│
│ Bit │
│ 7-0 Scale system speed to 256 level │
│ │
│ Port 32Bh System Control Port F (READ/WRITE)│
│ Bit │
│ 7 = 1 Serial port 1 as COM2 │
│ Serial port 2 as COM1 │
│ = 0 Serial port 1 as COM1 │
│ Serial port 2 as COM2 │
│ 6 = 1 Enable COM1 │
│ = 0 Disable COM1 │
│ 5 = 1 Enable COM2 │
│ = 0 Disable COM2 │
│ 4 = 1 Enable printer │
│ = 0 Disable printer │
│ 3 = 1 Select parallel port 1 │
│ 0 Select parallel port 2 │
│ 2 = 1 Disable on board FDC │
│ = 0 Enable on board FDC │
│ 1 = 1 Disable on board embeded HDC │
│ = 0 Enable on board embeded HDC │
│ 0 = 1 Normal │
│ = 0 Clear UPS │
└─────────────────────────────────────────────────────────────────────────┘
G. Acer 1100SX (p9) model I/O port definition :
┌─────────────────────────────────────────────────────────────────────────┐
│ Port 329h System Control Port D (WRITE ONLY)│
│ │
│ Bit │
│ ---------------------------------------------------------------- │
│ 7-4 Reserved = 0 │
│ 3 Bank B enable │
│ = 1 Enable │
│ = 0 Disable │
│ 2 Memory Map out │
│ = 1 Enable │
│ = 0 Disable │
│ 1 Bank B Size Select │
│ = 1 4M bytes │
│ = 0 1M bytes │
│ 0 Bank A Size Select │
│ = 1 4M bytes │
│ = 0 1M bytes │
│ │
│ Port 37Fh System Control Port E (READ/WRITE)│
│ │
│ Bit │
│ ---------------------------------------------------------------- │
│ 7 Parallel Port Bidirection Select │
│ = 1 Disable parallel port bidirection │
│ = 0 Enable parallel port bidirection │
│ │
│ 6,5 Parallel Port Selection │
│ = 00 LPT1 │
│ = 01 LPT2 │
│ = 10 LPT3 │
│ = 11 Parallel port disable │
│ │
│ 4 Serial Port 1 Enable/Disable │
│ = 1 Disable │
│ = 0 Enable │
│ 3 Serial Port 2 Enable/Disable │
│ = 1 Disable │
│ = 0 Enable │
│ 2 Hard Disk Driver Enable/Disable │
│ = 1 Disable │
│ = 0 Enable │
│ 1 Floppy Driver Enable/Disable │
│ = 1 Disable │
│ = 0 Enable │
│ 0 VGA Enable/Disable │
│ = 1 Disable VGA Function │
│ = 0 Enable VGA Function │
└─────────────────────────────────────────────────────────────────────────┘
H. Acer 1100LX model I/O port definition :
┌─────────────────────────────────────────────────────────────────────────┐
│ │
│Port 36Fh SYSTEM POWER CONTROL (read/write) │
│ │
│ Bit │
│ ---------------------------------------------------------------- │
│ 0 = 0 Hard disk +12V OFF │
│ 1 Hard disk +12V ON │
│ │
│ 1 = 0 Hard disk +5V OFF │
│ 1 Hard disk +5V ON │
│ │
│ 2 = 0 Floppy disk +5V OFF │
│ 1 Floppy disk +5V ON │
│ │
│ 3 = 0 LCD +5V OFF │
│ 1 LCD +5V ON │
│ │
│ 4 = 0 LCD Backlight +12V OFF │
│ 1 LCD Backlight +12V ON │
│ │
│ 5 = 0 LCD -23V OFF │
│ 1 LCD -23V ON │
│ │
│ 6 = 0 Modem +5V OFF │
│ 1 Modem +5V ON │
│ │
│ 7 = 0 Use external keyboard │
│ 1 Use internal keyboard │
│ │
│Port 35Fh SYSTEM STATUS REGISTER (read) │
│ │
│ 0 = 0 Normal status │
│ 1 Battery low level 1 │
│ │
│ 1 = 0 Normal status │
│ 1 Battery low level 2 │
│ │
│ 2 = Monitor sense bit │
│ │
│ 3 = 0 System power use AC adapter │
│ 1 System power use Battery │
│ │
│ │
│ │
│ │
│ -- to be continued -- │
│ │
│ 4 = 0 Stand-by LED OFF │
│ 1 Stand-by LED ON │
│ │
│ 5 = N/A │
│ │
│ 6 = N/A │
│ │
│ 7 = 0 Normal status │
│ 1 Stand-by button pressed │
│ │
│Port 35Fh SYSTEM CONTROL (write) │
│ │
│ 0 = 0 Low speed │
│ 1 High speed │
│ │
│ 1 = N/A │
│ │
│ 2 = 0 Normal status │
│ 1 Turn off DC/DC converter ===> power off │
│ │
│ 3 = 0 Enable NMI generated │
│ 1 Clear NMI status │
│ │
│ 4 = 0 Turn OFF stand-by LED │
│ 1 Turn ON stand-by LED │
│ │
│ 5 = N/A │
│ │
│ 6 = N/A │
│ │
│ 7 = N/A │
│ │
└─────────────────────────────────────────────────────────────────────────┘
-- to be continued --
┌─────────────────────────────────────────────────────────────────────────┐
│ ╔════════════════════════════════════╗ │
│ ║ GC113 Memory Control Register (G2) ║ │
│ ╚════════════════════════════════════╝ │
│ │
│ NOTE: G2 chip set is used only on Acer 1100LX only │
│ │
│port 1ECH Map Register ( 10bit R/W) │
│ bit Meanning │
│ D9 Bank Enable │
│ D8,D7 Bank select │
│ 0 0 Bank 0 │
│ 0 1 Bank 1 │
│ 1 0 Bank 2 │
│ 1 1 Bank 3 │
│ D6 - D0 Translated address bit │
│port 1EDH Control Register Index (R/W) │
│ bit Meanning │
│ D7 - D2 Reserved │
│ D1,D0 Control register select index at 1EFH │
│ 0 0 control register 0 │
│ 0 1 control register 1 │
│ 1 0 control register 2 │
│ 1 1 control register 3 │
│port 1EEH Map Address Register │
│ bit Meanning │
│ D7 Auto-increment enable │
│ 0 disable │
│ 1 enable │
│ D6 EMS Page Write Protect │
│ 0 not write protect │
│ 1 write protect │
│ D5 Context Selection │
│ 0 standard context │
│ 1 alternate context │
│ D4 - D0 Page selection │
│ 4 3210 page │
│ 0 0000 40000-43fffh 256k - 272k │
│ 0 0001 44000-47fffh 272k - │
│ 0 0010 48000-4bfffh 288k - │
│ 0 0011 4c000-4ffffh 304k - 320k │
│ │
│ 0 0100 50000-53fffh 320k - │
│ 0 0101 54000-57fffh 336k - │
│ 0 0110 58000-5bfffh 352k - │
│ 0 0111 5c000-5ffffh 368k - 384k │
│ │
│ │
-- to be continued --
│ │
│ 0 1000 60000-63fffh 384k - │
│ 0 1001 64000-67fffh 400k - │
│ 0 1010 68000-6bfffh 416k - │
│ 0 1011 6c000-6ffffh 432k - 448k │
│ │
│ │
│ ..... ...... │
│ │
│ 1 1000 c0000-c3fffh 768k - │
│ 1 1001 c4000-c7fffh 784k - │
│ 1 1010 c8000-cbfffh 800k - │
│ 1 1011 cc000-cffffh 816k - 832k │
│ │
│ 1 1100 d0000-d3fffh 832k - │
│ 1 1101 d4000-d7fffh 848k - │
│ 1 1110 d8000-dbfffh 864k - │
│ 1 1111 dc000-dffffh 880k - 896k │
│port 1EFH Control Register 0 (8bit R/W) │
│ bit Meanning │
│ D7 RAM type │
│ 0 256K (default) │
│ 1 1M │
│ D6,D5 No. of DRAM banks enable │
│ 0 0 1 │
│ 0 1 2 │
│ 1 0 3 │
│ 1 1 4 │
│ D4 Shadow Enable F0000h and FF0000h │
│ 0 disable │
│ 1 enable │
│ │
│ Note: program Map Register with value : │
│ │
│ 256k RAM 1M RAM │
│ │
│ 02 9c 02 3c │
│ 02 9d 02 3d │
│ 02 9e 02 3e │
│ 02 9f 02 3f │
│ │
│ │
│ D3 Shadow Enable E0000h and FE0000h │
│ 0 disable │
│ 1 enable │
│ │
│ Note: program Map Register with value : │
│ │
-- to be continued --
│ │
│ 256k RAM 1M RAM │
│ │
│ 02 98 02 38 │
│ 02 90 02 39 │
│ 02 9a 02 3a │
│ 02 9b 02 3b │
│ D2 Extra 384K Disable │
│ 0 disable │
│ 1 enable │
│ D1 Global EMS Enable │
│ 0 disable │
│ 1 enable │
│ D0 context Selection │
│ 0 standard context │
│ 1 alternate context │
│port 1EFH Control Register 1 (8bit R/W) │
│ D7 Page Mode Enable │
│ 0 disable │
│ 1 enable │
│ D6 Mix Dram type Mode Register │
│ 0 same type all four bank │
│ 1 first banks one type, other type last two │
│ banks │
│ D5 - D3 RAS Precharge Timing (PROCCLK) │
│ 0 0 0 8 │
│ 0 0 1 7 │
│ 0 1 0 6 │
│ 0 1 1 5 │
│ 1 0 0 4 │
│ 1 0 1 3 │
│ 1 1 0 2 │
│ D2 - D0 RAS Active Timeout (PROCCLK) │
│ 0 0 0 900 │
│ 0 0 1 780 │
│ 0 1 0 660 │
│ 0 1 1 540 │
│ 1 0 0 420 │
│ 1 0 1 200 │
│ 1 1 0 180 │
│ 1 1 1 60 │
│port 1EFH Control Register 2 (8bit R/W) │
│ D7, D6 CAS Active to Data Ready Delay (PROCCLK) │
│ 0 0 4 │
│ 0 1 3 │
│ 1 0 2 │
│ 1 1 1 │
│ D5, D4 Page Mode │
│ D5 - 0 Memory cannot function zero wait states │
│ 1 Assert zero wait state all non-page mode │
│ memory cycles. │
│ D4 - 0 Page mode operation without asserting zero │
│ wait state. │
│ 1 Page mode operation with zero wait state │
│ when data valid. │
│ │
-- to be continued --
│ D3, D2 CAS Precharge Time (PROCCLK) │
│ 0 0 4 │
│ 0 1 3 │
│ 1 0 2 │
│ 1 1 1 │
│ D1, D0 CAS Active Time (PROCCLK) │
│ 0 0 4 │
│ 0 1 3 │
│ 1 0 2 │
│ 1 1 1 │
│port 1EFH Control Register 3 (8bit R/W) │
│ D7 - D0 External Expansion RAM │
│port ???? RAM Control Register │
│ D0 CAS Precharge │
│ 0 2 procclk │
│ 1 3 procclk │
│ D2, D1 RAS Precharge │
│ 0 0 3 procclk │
│ 0 1 4 procclk │
│ 1 0 5 procclk │
│ 1 1 6 procclk │
│ D3 Reserved │
│ D7 - D4 RAS Timeout Load Value │
│port ???? Memory Control Sequencer (16 R/W bits I/O) │
│ D4 - D0 Jump Address Field │
│ D7 - D5 Jump Test Selector │
│ 0 0 0 Unconditional JUM (JMP) │
│ 0 0 1 REFRESH │
│ 0 1 0 RAS TIMEOUT/HLD ACK/PAGE MISS(RTH) │
│ 0 1 1 TREG1 - CAS precharge/active │
│ 1 0 0 TREG2 │
│ 1 0 1 TREG3 │
│ 1 1 0 TREG4 │
│ 1 1 1 Do Not Jump(NOJ) │
│ D10 - D8 Command Enable │
│ 0 0 0 Unconditional Command (COM) │
│ 0 0 1 REFRESH │
│ 0 1 0 RAS TIMEOUT/HLD ACK/PAGE MISS(RTH) │
│ 0 1 1 TREG1 - CAS precharge/active │
│ 1 0 0 TREG2 │
│ 1 0 1 TREG3 │
│ 1 1 0 TREG4 │
│ 1 1 1 Clear All Commands IF Jump │
│ D11 Hold/Step Select │
│ 0 Hold for S0/S1 Our Page │
│ 1 Step Unconditionally unless Jump │
│ D15 - D12 Control Register values to be Loaded if │
│ Command Enable. │
│ D12 DRAS - RAS Register Value │
│ D13 DMUX - MUX Register Value │
│ D14 DRDY - RDY Register Value │
│ D15 DCAS - CAS Register Value │
└─────────────────────────────────────────────────────────────────────────┘
I. Acer 1105 (M1209) model I/O port definition :
┌─────────────────────────────────────────────────────────────────────────┐
│ Port 37Fh System Control Port E (READ/WRITE)│
│ │
│ Bit │
│ ---------------------------------------------------------------- │
│ 7 Parallel Port Bidirection Select │
│ = 1 Disable parallel port bidirection │
│ = 0 Enable parallel port bidirection │
│ │
│ 6,5 Parallel Port Selection │
│ = 00 LPT1 │
│ = 01 LPT2 │
│ = 10 LPT3 │
│ = 11 Parallel port disable │
│ │
│ 4 Serial Port 1 Enable/Disable │
│ = 1 Disable │
│ = 0 Enable │
│ 3 Serial Port 2 Enable/Disable │
│ = 1 Disable │
│ = 0 Enable │
│ 2 Hard Disk Driver Enable/Disable │
│ = 1 Disable │
│ = 0 Enable │
│ 1 Floppy Driver Enable/Disable │
│ = 1 Disable │
│ = 0 Enable │
│ 0 VGA Enable/Disable │
│ = 1 Disable VGA Function │
│ = 0 Enable VGA Function │
│ │
└─────────────────────────────────────────────────────────────────────────┘
-- to be continued --
┌─────────────────────────────────────────────────────────────────────────┐
│ ╔════════════════════════════════╗ │
│ ║ M1209 chip I/O port definition ║ │
│ ╚════════════════════════════════╝ │
│ │
│ Port 22h M1209 chip set Index register │
│ This port is a write only port, the data input/output │
│ to/from M1209 chip set should be through port 23h and │
│ index by port 22h. │
│ Port 23h M1209 chip set Data register │
│ │
│ Index No. 10h -- DRAM Configuration Register │
│ 11h -- Miscellaneous register │
│ 12h -- Split register │
│ 13h -- Lock register │
│ │
│ 10h -- DRAM Configuration Register │
│ bit means │
│ 7-4 DRAM type │
│ bank0 bank1 bank2 bank3 │
│ 0000 256k 256k 1M 1M │
│ 0001 256k (default) │
│ 0010 256k 256k │
│ 0011 256k 256k 256k 256k │
│ 0100 1M 1M 256k 256k │
│ 0101 1M │
│ 0110 1M 1M │
│ 0111 1M 1M 1M 1M │
│ 1000 256k 256k 1M │
│ 3 Shadow RAM read only Enable/Disable ( 0E0000H - 0FFFFFH) │
│ 0 -- disable (default) │
│ 1 -- enable │
│ 2 Shadow RAM write only Enable/Disable ( 0E0000H - 0FFFFFH)│
│ 0 -- disable (default) │
│ 1 -- enable │
│ 1 Shadow RAM Enable/Disable (at 0E0000H - 0FFFFFH) │
│ 0 -- disable (default) │
│ 1 -- enable │
│ 0 ROM size │
│ 0 -- 64KB ROM/EPROM │
│ 1 -- 128KB ROM/EPROM │
│ │
│ │
│ │
│ │
│ │
-- to be continued --
│ 11h -- Miscellaneous Register │
│ bit means │
│ 7 Turbo# │
│ 0 -- CPU at maximal performance (20 Mhz) │
│ 1 -- Slowdown CPU (8 Mhz) │
│ 6 Wait │
│ 0 -- Normal Wait state │
│ 1 -- Add on more wait state to local memory access │
│ 5 Enable Time-out │
│ 0 -- Disable RAS time-out │
│ 1 -- Enable RAS time-out │
│ 4 Fast Page mode DRAM │
│ 0 -- Minimal CAS precharge time is 1/2 T │
│ 1 -- Minimal CAS precharge time is 1 T │
│ 3 Speed │
│ 0 -- CPU running at 20 MHZ │
│ 1 -- CPU running at 16 MHZ │
│ 2-0 Reserved │
│ │
│ 12h -- Split Register │
│ bit means │
│ 7-4 Local DRAM(256/384 KB) split addr. │
│ 0000 Illeagal │
│ 0001 1M (default) │
│ 0010 2M │
│ 0011 3M │
│ : : │
│ 1111 15M │
│ 3-0 Deturbo Waits │
│ 0000 Illeagal │
│ 0001 2 Waits │
│ 0010 4 Waits │
│ 0011 3 Waits │
│ 0100 8 Waits │
│ 0101 7 Waits │
│ 0110 5 Waits │
│ 0111 6 Waits │
│ 1000 16 Waits │
│ 1001 15 Waits │
│ 1010 13 Waits │
│ 1011 14 Waits │
│ 1100 9 Waits │
│ 1101 10 Waits │
│ 1110 12 Waits │
│ 1111 11 Waits │
│ 13h -- Lock Register │
│ = C5h -- memory configuration registers can be read/write │
│ = others -- Only lock register can be written │
└─────────────────────────────────────────────────────────────────────────┘
J. Acer A1, A2 (M1207) model I/O port definition :
┌─────────────────────────────────────────────────────────────────────────┐
│ ╔════════════════════════════════╗ │
│ ║ M1207 chip I/O port definition ║ │
│ ╚════════════════════════════════╝ │
│ │
│02XA Page Frame base address (R/W) │
│ D3 D2 D1 D0 Starting Addr. of Page Frame │
│ 0 0 0 0 = C0000, C4000, C8000, CC000 │
│ 0 0 0 1 = C4000, C8000, CC000, D0000 │
│ 0 0 1 0 = C8000, CC000, D0000, D4000 │
│ 0 0 1 1 = CC000, D0000, D4000, D8000 │
│ 0 1 0 0 = D0000, D4000, D8000, DC000 │
│ 0 1 0 1 = D4000, D8000, DC000, E0000 │
│ 0 1 1 0 = D8000, DC000, E0000, E4000 │
│ 0 1 1 1 = DC000, E0000, E4000, E8000 │
│ 1 0 0 0 = E0000, E4000, E8000, EC000 │
│ │
│ D4 - D5 Reserved │
│ D6 Wait State for EMS Access through D-type Page Reg. │
│ D6 Wait State │
│ 0 0 wait │
│ 1 1 wait │
│ D7 Global Enable/Disable all I/O ports │
│ = 0 disable │
│ = 1 enable │
│ │
│02XB ID Code of EMS (R) │
│ default = 0C1h │
│ │
│02X8/02X9 Page Register 0 for SET 0 │
│42X8/42X9 Page Register 1 for SET 0 │
│82X8/82X9 Page Register 2 for SET 0 │
│C2X8/C2X9 Page Register 3 for SET 0 │
│ D6 - D0 = Low bits of page number │
│ D7 = Enable/Disable of mapping │
│ 0 disable │
│ 1 enable │
│ D10 - D8 = High bits of page number │
│ D15 - D11 = Reserved │
│12X8/12X9 Page Register 0 for SET 1 │
│52X8/52X9 Page Register 1 for SET 1 │
│92X8/92X9 Page Register 2 for SET 1 │
│D2X8/D2X9 Page Register 3 for SET 1 │
│ │
│ │
│ │
-- to be continued --
│ D6 - D0 = Low bits of page number │
│ D7 = Enable/Disable of mapping │
│ 0 disable │
│ 1 enable │
│ D10 - D8 = High bits of page number │
│ D15 - D11 = Reserved │
│ │
│12XA Page Index for Page Register │
│ D6 - D0 = Page index │
│ D7 = Reserved │
│12XB Page Register Data │
│ D6 - D0 = Low bits of page number │
│ │
│FC80 System Clock/Cycle Control Register │
│ D2 D1 D0 PROCLK SYSCLK │
│ 0 X X CLK2IN/2 CLK2IN/4 │
│ 1 0 1 CLK2IN CLK2IN/2 │
│ 1 1 0 CLK2IN CLK2IN/4 │
│ 1 1 1 CLK2IN ATCLK/2 │
│ D4 D3 = 16bit AT Cycle Wait Status Gen. │
│ 0 0 3 waits │
│ 0 1 2 waits │
│ 1 0 1 waits │
│ 1 1 0 waits │
│ D6 D5 = 8 bit AT Cycle Wait States Gen. │
│ 0 0 5 waits │
│ 0 1 4 waits │
│ 1 0 3 waits │
│ 1 1 2 waits │
│ D7 Reserved │
│ Default = X000000 │
│ │
│FC81 Memory Control Register 1 │
│ D1 D0 = ROM Wait States │
│ 0 0 3 waits │
│ 0 1 2 waits │
│ 1 0 1 waits │
│ 1 1 0 waits │
│ D2 = RAM Wait States │
│ 0 1 wait │
│ 1 0 wait │
│ D5 D4 D3 DRAM Type │
│ 0 0 0 1 │
│ 0 0 1 2 │
│ 0 1 0 3 │
│ 0 1 1 4 │
│ │
│ │
-- to be continued --
│ 1 0 0 5 │
│ 1 0 1 6 │
│ 1 1 0 7 │
│ 1 1 1 8 │
│ D6 = 640K Base Memory Enable │
│ 0 512K │
│ 1 640K │
│ D7 = Page/Interleave Mode Enable │
│ 0 Disable │
│ 1 Enable │
│ Default = 00000000 │
│FC82 Memory Control Register 2 │
│ D0 = 8/16bit BIOS ROM Select │
│ 0 16bit │
│ 1 8bit │
│ D2 D1 = Bank Parity Check Error │
│ 0 0 Bank 0 │
│ 0 1 Bank 1 │
│ 1 0 Bank 2 │
│ 1 1 Bank 3 │
│ D3 = Enable/Disable Parity bit Check │
│ 0 Enable │
│ 1 Disable │
│ D4 = Delay 1/2 CLK2 for RAS durung Noninterleave │
│ Memory Access │
│ 0 ON │
│ 1 OFF │
│ D6 D5 = Mode Select for Noninterleave │
│ 0 0 Mode 1 -- Starting RAS at Falling Edge of CLK2 │
│ 0 1 Mode 2 -- at Rising Edge of CLK2 │
│ 1 0 mode 3 -- Using Delay Line for CAS │
│ D7 = Mode Select for Interleave │
│ 0 Normal Mode │
│ 1 Advance Mode │
│FC83 Shadow RAM Control Register 1 │
│ D0 = 0A0000 - 0AFFFF Enable/Disable │
│ D1 = 0B0000 - 0BFFFF Enable/Disable │
│ D2 = 0C0000 - 0CFFFF Enable/Disable │
│ D3 = 0D0000 - 0DFFFF Enable/Disable │
│ D4 = 0E0000 - 0EFFFF Enable/Disable │
│ D5 = 0F0000 - 0FFFFF Enable/Disable │
│ 0 Disable │
│ 1 Enable │
│ D6 = 640k bytes to 1M byte RAM Relocation Bit │
│ 0 No remapping(for TYP1 & 8) │
│ 1 Relocate RAM Area 0A0000H - 0FFFFFH for other type │
│ D7 = Reserved │
│ Default = X0000000 │
│ │
-- to be continued --
│FC84 Shadow RAM Control Register 2 │
│ D0 = 0F0000 - 0FFFFF Enable/Disable │
│ D1 = 0E0000 - 0EFFFF Enable/Disable │
│ 0 Enable │
│ 1 Disable │
│ D3 D2 = Function of Shadow ROM Area │
│ 0 0 Disable │
│ 0 1 Readable │
│ 1 0 Writable │
│ 1 1 Readable/Writable │
│ D5 D4 = Function of Shadow Video RAM Area │
│ 0 0 Disable │
│ 0 1 Readable │
│ 1 0 Writable │
│ 1 1 Readable/Writable │
│ D7 D6 = ROM Type │
│ 0 0 16KROM (27128) │
│ 0 1 32KROM (27256) │
│ 1 0 64KROM (27512) │
│ Default= 00000010 │
│ │
│FC85 Extend System Control Register │
│ D0 = Sleep Mode Enable/Disable │
│ 0 Disable │
│ 1 Enable │
│ D1 Enter Sleep Mode │
│ 0 Clock will not be shut off │
│ 1 Clock will be shut off if sleep enable mode bit is 1│
│ D2 Suspend/Resume Mode Enable/Disable │
│ 0 │
│ │
│FC86 Plannar Control Register 1 │
│ D0 = RAM 40000 - 4FFFF Enable/Disable │
│ D1 = RAM 50000 - 5FFFF Enable/Disable │
│ D2 = RAM 60000 - 6FFFF Enable/Disable │
│ D3 = RAM 70000 - 7FFFF Enable/Disable │
│ D4 = RAM 80000 - 8FFFF Enable/Disable │
│ D5 = RAM 90000 - 9FFFF Enable/Disable │
│ 0 Enable │
│ 1 Disable │
│ D7 D6 = Reserved │
│ Default= XX110000 │
│ │
│FC87 Enable Configuration Register Access │
│ │
-- to be continued --
│ │
│FC88 EMS control register │
│ D2 D1 D0 = on Board EMS Starting Addr. │
│ 0 0 0 = 1M │
│ 0 0 1 = 2M │
│ 0 1 0 = 4M │
│ 0 1 1 = 6M │
│ 1 0 0 = 8M │
│ D4 D3 = EMS I/O Port ADDR. Select │
│ 0 0 = 0 │
│ 0 1 = 1 │
│ 1 0 = 2 │
│ 1 1 = 3 │
│ D5 = EMS Set Select │
│ 0 Set0 │
│ 1 Set1 │
│ │
│FC89 Refresh Cycle Option Select │
│ D1 D0 = Refresh Cycle Mode Select │
│ 0 0 0 ( 4ms) │
│ 0 1 1 ( 8ms) │
│ 1 0 2 (16ms) │
│ 1 1 3 (32ms) │
│ D3 D2 = No. of Refreshes in one cycle │
│ 0 0 = 1 │
│ 0 1 = 2 │
│ 1 0 = 3 │
│ 1 1 = 4 │
│ D7 - D4 Reserved │
│ Default = XXXX0000 │
│ │
│094H Programmable Option Select │
│ │
│102H Global Enable Register (R/W) │
│ │
└─────────────────────────────────────────────────────────────────────────┘
