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GNU Info File
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1994-05-17
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928 lines
This is Info file make.info, produced by Makeinfo-1.54 from the input
file ./make.texinfo.
This file documents the GNU Make utility, which determines
automatically which pieces of a large program need to be recompiled,
and issues the commands to recompile them.
This is Edition 0.45, last updated 11 May 1994, of `The GNU Make
Manual', for `make', Version 3.71 Beta.
Copyright (C) 1988, '89, '90, '91, '92, '93, '94 Free Software
Foundation, Inc.
Permission is granted to make and distribute verbatim copies of this
manual provided the copyright notice and this permission notice are
preserved on all copies.
Permission is granted to copy and distribute modified versions of
this manual under the conditions for verbatim copying, provided that
the entire resulting derived work is distributed under the terms of a
permission notice identical to this one.
Permission is granted to copy and distribute translations of this
manual into another language, under the above conditions for modified
versions, except that this permission notice may be stated in a
translation approved by the Free Software Foundation.
File: make.info, Node: Rule Example, Next: Rule Syntax, Up: Rules
Rule Example
============
Here is an example of a rule:
foo.o : foo.c defs.h # module for twiddling the frobs
cc -c -g foo.c
Its target is `foo.o' and its dependencies are `foo.c' and `defs.h'.
It has one command, which is `cc -c -g foo.c'. The command line
starts with a tab to identify it as a command.
This rule says two things:
* How to decide whether `foo.o' is out of date: it is out of date if
it does not exist, or if either `foo.c' or `defs.h' is more recent
than it.
* How to update the file `foo.o': by running `cc' as stated. The
command does not explicitly mention `defs.h', but we presume that
`foo.c' includes it, and that that is why `defs.h' was added to
the dependencies.
File: make.info, Node: Rule Syntax, Next: Wildcards, Prev: Rule Example, Up: Rules
Rule Syntax
===========
In general, a rule looks like this:
TARGETS : DEPENDENCIES
COMMAND
...
or like this:
TARGETS : DEPENDENCIES ; COMMAND
COMMAND
...
The TARGETS are file names, separated by spaces. Wildcard
characters may be used (*note Using Wildcard Characters in File Names:
Wildcards.) and a name of the form `A(M)' represents member M in
archive file A (*note Archive Members as Targets: Archive Members.).
Usually there is only one target per rule, but occasionally there is a
reason to have more (*note Multiple Targets in a Rule: Multiple
Targets.).
The COMMAND lines start with a tab character. The first command may
appear on the line after the dependencies, with a tab character, or may
appear on the same line, with a semicolon. Either way, the effect is
the same. *Note Writing the Commands in Rules: Commands.
Because dollar signs are used to start variable references, if you
really want a dollar sign in a rule you must write two of them, `$$'
(*note How to Use Variables: Using Variables.). You may split a long
line by inserting a backslash followed by a newline, but this is not
required, as `make' places no limit on the length of a line in a
makefile.
A rule tells `make' two things: when the targets are out of date,
and how to update them when necessary.
The criterion for being out of date is specified in terms of the
DEPENDENCIES, which consist of file names separated by spaces.
(Wildcards and archive members (*note Archives::.) are allowed here
too.) A target is out of date if it does not exist or if it is older
than any of the dependencies (by comparison of last-modification
times). The idea is that the contents of the target file are computed
based on information in the dependencies, so if any of the dependencies
changes, the contents of the existing target file are no longer
necessarily valid.
How to update is specified by COMMANDS. These are lines to be
executed by the shell (normally `sh'), but with some extra features
(*note Writing the Commands in Rules: Commands.).
File: make.info, Node: Wildcards, Next: Directory Search, Prev: Rule Syntax, Up: Rules
Using Wildcard Characters in File Names
=======================================
A single file name can specify many files using "wildcard
characters". The wildcard characters in `make' are `*', `?' and
`[...]', the same as in the Bourne shell. For example, `*.c' specifies
a list of all the files (in the working directory) whose names end in
`.c'.
The character `~' at the beginning of a file name also has special
significance. If alone, or followed by a slash, it represents your home
directory. For example `~/bin' expands to `/home/you/bin'. If the `~'
is followed by a word, the string represents the home directory of the
user named by that word. For example `~john/bin' expands to
`/home/john/bin'.
Wildcard expansion happens automatically in targets, in dependencies,
and in commands (where the shell does the expansion). In other
contexts, wildcard expansion happens only if you request it explicitly
with the `wildcard' function.
The special significance of a wildcard character can be turned off by
preceding it with a backslash. Thus, `foo\*bar' would refer to a
specific file whose name consists of `foo', an asterisk, and `bar'.
* Menu:
* Wildcard Examples:: Several examples
* Wildcard Pitfall:: Problems to avoid.
* Wildcard Function:: How to cause wildcard expansion where
it does not normally take place.
File: make.info, Node: Wildcard Examples, Next: Wildcard Pitfall, Up: Wildcards
Wildcard Examples
-----------------
Wildcards can be used in the commands of a rule, where they are
expanded by the shell. For example, here is a rule to delete all the
object files:
clean:
rm -f *.o
Wildcards are also useful in the dependencies of a rule. With the
following rule in the makefile, `make print' will print all the `.c'
files that have changed since the last time you printed them:
print: *.c
lpr -p $?
touch print
This rule uses `print' as an empty target file; see *Note Empty Target
Files to Record Events: Empty Targets. (The automatic variable `$?' is
used to print only those files that have changed; see *Note Automatic
Variables: Automatic.)
Wildcard expansion does not happen when you define a variable.
Thus, if you write this:
objects = *.o
then the value of the variable `objects' is the actual string `*.o'.
However, if you use the value of `objects' in a target, dependency or
command, wildcard expansion will take place at that time. To set
`objects' to the expansion, instead use:
objects := $(wildcard *.o)
*Note Wildcard Function::.
File: make.info, Node: Wildcard Pitfall, Next: Wildcard Function, Prev: Wildcard Examples, Up: Wildcards
Pitfalls of Using Wildcards
---------------------------
Now here is an example of a naive way of using wildcard expansion,
that does not do what you would intend. Suppose you would like to say
that the executable file `foo' is made from all the object files in the
directory, and you write this:
objects = *.o
foo : $(objects)
cc -o foo $(CFLAGS) $(objects)
The value of `objects' is the actual string `*.o'. Wildcard expansion
happens in the rule for `foo', so that each *existing* `.o' file
becomes a dependency of `foo' and will be recompiled if necessary.
But what if you delete all the `.o' files? When a wildcard matches
no files, it is left as it is, so then `foo' will depend on the
oddly-named file `*.o'. Since no such file is likely to exist, `make'
will give you an error saying it cannot figure out how to make `*.o'.
This is not what you want!
Actually it is possible to obtain the desired result with wildcard
expansion, but you need more sophisticated techniques, including the
`wildcard' function and string substitution. *Note The Function
`wildcard': Wildcard Function.
File: make.info, Node: Wildcard Function, Prev: Wildcard Pitfall, Up: Wildcards