Vectronix 2/VECTRONIX2.iso/FILES_10/DEVELOP.LZH/DSP/DSPDEBUG/SSINDX.HLP

Text File | 1992-08-29 | 1KB | 33 lines

{
SSI}    :    {
SYNCHRONOUS SERIAL INTERFACE}
{
CRA}    :    {
SSI CONTROL REGISTER A}
    {
PM0}-{
PM7}    :    {Prescale Modulus Select}
    {
DC0}-{
DC4}    :    {Frame Rate Divider Control}
    {
WL0}-{
WL1}    :    {Word Length Control}
    {
PSR}    :    {Prescaler Range}
{
CRB}    :    {
SSI CONTROL REGISTER B}
    {
OF0}-{
OF1}    :    {Serial Output Flag}
    {
SCD0}-{
SCD2}    :    {Serial Control Direction}
    {
SCKD}    :    {Clock Source Direction}
    {
SHFD}    :    {Shift Direction}
    {
FSL0}-{
FSL1}    :    {Frame Sync Length}
    {
SYN}    :    {Sync/Async}
    {
GCK}    :    {Gated Clock Control}
    {
MOD}    :    {SSI Mode Select}
    {
TE}    :    {SSI Transmit Enable}
    {
RE}    :    {SSI Receive Enable}
    {
TIE}    :    {SSI Transmit Interrupt Enable}
    {
RIE}    :    {SSI Receive Interrupt Enable}
{
SSISR}    :    {
SSI STATUS REGISTER}
    {
IF0}-{
IF1}    :    {Serial Input Flag}
    {
TFS}    :    {Transmit Frame Sync Flag}
    {
RFS}    :    {Receive Frame Sync Flag}
    {
TUE}    :    {Transmitter Underrun Error Flag}
    {
ROE}    :    {Receive Overrun Error Flag}
    {
TDE}    :    {SSI Transmit Data Register Empty}
    {
RDF}    :    {SSI Receive Data Register Full}
            {
SSI Receive Shift Register}
{
RX}    :    {
SSI Receive Data Register}
            {
SSI Transmit Shift Register}
{
TX}    :    {
SSI Transmit Data Register}
{
TSR}    :    {
SSI Time Slot Register}