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Text File  |  1996-09-06  |  13KB  |  342 lines
  1. ;*************  VIA VT82C480 **************************************
  2. ; Based on VIA Technology Datasheets.
  3. ; Written by Jos Maas
  4. ; Chipset has VT82C481 ISA Bus Controller and VT82C495 Cache/DRAM Controller.
  5. ; Note that VT82C491 is EISA Bus Controller, compatible to work with VT82C495.
  6. ;******************************************************************
  7.  
  8. NAME=VT82C495
  9. INDEXPORT=A8H   ;
  10. DATENPORT=A9H
  11.  
  12. MACRO=L2OFF    = FLUSH , 50H:00xxxxxx
  13. MACRO=L2ON     = FLUSH , 50H:01xxxxxx, FLUSH , 50H:10xxxxxx
  14. MACRO=ALLDIRTY = L2OFF , 50H:xx0xxxxx, L2ON
  15. MACRO=NODIRTY  = L2OFF , 50H:xx1xxxxx, L2ON
  16. MACRO=BUSCLK8  = FLUSH , 11H:xxxx0xxx
  17. MACRO=BUSCLK2  = BUSCLK8,11H:xxxxx001, FLUSH , 11H:xxxx1xxx
  18. MACRO=BUSCLK3  = BUSCLK8,11H:xxxxx000, FLUSH , 11H:xxxx1xxx
  19. MACRO=BUSCLK4  = BUSCLK8,11H:xxxxx010, FLUSH , 11H:xxxx1xxx
  20. MACRO=BUSCLK5  = BUSCLK8,11H:xxxxx100, FLUSH , 11H:xxxx1xxx
  21. MACRO=BUSCLK6  = BUSCLK8,11H:xxxxx011, FLUSH , 11H:xxxx1xxx
  22. MACRO=BUSCLK10 = BUSCLK8,11H:xxxxx101, FLUSH , 11H:xxxx1xxx
  23. MACRO=BUSCLK12 = BUSCLK8,11H:xxxxx110, FLUSH , 11H:xxxx1xxx
  24.  
  25. ;******************************************************************
  26.                 ;ISA/EISA Bus Control
  27. ;******************************************************************
  28.  
  29. ;******************************************************************
  30. INDEX=00H       ;Chip Revision ID ??? (All bits are read-only)
  31. ;******************************************************************
  32. BIT=76543210    ;Read-only, Chip(set) ID (??)
  33.                  00000001=VT82C481 - VT82C495
  34.  
  35. ;******************************************************************
  36. INDEX=01H       ;Unknown
  37. ;******************************************************************
  38. BIT=765         ;Unknown, defaults to 101 in Highscreen 486DX50
  39. BIT=43210       ;Read-only, set to 00001
  40.  
  41.  
  42. ;******************************************************************
  43. INDEX=02H       ;Slow Counter
  44. ;******************************************************************
  45. BIT=7            ;0/1 CPU slow mode (ISA only)
  46. BIT=6543210      ;Hold pulse-width value
  47.  
  48. ;******************************************************************
  49. INDEX=03H       ;ISA Bus Control 1
  50. ;******************************************************************
  51. BIT=7           ;ISA Command Delay
  52.                  0 = normal
  53.                  1 = extended
  54. BIT=6           ;ROM Wait State
  55.                  0 = 1 Waits
  56.                  1 = 0 Waits
  57. BIT=5           ;ISA Wait State
  58.                  0 = normal
  59.                  1 = extended
  60. BIT=4           ;Chipset Register Wait State
  61.                  0 = normal
  62.                  1 = extended
  63. BIT=3            ;0/1 I/O Recovery Time
  64. BIT=2            ;0/1 Extended ALE
  65. BIT=1            ;Reserved, must be 0
  66. BIT=0            ;0/1 De-coupled refresh
  67.  
  68. ;******************************************************************
  69. INDEX=04H       ;ISA Bus Control 2
  70. ;******************************************************************
  71. BIT=765         ;Reserved must be 0
  72. BIT=4           ;0/1 Turbo Pin Function
  73. BIT=3           ;Reserved, must be 0
  74. BIT=2           ;0/1 Dallas 1387 support (EISA only)
  75. BIT=1           ;System ID (EISA only)
  76.                  0 = Write disable
  77.                  1 = Write enable
  78. BIT=0           ;0/1 EISA Burst Transfer
  79.  
  80. ;******************************************************************
  81. INDEX =10H      ;Chip Control (read only)
  82.                 ;To select the 1 or 0 option, the corresponding bit
  83.                 ;of the XD bus is pulled up/down respectively with
  84.                 ;a 4K7 resistor. The presence of the 80387DX can be
  85.                 ;automatically detected through the ERROR pin.
  86. ;******************************************************************
  87. BIT=7           ;80387DX Presence
  88.                  0 = not present
  89.                  1 = present
  90. BIT=6           ;Weitek 4167/3167 Presence
  91.                  0 = not present
  92.                  1 = present
  93. BIT=543         ;Reserved must be 0
  94. BIT=2           ;Expansion Bus Type
  95.                  0 = EISA
  96.                  1 = ISA
  97. BIT=1           ;Clock mode
  98.                  0 = 1x
  99.                  1 = 2x
  100. BIT=0           ;CPU Type
  101.                  0 = 80386DX
  102.                  1 = 80486DX
  103.  
  104. ;******************************************************************
  105. INDEX=11H       ;ISA/EISA Bus Clock
  106. ;******************************************************************
  107. BIT=7          ;0/1 SA16 Reversal for Flash EPROMs
  108. BIT=6          ;0/1 ROM Write for Flash EPROMs
  109. BIT=54         ;Reserved, must be 0
  110. BIT=3          ;BCLK2-Selection (ISA bus runs at half of BCLK2)
  111.                 0=BCLK2=CLK2/4
  112.  
  113. BIT=210        ;BCLK2
  114.                 000=CLK2/1.5
  115.                 001=CLK2
  116.                 010=CLK2/2
  117.                 011=CLK2/3
  118.                 100=CLK2/3.5
  119.                 101=CLK2/5
  120.                 110=CLK2/6
  121.                 111=reserved
  122.  
  123. ;******************************************************************
  124. INDEX=20H       ;DRAM Control
  125. ;******************************************************************
  126.  
  127. ;******************************************************************
  128. INDEX=20H       ;Bank 0/1 Configuration
  129. ;******************************************************************
  130.  
  131. BIT=765       ;Bank 0 DRAM Type
  132.               000 = disable
  133.               001 = 256 Kbit DRAM
  134.               010 = 1 MBit DRAM
  135.               011 = 4 MBit DRAM
  136.               100 =16 MBit DRAM
  137.  
  138. BIT=4         ;0/1 DRAM Page Mode
  139.  
  140. BIT=321       ;Bank 1 DRAM Type
  141.               000 = disable
  142.               001 = 256 Kbit DRAM
  143.               010 = 1 MBit DRAM
  144.               011 = 4 MBit DRAM
  145.               100 =16 MBit DRAM
  146. BIT=0         ;Reserved, must be 0
  147.  
  148. ;******************************************************************
  149. INDEX=21H       ;Bank 2/3 Configuration
  150. ;******************************************************************
  151.  
  152. BIT=765       ;Bank 2/3 DRAM Type
  153.               000 = disable
  154.               001 = 256 Kbit DRAM
  155.               010 = 1 MBit DRAM
  156.               011 = 4 MBit DRAM
  157.               100 =16 MBit DRAM
  158. BIT=4         ;Bank 3
  159.               0 = not present
  160.               1 = present
  161. BIT=3         ;0/1 High Boot ROM
  162. BIT=2         ;0/1 Middle Boot ROM
  163. BIT=10        ;Reserved, must be 0
  164.  
  165. ;******************************************************************
  166. INDEX=22H       ;DRAM-Timing
  167. ;******************************************************************
  168.  
  169. BIT=76        ;RAS Precharge width
  170.               00=1 CPU Cycle
  171.               01=2 CPU Cycles
  172.               10=3 CPU Cycles
  173.               11=4 CPU Cycles
  174. BIT=54       ;RAS Pulse width
  175.               00=2 CPU Cycles
  176.               01=3 CPU Cycles
  177.               10=4 CPU Cycles
  178.               11=5 CPU Cycles
  179. BIT=32       ;Read Cycle CAS pulse width
  180.               00=1 CPU Cycle
  181.               01=2 CPU Cycles
  182.               10=3 CPU Cycles
  183.               11=4 CPU Cycles
  184. BIT=1        ;Write Cycle CAS pulse width
  185.               0=1 CPU Cycle
  186.               1=2 CPu Cycles
  187. BIT=0       ; RAS to Column Address / Column Address to CAS
  188.               0=1 CLK2IN
  189.               1=2 CLK2IN
  190. ;******************************************************************
  191. INDEX=30H       ;Shadow Control 1
  192. ;******************************************************************
  193. BIT=7       ; 0/1 CC000-CFFFF shadow area read
  194. BIT=6       ; 0/1 CC000-CFFFF shadow area write
  195. BIT=5       ; 0/1 C8000-CBFFF shadow area read
  196. BIT=4       ; 0/1 C8000-CBFFF shadow area write
  197. BIT=3       ; 0/1 C4000-C7FFF shadow area read
  198. BIT=2       ; 0/1 C4000-C7FFF shadow area write
  199. BIT=1       ; 0/1 C0000-C3FFF shadow area read
  200. BIT=0       ; 0/1 C0000-C3FFF shadow area write
  201.  
  202. ;******************************************************************
  203. INDEX=31H       ;Shadow Control 2
  204. ;******************************************************************
  205. BIT=7       ; 0/1 DC000-DFFFF shadow area read
  206. BIT=6       ; 0/1 DC000-DFFFF shadow area write
  207. BIT=5       ; 0/1 D8000-DBFFF shadow area read
  208. BIT=4       ; 0/1 D8000-DBFFF shadow area write
  209. BIT=3       ; 0/1 D4000-D7FFF shadow area read
  210. BIT=2       ; 0/1 D4000-D7FFF shadow area write
  211. BIT=1       ; 0/1 D0000-D3FFF shadow area read
  212. BIT=0       ; 0/1 D0000-D3FFF shadow area write
  213.  
  214. ;******************************************************************
  215. INDEX=32H       ;Shadow Control 3
  216. ;******************************************************************
  217. BIT=7       ; 0/1 E0000-EFFFF shadow area read
  218. BIT=6       ; 0/1 E0000-EFFFF shadow area write
  219. BIT=5       ; 0/1 F0000-FFFFF shadow area read
  220. BIT=4       ; 0/1 F0000-FFFFF shadow area write
  221. BIT=3210    ; Unknown
  222.  
  223. ;******************************************************************
  224. INDEX=33H       ;ROM Decode and Relocation
  225. ;******************************************************************
  226. BIT=7           ;C8000-CFFFF is decoded as
  227.                  0 = ISA Bus cycle
  228.                  1 = ROM cycle
  229. BIT=6           ;C0000-C7FFF is decoded as
  230.                  0 = ISA Bus cycle
  231.                  1 = ROM cycle
  232. BIT=5           ;E8000-EFFFF is decoded as
  233.                  0 = ISA Bus cycle
  234.                  1 = ROM cycle
  235. BIT=4           ;E0000-E7FFF is decoded as
  236.                  0 = ISA Bus cycle
  237.                  1 = ROM cycle
  238. BIT=32          ; 256K/384K relocation
  239.                 00= no relocation
  240.                 01= illegal
  241.                 10= 256K relocation
  242.                 11= 384K relocation
  243. BIT=1,0         ;Reserved, must be 0
  244.  
  245. ;******************************************************************
  246. INDEX=40H       ;Cache Control
  247. ;******************************************************************
  248.  
  249. ;******************************************************************
  250. INDEX=40H       ;ROM Cacheable
  251. ;******************************************************************
  252. BIT=7           ;C0000-C7FFF ROM is
  253.                 0 = not cacheable
  254.                 1 = cacheable and write protect
  255. BIT=6           ;F0000-FFFFF ROM is
  256.                 0 = not cacheable
  257.                 1 = cacheable and write protect
  258. BIT=5           ;E0000-EFFFF ROM is
  259.                 0 = not cacheable
  260.                 1 = cacheable and write protect
  261. BIT=43210       ;Reserved, must be 0
  262.  
  263. ;******************************************************************
  264. INDEX=41H       ;Non Cacheable Area Base Address
  265. ;******************************************************************
  266. BIT=76543210    ;A26..A19
  267.  
  268. ;******************************************************************
  269. INDEX=42H       ;Non Cacheable Area Base Address and Size
  270. ;******************************************************************
  271. BIT=765         ;A18..A16
  272. BIT=4           ;Reserved, must be 0
  273. BIT=321         ;non-cacheable area size
  274.                 000=disable
  275.                 001=64K
  276.                 010=128K
  277.                 011=256K
  278.                 100=512K
  279.                 101=1M
  280.                 110=2M
  281.                 111=4M
  282. BIT=0           ;Reserved, must be 0
  283.  
  284. ;******************************************************************
  285. INDEX=50H       ;Cache Access Control
  286. ;******************************************************************
  287. BIT=76           ;L2-Cache
  288.                  00 = disable
  289.                  01 = initial
  290.                  10 = enable
  291.                  11 = illegal
  292.  
  293. BIT=5           ;0/1 L2-Direct, always hit
  294. BIT=4           ;Alter bit SRAM
  295.                  0 = present
  296.                  1 = not present
  297. BIT=32          ;Cache Line Size
  298.                 00= 4 Bytes
  299.                 01= 8 Bytes
  300.                 10=16 Bytes
  301.                 11= 4 bytes
  302. BIT=1           ;0/1 Burst Write
  303. BIT=0           ;Reserved, must be 0
  304.  
  305. ;******************************************************************
  306. INDEX=51H       ;Cache Timing
  307. ;******************************************************************
  308.  
  309. BIT=75          ; Read-Burst
  310.                 00 = 2-1-1-1
  311.                 01 = 2-2-2-2
  312.                 10 = 3-1-1-1
  313.                 11 = 3-2-2-2
  314.  
  315. BIT=64          ; Write-Burst
  316.                 00 = 2-1-1-1
  317.                 01 = 2-2-2-2
  318.                 10 = 3-1-1-1
  319.                 11 = 3-2-2-2
  320.  
  321. BIT=3           ;Cache Banks
  322.                 0 = 1 Bank
  323.                 1 = 2 Banks
  324.  
  325. BIT=210         ;Cache Size
  326.                 000 =No Cache
  327.                 001 =32K
  328.                 010 =64K
  329.                 011 =128K
  330.                 100 =256K
  331.                 101 =512K
  332.                 110 =1M
  333.                 111 =Illegal
  334.  
  335. ;******************************************************************
  336. INDEX=80H       ;UNKNOWN
  337. BIT=76543210    ;Read-only, Chip(set) ID (??)
  338.                  10101001=VT82C481 - VT82C495
  339.  
  340. ;******************************************************************
  341.  
  342.