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VT82C486.CFG
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1995-03-07
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18KB
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461 lines
;************* VIA VT82C486, D, A-D, E, A-E, A-F, A-G *************
; c't 3/95/as : Roh-Fassung, nur schwach getestet, ohne Power-Management
;******************************************************************
NAME=VT82C486
INDEXPORT=A8H ;
DATENPORT=A9H
MACRO=L2OFF = FLUSH , 50H:0xxxxxxx
MACRO=L2ON = FLUSH , 50H:x1xxxxxx, FLUSH , 50H:10xxxxxx
MACRO=ALLDIRTY = L2OFF , 50H:xxx0xxxx, L2ON
MACRO=NODIRTY = L2OFF , 50H:xxx1xxxx, L2ON
MACRO=L1WB = L2OFF , 5EH:0xxxxxxx, L2ON
MACRO=L1WT = L2OFF , 5EH:1xxxxxxx, L2ON
MACRO=L2WB = L2OFF , 5EH:x0xxxxxx, L2ON
MACRO=L2WT = L2OFF , 5EH:x1xxxxxx, L2ON
;******************************************************************
INDEX=00H ;Revision-ID
;******************************************************************
BIT=76543210 ;Chipset and Revision-ID of 82C486
01010001= VT82C486D No Parity, No Power Management
01100001= VT82C486A-D With Parity, No Power Management
01010010= VT82C486-E No Parity, With Power Management
01100010= VT82C486A-E With Parity, With Power Management
01100011= VT82C486A-F With Parity, With Power Management
01100100= VT82C486A-G With Parity, With Power Management
ELSE = VT82C486 unbekannte Revision
;******************************************************************
INDEX=01H ;XD Bus Switch Register
;******************************************************************
BIT=7 ;0/1 Parity Check
BIT=65 ;reserved
BIT=4 ;0/1 PS2-Mouse
BIT=3 ;0/1 Keyboard Controller
BIT=2 ;0/1 use IRQ15/SMI as power management interrupt
BIT=10 ; CPU-Type
00=80386SX
01=80486LP
10=80386DX
11=80486
;******************************************************************
INDEX=02H ;Slow Counter
;******************************************************************
BIT=6..0 ;Puls-With value
;******************************************************************
INDEX=03H ;ISA Bus Control 1
;******************************************************************
BIT=7 ;ISA Command Delay
0=normal
1= extra
BIT=6 ;ROM Wait State
0 = 0 Waits
1 = 1 Waits
BIT=5 ;ISA Slave Wait State
0 = 4 Waits
1 = 5 Waits
BIT=4 ; Chipset Register Wait State
0 = 2 Waits
1 = 4 Waits
BIT=3 ;0/1 I/O Recovery Time
BIT=2 ;0/1 extended BALE for Byte Conversation
BIT=1 ;0/1 reserved must be 0
BIT=0 ;0/1 decouple refresh
;******************************************************************
INDEX=04H ;ISA Bus Control 2
;******************************************************************
BIT=7 ;0/1 reserved must be 0
BIT=6 ;0/1 internal XRDY when slow down CPU
BIT=5 ;0/1 Port 92h Fast Reset
BIT=4 ;0/1 Turbo Pin for Deturbo Function
BIT=3,2 ;reserved, must be 0
BIT=1 ;0/1 Parity Check of ISA Master and DMA Cycle
BIT=0 ;LOCAL# Pin uses for PCI Bridge (VT82C486A-F/G only)
;******************************************************************
INDEX =10H ; 80387
;******************************************************************
0=not exist
1=exist
;******************************************************************
INDEX=11H ;ISA Bus Clock
;******************************************************************
BIT=7 ;0/1 SA16 Reversal for Flash EPROMs
BIT=6 ;0/1 ROM Write for Flash EPROMs
BIT=5 ;0/1 PS/2 mouse lock (82C486A-G only)
BIT=4 ;reserved, must be 0
BIT=3 ;0/1 BCLK-Selection
0=BCLK=CLK2/8
BIT=210 ;BCLK
000=CLK2/3
001=CLK2/2
010=CLK2/4
011=CLK2/6
100=CLK2/5
101=CLK2/10
110=CLK2/12
111=7,159 MHz
;******************************************************************
INDEX=20H ;DRAM-Typ
;******************************************************************
BIT=765 ; Bank 0 DRAM Type
000 = disable
001 = 256 Kbit DRAM
010 = 1 MBit DRAM
011 = 4 MBit DRAM
100 =16 MBit DRAM
BIT=4 ;0/1 DRAM Page Mode
BIT=321 ; Bank 1 DRAM Type
000 = disable
001 = 256 Kbit DRAM
010 = 1 MBit DRAM
011 = 4 MBit DRAM
100 =16 MBit DRAM
;******************************************************************
INDEX=21H ;DRAM-Typ
;******************************************************************
BIT=765 ; Bank 2/3 DRAM Type
000 = disable
001 = 256 Kbit DRAM
010 = 1 MBit DRAM
011 = 4 MBit DRAM
100 =16 MBit DRAM
BIT=4 ;0/1 Bank 3
BIT=3 ;0/1 High Boot ROM
BIT=2 ;0/1 Middle Boot ROM
BIT=1 ;0/1 80386 Pipeline Address
BIT=0 ;0/1 Fast 2x-Mode
;******************************************************************
INDEX=22H ;DRAM-Typ
;******************************************************************
BIT=76 ; RAS Precharge
00=1 Cycle
01=2 Cycles
10=3 Cycles
11=4 Cycles
BIT=54 ; RAS Puls
00=2 Cycles
01=3 Cycles
10=4 Cycles
11=5 Cycles
BIT=32 ; Read Cycle
00=1 Cycle
01=2 Cycles
10=3 Cycles
11=4 Cycles
BIT=1 ; Write Cycle
0=1 Cycle
1=2 Cycles
BIT=0 ; RAS to Column Address and Column Address to CAS
0=1 Cycle
1=2 Cycles
;******************************************************************
INDEX=30H ;Shadow Control 1
;******************************************************************
BIT=7 ; 0/1 CC000-CFFFF shadow area read option
BIT=6 ; 0/1 CC000-CFFFF shadow area write option
BIT=5 ; 0/1 C8000-CBFFF shadow area read option
BIT=4 ; 0/1 C8000-CBFFF shadow area write option
BIT=3 ; 0/1 C4000-C7FFF shadow area read option
BIT=2 ; 0/1 C4000-C7FFF shadow area write option
BIT=1 ; 0/1 C0000-C3FFF shadow area read option
BIT=0 ; 0/1 C0000-C3FFF shadow area write option
;******************************************************************
INDEX=31H ;Shadow Control 2
;******************************************************************
BIT=7 ; 0/1 DC000-DFFFF shadow area read option
BIT=6 ; 0/1 DC000-DFFFF shadow area write option
BIT=5 ; 0/1 D8000-DBFFF shadow area read option
BIT=4 ; 0/1 D8000-DBFFF shadow area write option
BIT=3 ; 0/1 D4000-D7FFF shadow area read option
BIT=2 ; 0/1 D4000-D7FFF shadow area write option
BIT=1 ; 0/1 D0000-D3FFF shadow area read option
BIT=0 ; 0/1 D0000-D3FFF shadow area write option
;******************************************************************
INDEX=32H ;Shadow Control 3 + DRAM-Control
;******************************************************************
BIT=7 ; 0/1 E0000-EFFFF shadow area read option
BIT=6 ; 0/1 E0000-EFFFF shadow area write option
BIT=5 ; 0/1 F0000-FFFFF shadow area read option
BIT=4 ; 0/1 F0000-FFFFF shadow area write option
BIT=3 ; chipset parity generation
0=generates by CPU for 486 Operation
1=generated by chipset for 386DX/SX
BIT=2 ; 0/1 1MB Hole at Top of 16 MB from 0F00000h
BIT=1 ; 0/1 DRAM Burst Mode if L2 enabled (not 82C486, -D)
BIT=0 ; 0/1 reserved, must be 0
;******************************************************************
INDEX=33H ;ROM Decode
;******************************************************************
BIT=7 ;0/1 C8000-CFFFF is decoded as ROM/ISA-Cycle
BIT=6 ;0/1 C0000-C7FFF is decoded as ROM/ISA-Cycle
BIT=5 ;0/1 E8000-EFFFF is decoded as ROM/ISA-Cycle
BIT=4 ;0/1 E0000-E7FFF is decoded as ROM/ISA-Cycle
BIT=32 ; 256K/384K relocation
00= no relocation
01= illegal
10= 256K relocation
11= 384K relocation
BIT=1,0 ;reserved, must be 0
;******************************************************************
INDEX=34H ;ROM Cacheable
;******************************************************************
BIT=7 ;0/1 C0000-C7FFF to be cacheable and Write protect
BIT=6 ;0/1 F0000-FFFFF to be cacheable and Write protect
BIT=5 ;0/1 E0000-EFFFF to be cacheable and Write protect
BIT=4 ;reserved
BIT=3 ;0/1 CAS before RAS Refresh
BIT=2 ;0/1 ISA Master Command Sampling
BIT=10 ;Delay of CAS# during DMA Write Cycle
00= disable
01= 1 CPU Clock
10= 2 CPU Clocks
11= 3 CPU Clocks
;******************************************************************
INDEX=41H ;Non Cacheable Area Base
;******************************************************************
BIT=7..0 ;A26..A19
;******************************************************************
INDEX=42H ;Non Cacheable Area Size
;******************************************************************
BIT=765 ;A18..A16
BIT=4 ;0/1 IOCHRDY for ISA-Master DRAM access (not 82C486,A-D)
BIT=321 ;non-cacheable area size
000=disable
001=64K
010=128K
011=256K
100=512K
101=1M
110=2M
111=4M
BIT=0 ;0/1 Local Bus Ready synchron with cpu clock
;******************************************************************
INDEX=50H ;Cache Access Control
;******************************************************************
BIT=7 ;0/1 L2-Cache
BIT=6 ;0/1 L2-Init, always miss
BIT=5 ;0/1 L2-Direct, always hit
BIT=4 ;1/0 Combined Tag/Dirty
BIT=32 ;Cache Line Size
00= 4 Bytes
01= 8 Bytes
10=16 Bytes
11= reserved
BIT=1 ;0/1 Burst Write
BIT=0 ;0/1 80486 Data Streaming
;******************************************************************
INDEX=51H ;Cache Timing
;******************************************************************
BIT=75 ; READ-Burst
00 = 2-1-1-1
01 = 2-2-2-2
10 = 3-1-1-1
11 = 3-2-2-2
BIT=64 ; Write-Burst
00 = 2-1-1-1
01 = 2-2-2-2
10 = 3-1-1-1
11 = 3-2-2-2
BIT=3 ;Cache Banks
0=1 Bank
1=2 Banks
BIT=210 ;Cache Size
000 =No Cache
001 =32K
010 =64K
011 =128K
100 =256K
101 =512K
110 =1M
111 =16K
;******************************************************************
INDEX=52H ;Primary activity detector Control
;******************************************************************
;******************************************************************
INDEX=53H ;Primary activity status
;******************************************************************
;******************************************************************
INDEX=54H ;Power management Interrupt event control
;******************************************************************
;******************************************************************
INDEX=55H ;Power management Interrupt status
;******************************************************************
;******************************************************************
INDEX=56H ;CPU Clock Control
;******************************************************************
BIT=765 ; CLOCK Selection (activate with Register 5D)
000= CLK2IN (Full-on Mode)
001= CLK2IN/4 (DOZE)
010= CLK2IN/8 (DOZE)
011= CLK2IN/16 (DOZE)
100= CLK2IN/32 (DOZE)
101= CLK2IN/64 (DOZE)
110= CLK2IN/2 (DOZE)
111= stop clock (Suspend)
BIT=4..0 ;reserved
;******************************************************************
INDEX=57H ;2. General Purpose Timer
;******************************************************************
BIT=7..0 ; actual value
;******************************************************************
INDEX=58H ;1. General Purpose Timer
;******************************************************************
BIT=7..0 ; actual value
;******************************************************************
INDEX=59H ;1. General Purpose Timer and Idle Control
;******************************************************************
BIT=76 ; GP timer clock selection
00= disable
01= 32768 Hz
10= 1 sec
11= 1 min
BIT=54 ; (1)STPCLK# recovery time or (2) auto grant delay time
00 = Immediately
01 = 1 ms (1) if 5D:3=0
01 = 0,5 ms (2) if 5D:3=1
10 = 0,375 ms (1) if 5D:3=0
10 = 0,1875 ms (2) if 5D:3=1
11 = 0,125 ms (1) if 5D:3=0
11 = 0,0625 ms (2) if 5D:3=1
BIT=321 ; Idle Timer (timeout not retriggaeable)
000=disable
001=2 s
010=8 s
011=32 s
100=2 min
101=8 min
110=16 min
111=32 min
BIT=0 ; PIN 60 (82C486)/ PIN 152 (82C486A) is
0=CA26
1=IRQ15
;******************************************************************
INDEX=5AH ;General Purpose Output Ports
;******************************************************************
;******************************************************************
INDEX=5BH ;SMM-Control
;******************************************************************
;******************************************************************
INDEX=5CH ;MISC 1
;******************************************************************
BIT=7 ; 0/1 Wait for Halt cycle to start clock change
BIT=6 ; 0/1 Wait for Acknowledge Resonse whne clock change
BIT=4 ; CPU-Type for change clock protokol
0=Cyrix-SUSPA#
1=Intel STPCLK# or Cyrix-SUSP#
BIT=3 ; Turbo Pin status (read only)
BIT=2 ; reserved, must be 0
BIT=1 ;0/1 Soft reset for write Back CPU and Intel-SLe
BIT=0 ;0/1 wait delay for local Bus master write cycle
;******************************************************************
INDEX=5DH ;Change CPU Clock
;******************************************************************
BIT=7 ;Write 1 to start change CPU Clock operation
BIT=6 ;0/1 PMI automatically wake up clock (82C486A-G only)
BIT=5 ;0/1 SMI# activ until SMIADS# (82C486A-F/G only)
BIT=4 ;0/1 Turbo Pin used as keyb lock (82C486A-F/G only)
BIT=3 ;Write 1 to enable auto stop grant protocol
BIT=2 ;0/1 Turbo Pin used as keyb lock (82C486A-F/G only)
BIT=10 ;2. General Purpose Timer
00= disable
01= 32768 Hz
10= 1 sec
11= 1 min
;******************************************************************
INDEX=5EH ;MISC 2
;******************************************************************
BIT=7 ;0/1 L1-Write Back
BIT=6 ;L2-Strategie
0=Write Back
1=Write Through
BIT=5 ;CACHE#/BLAST# Signal sharing on Pin 65 or 151
0=BLAST#
1=CACHE#
BIT=4 ;0/1 snoop filter for ISA master
BIT=3 ;0/1 one CPU Clock Delay of ISA ready (82C486A-F/G only)
BIT=2 ;0/1 two times longer slow refresh (82C486A-F/G only)
BIT=1 ;0/1 parity check for byte 2 and 3 (82C486A-F/G only)
BIT=0 ; Write 1 asserts STPCLK#-Signal and force CPU to
; suspend without change clock (82C486A-F/G only)
;******************************************************************
INDEX=60H ;Interrupt event/activity detection control (VT82C486A-G only)
;******************************************************************
;******************************************************************
INDEX=61H ;Interrupt event/activity detection control (VT82C486A-G only)
;******************************************************************
;******************************************************************
INDEX=62H ;Level Trigger Interrupt Control (VT82C486A-G only)
;******************************************************************
;******************************************************************
INDEX=63H ;Level Trigger Interrupt Control (VT82C486A-G only)
;******************************************************************
;******************************************************************
INDEX=63H ;Power on Switch Setting (VT82C486A-G only)
;******************************************************************