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Magazyn Enter 1999 January
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enter_01_1999_2.iso
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ctchip34
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SHASTA.CFG
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1993-12-23
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15KB
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461 lines
;********************************************************************
NAME=HT321; HTK340 Shasta 486 HT321 Register Descriptions
;********************************************************************
INDEXPORT=28h
DATENPORT=24h
;********************************************************************
INDEX=00h ;Chip/Revision Identifier, Read Only
;********************************************************************
BIT=7654 ;=Chip Identifier (0 = HT321)
BIT=3210 ;=Chip Revision Indicator - (0=Rev A,1=Rev.B, 3=Rev D)
;********************************************************************
INDEX=01h ;System Clocking (Reset State = 00H), R/W
;********************************************************************
BIT=7654 ; Reserved. Always program to 0
BIT=3210 ;ISA Speed Set
0000=HCLK frequency = 66 MHz
0001=HCLK frequency = 66 MHz
0010=HCLK frequency = 66 MHz
0011=HCLK frequency = 66 MHz
0100=HCLK frequency = 50 MHz
0101=HCLK frequency = 40 MHz
0110=HCLK frequency = 33 MHz
0111=HCLK frequency = 25 MHz
1000=HCLK frequency = 20 MHz
1001=HCLK frequency = 16 MHz
1010=Reserved, Do Not Program
1011=Reserved, Do Not Program
1100=Reserved, Do Not Program
1101=Reserved, Do Not Program
1110=Reserved, Do Not Program
1111=Reserved, Do Not Program
;********************************************************************
INDEX=02h ;System Parameters (Reset State = 00H), R/W
;********************************************************************
BIT=76 ;I/O-Recovery (Rev. D or later)
; ; minimum = 1,5 BCLKs +
00= 0 additional BCLKs
01= 1 additional BCLKs
10= 3 additional BCKLs
11= 7 additional BCLKs
BIT=5 ;PARITY_OVERRIDE
0=Parity Error Override OFF
1=Parity Error Override ON
BIT=43 ;CYCLE_WIDTH
00=Backplane Cycle Time = 6 BCLKs (ISA Default)
01=Backplane Cycle Time = 5 BCLKs
10=Backplane Cycle Time = 4 BCLKs
11=Backplane Cycle Time = 3 BCLKs
BIT=2 ;0/1 Port 92 Functionality
BIT=1 ;IO_DECODE
0=10-Bit I/O decoding enabled
1=16-Bit I/O decoding enabled
BIT=0 ;0/1 POSTED Backplane MEMWN cycles
;********************************************************************
INDEX=04h ;Co-Processor (Reset State - 00H), R/W***
;********************************************************************
BIT=76543 ; Reserved. Always program to 0
BIT=2 ;SOFT_NPU_R
0=Software Co-Processor RESET not blocked (386 only)
1=Software Co-Processor RESET blocked (386 only)
BIT=1 ;WEITEK_IN
0=Weitek Co-Processor not installed
1=Weitek Co-Processor installed
BIT=0 ;387_IN
0=80387 Co-Processor not installed
1=80387 Co-Processor installed
;********************************************************************
INDEX=06h ;DMA (Reset State = 00H), R/W
;********************************************************************
BIT=7 ; Reserved. Always program to 0.
BIT=6 ;1/0 IOCHRDY during Master Cycle (Rev.C or later)
; ;kann Busmaster, etwa Adaptec "ausbremsen"
BIT=5 ;0/1 Fast Sample DMA
; ;enabled only for 16 .. 20 MHz 486
BIT=43 ;DMA_WS
00=DMA Wait states = 3
01=DMA Wait states = 2
10=DMA Wait states = 1
11=DMA Wait states = 0
BIT=2 ;0/1 DMA FLOW_THRU Mode
; ;=> 1 if write buffer enabled
; ; corresponds to Index 2Bh, Bit 4
BIT=1 ;0/1 Extended DMA Page Registers
BIT=0 ;DMA_CLK
0=DMA Clock = BCLK divided by 2
1=DMA Clock = BCLK inverted
;********************************************************************
INDEX=07h ; EPROM (Reset State = 00H), R/W
;********************************************************************
BIT=76 ; Reserved. Always program to 0
BIT=5 ;0/1 EADS CACHE Invalidation for EPROM Writes (Rev.D or later)
BIT=4 ;0/1 ROMEN for EPROM Writes (Rev.C or later)
BIT=3 ;0/1 Middle BIOS region of 64K space (below 16 Mb)
BIT=2 ;ROM_SIZE
0= ROM size = 64 K
1= ROM size = 128 K
BIT=1 ;V_BIOS_ADD
0=Video BIOS separate from System BIOS
1=Video BIOS together with System BIOS in same physical device
BIT=0 ;ROM_ACCESS_T
0=250nSec ROM Output Enable pulse duration
1=125nSec ROM Output Enable pulse duration
;********************************************************************
INDEX=08h ;I/O and MEMORY MAP HOLES (Reset State = 00H), R/W
;********************************************************************
BIT=765 ; Reserved. Always program to 0
BIT=4 ; Reserved. Always program to 0
BIT=3 ;0/1 I/O Map Hole-A
BIT=2 ; Reserved. Always program to 0
BIT=1 ;0/1 Memory Map Hole-B
BIT=0 ; Reserved. Always program to 0
;********************************************************************
INDEX=10h ;I/O HOLE-A LOW ADDRESS (Reset State = 00H), R/W
;********************************************************************
BIT=76543210 ;=Start Address of I/O HOLE-A (Address 11 DOWN to 4)
;********************************************************************
INDEX=11h ;I/O HOLE-A HIGH ADDRESS (Reset State = 00H), R/W
;********************************************************************
BIT=76543210 ;=End Address of I/O HOLE-A (Address 11 DOWN to 4)
;********************************************************************
INDEX=19h ;MEM HOLE-B START ADDRESS, LOWER (Reset State = 00H), R/W
;********************************************************************
BIT=76543210 ;=Address of MEM HOLE-B Start (Address 21 DOWN to 14)
;********************************************************************
INDEX=1Ah ;MEM HOLE-B START ADDRESS, UPPER (Reset Stste = 00H), R/W
;********************************************************************
BIT=76 ; Reserved. Always program to 0
BIT=543210 ;=Address of MEM HOLE-B Start (Address 27 DOWN to 22)
;********************************************************************
INDEX=1Ch ;MEM HOLE-B END ADDRESS, LOWER (Reset State = 00h) , R/W
;********************************************************************
BIT=76543210 ;=Address of MEM HOLE-B End (Address 21 DOWN to 14)
;********************************************************************
INDEX=1Dh ;MEM HOLE-B END ADDRESS, UPPER (Reset State = 00H) , R/W
;********************************************************************
BIT=76 ; Reserved. Always program to 0
BIT=543210 ;=Address of MEM HOLE-B End (address 27 DOWN to 22)
;********************************************************************
NAME=HT342 ;HTK340 Shasta 486 HT342 Register Descriptions
;********************************************************************
INDEXPORT=28h
DATENPORT=24h
;********************************************************************
INDEX=20h ;Identifier Port Read (Write Ignored)
;********************************************************************
BIT=7654 ;0010=DRAM controller identifier
BIT=3210 ;0000=Revision number (0=Rev. A)
;********************************************************************
INDEX=21h ;Feature Port (Reset State = 00H) Read (Write Ignored)
;********************************************************************
BIT=76543210 ; Reserved
;********************************************************************
INDEX=24h ;DRAM Options Port #1 (Reset Staste = 00H), R/W
;********************************************************************
BIT=7 ;0/1 Staggered Refresh
BIT=6 ;REFRESH_TYPE
0=RAS Only Refresh
1=CAS Before RAS Refresh
BIT=5 ;0/1 DRAM Paging
BIT=432 CAS INTERLEAVE
000=No interleave
001=2-way interleave on LOW Banks
010=2-way interleave on HIGH Banks
011=2-way interleave on Both LOW and HIGH Banks
100=4-way interleave
101=Reserved. Do not program
110=Reserved. Do not program
111=Reserved. Do not program
BIT=10 ;BANKS
00=1 bank
01=2 banks
10=3 banks
11=4 banks
;********************************************************************
INDEX=25h ;DRAM Options Port #2 (Reset State = 00H)
;********************************************************************
BIT=76 ;Type of DRAMs in bank 3
00=256K DRAM type
01=1Mb DRAM type
10=4Mb DRAM type
11=16Mb DRAM type
BIT=54 ;Type of DRAMs in bank 2
00=256K DRAM type
01=1Mb DRAM type
10=4Mb DRAM type
11=16Mb DRAM type
BIT=32 ;Type of DRAMs in bank 1
00=256K DRAM type
01=1Mb DRAM type
10=4Mb DRAM type
11=16Mb DRAM type
BIT=10 ;Type of DRAMs in bank 0
00=256K DRAM type
01=1Mb DRAM type
10=4Mb DRAM type
11=16Mb DRAM type
;********************************************************************
INDEX=26h ;DRAM Options Port #3 (Reset State = FFH), R/W
;********************************************************************
BIT=7 ;CAS HOLD on RAS (CAS before RAS REFRESH)
0=1 HCLK
1=2 HCLKs
BIT=6 ;CAS PRECHARGE
0=0,5 HCLK
1=1 HCLK
BIT=5 ;CAS BURST DELAY
0=NONE
1=1 HCLK
BIT=4 ;CAS DELAY (WRITES)
0=1 HCLK
1=2 HCLKs
BIT=3 ;CAS DELAY (READS)
0=1 HCLK
1=2 HCLKs
BIT=2 ;CAS ACTIVE TIME (WRITES)
0=1 HCLK
1=2 HCLKs
BIT=10 ;CAS ACTIVE TIME (READS)
00=1 HCLK
01=2 HCLKs
10=3 HCLKs
11=4 HCLKs
;********************************************************************
INDEX=27h ;DRAM Options Port #4 (Reset State = FFH), R/W
;********************************************************************
BIT=7 ;RAS Delay
0=No RAS Delay
1=1 HCLK
BIT=65 ;RAS ACTIVE (WRITES)
00=2 HCLKs
01=3 HCLKs
10=4 HCLKs
11=5 HCLKs
BIT=432 ;RAS ACTIVE (READS)
000=2 HCLKs
001=3 HCLKs
010=4 HCLKs
011=5 HCLKs
100=6 HCLKs
101=7 HCLKs
110=8 HCLKs
111=9 HCLKs
BIT=10 ;RAS PRECHARGE
00=1 HCLK
01=2 HCLKs
10=3 HCLKs
11=4 HCLKs
;********************************************************************
INDEX=28h ;Data Transfer Control Port (Reset State = 00H) , R/W
;********************************************************************
;!!!! Achtung Register für doppeltindizierte Adressierung
;!!!! Die Doppeladressierung unterstützt die aktuelle Version
;!!!! von Chipset noch nicht
;!!!! betrifft EMS, Shadow, Cachable, R/W von 16K-Speicherbereichen
;!!!! für den Adreßbereich von 640 KB bis 1 MByte
;!!!! Register 28 legt den Transfertyp fest:
BIT=7 ;Initiate Transfer
0=No action.
1=Initiate Transfer
BIT=6 ;Read/Write Transfer
0=Read transfer.
1=Write transfer.
BIT=54 ; Reserved. Do not change contents.
BIT=3210 ;Transfer/destination
0000=EMS translation RAM location (MSB)
0001=EMS translation RAM location (LSB)
0010=REMAP RAM translation location
0011=EMS Page Descriptor RAM location
0100=Reserved. Do not program.
0101=Reserved. Do not program.
0110=Reserved. Do not program.
0111=Reserved. Do not program.
1000=NON_CACHEHIMEM register (MSB)
1001=NON_CACHEHIMEM register (LSB)
1010=NON_CACHE1MLO register
1011=NON_CACHE1MHI register
1100=TOP_OF_REMAP_MEMORY register (MSB)
1101=TOP_OF_REMAP_MEMORY register (LSB)
1110=TOP_OF_MEMORY register (MSB)
1111=TOP_OF_MEMORY register (LSB)
;********************************************************************
INDEX=29h ;RAM Address Register (Reset State = 00H), R/W
;********************************************************************
;!!!! Achtung Register für doppeltindizierte Adressierung
;!!!! Die Doppeladressierung unterstützt die aktuelle Version
;!!!! von Chipset noch nicht
;!!!! betrifft EMS, Shadow, Cachable, R/W von 16K-Speicherbereichen
;!!!! für den Adreßbereich von 640 KB bis 1 MByte
;!!!! RAM Address Page 0: von Segment A000 bis A3FF
;!!!! Page 1: " A400 bis A7FF
;!!!! etc.
BIT=765 ; Reserved. Do not change contents.
BIT=43210 ;= RAM address register contents
;********************************************************************
INDEX=2Ah ;Data Transfer Port (Reset State = 00H), R/W
;********************************************************************
;!!!! Achtung Register für doppeltindizierte Adressierung
;!!!! Die Doppeladressierung unterstützt die aktuelle Version
;!!!! von Chipset noch nicht
;!!!! betrifft EMS, Shadow, Cachable, R/W von 16K-Speicherbereichen
;!!!! für den Adreßbereich von 640 KB bis 1 MByte
;!!!! Über den Data Transfer Port wird für die ausgewählte
;!!!! RAM Address Page die gewünschte Eigenschaft übermittelt:
BIT=0 ;0/1 Shadow
BIT=1 ;0/1 Read
BIT=2 ;0/1 Write
BIT=3 ;0/1 Cacheing
BIT=4 ;Reserved
BIT=5 ;EMS Translation
BIT=76 ;Reserved
;********************************************************************
INDEX=2Bh ;Other options (Reset State = 00H), R/W
;********************************************************************
BIT=7 ;Reserved
0=Reserved
1=Reserved
BIT=6 ;0/1 Middle BIOS
BIT=5 ;0/1 Data Pipeline
BIT=4 ;0/1 DMA Flow-thru Mode
; ; korresponds to Index 6, Bit 2
BIT=3 ;IO_DECODE
0=10-bit I/O Decode
1=16-bit I/O Decode
BIT=2 ;Reserved
0=Reserved. Do not program
1=Reserved. Do not program
BIT=1 ;16-bit DMA bridge
0=Enable (normal)
1=Disable (only for local 32 Bit DMA Devices)
BIT=0 ;0/1 Write Buffering
;********************************************************************
INDEX=2Dh ;DRAM Options Port #5 (Reset State = 03H), R/W
;********************************************************************
BIT=765 ; Reserved. Do not change contents.
BIT=4 ;0/1 10uS RAS Timeout
BIT=32 ;BUS Speed
00=33MHz
01=25MHz
10=20MHz
11=16MHz
BIT=10 ;BUS Recovery for DRAM cycles
00=No recovery
01=1 HCLK
10=0,5 HCLK
11=1 HCLK
;********************************************************************