Magazyn Enter 1999 January

home *** CD-ROM | disk | FTP | other *** search

/ Magazyn Enter 1999 January / enter_01_1999_2.iso / BIOS / ctchip34 / SATURN.CFG < prev next >

Wrap

Text File | 1996-09-05 | 15KB | 390 lines

;********************************************************** NAME=82420ZX; (Saturn) ;********************************************************** INDEXPORT=0CF8h ;; CONFADDR DATENPORT=0CFCh ;; CONFDATA MODE=DIRECT ConfigAccess=2 MACRO OPEN=0CF8h:11110000,0CFAh:00000000 MACRO CLOSE=0CF8h:00000000,0CFAh:00000000 BASEADR=C000h *IF 0:==$FFFF WRITELN "CONFIGAccess 2 nicht implementiert" *ENDIF ;; Konditionen für IF-Abfragen (VerANDed) MACRO INTEL = 0:==$8086 MACRO Saturn = INTEL, 2:==$0483 *IF Saturn WRITELN "Intel Saturn 82420ZX" *ELSE WRITELN "Chip nicht identifiziert" Exit *ENDIF MACRO FREEZE= Flush,50h:xxxxx0xx MACRO CacheOFF = Freeze, WBINVD MACRO CacheON = Flush,50h:xxxxx1xx, Flush,50h:xxxxx1xx MACRO L1OFF = Cacheoff, CDNW:=11, WBINVD, CacheON ;; Bits CD und NW in CR0 auf 1 MACRO L1ON = Cacheoff, CDNW:=00, WBINVD, CacheON ;; Bits CD und NW in CR0 auf 1 MACRO L2OFF = Cacheoff, FLUSH, 52h:xxxxxxx0, CacheON MACRO L2ON = Cacheoff, FLUSH, 52h:xxxxxxx1, CacheON MACRO L2WB = Cacheoff, FLUSH, 52h:xxxxxx11, CacheON ;; MACRO L2WT = Cacheoff, FLUSH, 52h:xxxxxx01, CacheON Let rwc = x111 ;; read write Cacheable Let rwn = x011 ;; read write not Cacheable Let won = x010 ;; Write only not Cacheable Let roc = x101 ;; Read only, cacheable Let ron = x001 ;; Read only not Cacheable Let bus = x000 ;; Read/Write to PCI Bus MACRO SF0 = Cacheoff, 59h:#1#xxxx, Cacheon MACRO sC0 = Cacheoff, 5Ah:xxxx#1#, Cacheon MACRO sC4 = Cacheoff, 5Ah:#1#xxxx, Cacheon MACRO sC8 = Cacheoff, 5Bh:xxxx#1#, Cacheon MACRO sCC = Cacheoff, 5Bh:#1#xxxx, Cacheon MACRO sD0 = Cacheoff, 5Ch:xxxx#1#, Cacheon MACRO sD4 = Cacheoff, 5Ch:#1#xxxx, Cacheon MACRO sD8 = Cacheoff, 5Dh:xxxx#1#, Cacheon MACRO sDC = Cacheoff, 5Dh:#1#xxxx, Cacheon MACRO sE0 = Cacheoff, 5Eh:xxxx#1#, Cacheon MACRO sE4 = Cacheoff, 5Eh:#1#xxxx, Cacheon MACRO sE8 = Cacheoff, 5Fh:xxxx#1#, Cacheon MACRO sEC = Cacheoff, 5Fh:#1#xxxx, Cacheon ;********************************************************** INDEX16=0 ; VID PCI Vendor Identification r/o ;********************************************************** BIT=15..00 ; Vendor Identification $8086= INTEL else = other Vendor ;********************************************************** INDEX16=2 ;DID PCI Divice Identification r/o ;********************************************************** BIT=15..00 ; Device Identification $0483= Saturn else= unknown ;********************************************************** INDEX16=4 ; PCICMD PCI Command Register r/w ;********************************************************** BIT=15..09 ; Reserved BIT=08 ;0/1 SERRE BIT=06 ;0/1 Parity Error (Master Enable) BIT=02 ;0/1 Bus Master Operations BIT=01 ;0/1 Memory Access BIT=00 ;0/1 I/O-Access ;********************************************************** INDEX16=6h ; PCISTS PCI Status Register (r/w) ;********************************************************** BIT=15 ;reserved BIT=14 ;Signaled System Error BIT=13 ;Received Master Abort Status BIT=12 ;Received Target Abort Status BIT=11 ;reserved BIT=10,09 ;DevSel 00=FAST 01=Medium 10=SLOW 11=reserved BIT=08 ;Data Parity 0= not detected 1= detected ;********************************************************** INDEX=8 ;RID Revision IDentification Register r/o ;********************************************************** BIT=7..0 ;PCI Cache/Memory-Controller ;********************************************************** INDEX=9 ;RLPI Register-Level Programming Interface r/o ;********************************************************** BIT=7..0 00=no register-level Programming Interface ;********************************************************** INDEX=0Ah ;SUBC Sub-Class-Code r/o ;********************************************************** BIT=7..0 00=PCMC is host Bridge ;********************************************************** INDEX=0Bh ;BASEC Base Class Code r/o ;********************************************************** BIT=7..0 $06=PCMC is Bridge Device ;********************************************************** INDEX=0Dh ; MLT Master Latency Timer Register r/w ;********************************************************** BIT=7654 ;Master Latency Timer, bus clocks = 16 x this value ;********************************************************** INDEX=0Fh ;BIST BIST-Register r/o ;********************************************************** BIT=7 ;0/1 BIST (ro), not supported by 82434LX/NX BIT=6 ;Start BIST (r/w), not supported by 82434LX/NX BIT=3..0 ;Completion Code (ro) ;********************************************************** INDEX=50h ;HCS HOST CPU Selection Register r/o, r/w ;********************************************************** BIT=765 ;Host CPU Type 000=Intel486 DX 001=Intel486 SX 010=Intel486 DX2, DX4 100= DX2 -WB else Reserved BIT=2 ;L1-Cache 0=L1-Freeze, #KEN always high 1=#KEN aktiv, BIT=10 ;Host Operating Frequency 00= 25 MHz 01= 33 MHz else Reserved ;********************************************************** INDEX=51h ;DFC Deturbo Frequency Control Register r/w ;********************************************************** BIT=76543210 ;Deturbo Mode Frequency Adjustment Value ;********************************************************** INDEX=52h ;SCC L2-Cache Control Register r/w ;********************************************************** BIT=76 ;L2-Cachesize 00=64 KBytes 01=128 KBytes 10=256 KBytes 11=512 KBytes BIT=5 ;L1 Cache present 0= No L1-Cache 1= L1-Cache present BIT=43 ;Tag Address Width 10 = 7 Bit 00 = 8 Bit 01 = 9 Bit 11 = reserved BIT=2 ;L2 Cache Lead Off Cycle 0= 3-1-1-1 (read) 3 (Write) 1= 2-1-1-1 (read) 2 (Write) BIT=1 ;L2 Write Policy 0=Write Through 1=Write Back BIT=0 ;0/1 L2-Cache ;********************************************************** INDEX=53h ;HBC Host Read/Write Buffer Control r/w ;********************************************************** BIT=7..2 ;Reserved BIT=1 ;0/1 Host-to-PCI Posting BIT=0 ;0/1 Host-to-Memory Posting ;********************************************************** INDEX=54h ;PBC PCI Read/Write Buffer Control Register ;********************************************************** BIT=7..2 ;Reserved BIT=1 ;0/1 CPU to PCI Burst Write BIT=0 ;0/1 PCI to Memory Posting ;********************************************************** INDEX=55h ;DRAM Operation Mode Register r/w ;********************************************************** BIT=6 ;0/1 Fast Page Mode Data Read BIT=5 ;0/1 Pipeline Mode BIT=3 ;1/0 DRAM-Refresh BIT=1 ;0/1 Fast Page Mode Code Read BIT=0 ;0/1 Fast Page Mode Write ;********************************************************** INDEX=56h ;System Exception Handling Register r/w ;********************************************************** BIT=6 ;Target Abort Status BIT=5 ;Cache Parity Error BIT=4 ;Memory Parity Error BIT=3 ;Reserved BIT=2 ;0/1 Target Abort Error BIT=1 ;0/1 Cache Parity Error BIT=0 ;0/1 Memory Parity error ;********************************************************** INDEX=59h ;PAM0 Programmable Attribute Register 0 r/w ;********************************************************** BIT=7654 ; F0000h..FFFFFh, 64 KB xx00= DRAM Disabled, Accesses directed to PCI x001= Read Only DRAM Write Protected, Non-Cacheable x101= Read Only, DRAM Write Protected, Cacheable for Code x010= Write Only x011= Read/write,Non-Cacheable x111= Read/write,Cacheable BIT=3210 ; 80000h..9FFFFh, 128 KB xx00= DRAM Disabled, Accesses directed to PCI x001= Read Only DRAM Write Protected, Non-Cacheable x101= Read Only, DRAM Write Protected, Cacheable for Code x010= Write Only x011= Read/write,Non-Cacheable x111= Read/write,Cacheable ;********************************************************** INDEX=5Ah ;PAM1 Programmable Attribute Register 1 r/w ;********************************************************** BIT=7654 ; C4000h..C7FFFh, 16 KB xx00= DRAM Disabled, Accesses directed to PCI x001= Read Only DRAM Write Protected, Non-Cacheable x101= Read Only, DRAM Write Protected, Cacheable for Code x010= Write Only x011= Read/write,Non-Cacheable x111= Read/write,Cacheable BIT=3210 ; C0000h..C3FFFh, 16 KB xx00= DRAM Disabled, Accesses directed to PCI x001= Read Only DRAM Write Protected, Non-Cacheable x101= Read Only, DRAM Write Protected, Cacheable for Code x010= Write Only x011= Read/write,Non-Cacheable x111= Read/write,Cacheable ;********************************************************** INDEX=5Bh ;PAM2 Programmable Attribute Register 2 r/w ;********************************************************** BIT=7654 ; CC000h..CFFFFh, 16 KB xx00= DRAM Disabled, Accesses directed to PCI x001= Read Only DRAM Write Protected, Non-Cacheable x101= Read Only, DRAM Write Protected, Cacheable for Code x010= Write Only x011= Read/write,Non-Cacheable x111= Read/write,Cacheable BIT=3210 ; C8000h..CBFFFh, 16 KB xx00= DRAM Disabled, Accesses directed to PCI x001= Read Only DRAM Write Protected, Non-Cacheable x101= Read Only, DRAM Write Protected, Cacheable for Code x010= Write Only x011= Read/write,Non-Cacheable x111= Read/write,Cacheable ;********************************************************** INDEX=5Ch ;PAM3 Programmable Attribute Register 3 r/w ;********************************************************** BIT=7654 ; D4000h..D7FFFh, 16 KB xx00= DRAM Disabled, Accesses directed to PCI x001= Read Only DRAM Write Protected, Non-Cacheable x101= Read Only, DRAM Write Protected, Cacheable for Code x010= Write Only x011= Read/write,Non-Cacheable x111= Read/write,Cacheable BIT=3210 ; D0000h..D3FFFh, 16 KB xx00= DRAM Disabled, Accesses directed to PCI x001= Read Only DRAM Write Protected, Non-Cacheable x101= Read Only, DRAM Write Protected, Cacheable for Code x010= Write Only x011= Read/write,Non-Cacheable x111= Read/write,Cacheable ;********************************************************** INDEX=5Dh ;PAM4 Programmable Attribute Register 4 r/w ;********************************************************** BIT=7654 ; DC000h..DFFFFh, 16 KB xx00= DRAM Disabled, Accesses directed to PCI x001= Read Only DRAM Write Protected, Non-Cacheable x101= Read Only, DRAM Write Protected, Cacheable for Code x010= Write Only x011= Read/write,Non-Cacheable x111= Read/write,Cacheable BIT=3210 ; D8000h..DBFFFh, 16 KB xx00= DRAM Disabled, Accesses directed to PCI x001= Read Only DRAM Write Protected, Non-Cacheable x101= Read Only, DRAM Write Protected, Cacheable for Code x010= Write Only x011= Read/write,Non-Cacheable x111= Read/write,Cacheable ;********************************************************** INDEX=5Eh ;PAM5 Programmable Attribute Register 5 r/w ;********************************************************** BIT=7654 ; E4000h..E7FFFh, 16 KB xx00= DRAM Disabled, Accesses directed to PCI x001= Read Only DRAM Write Protected, Non-Cacheable x101= Read Only, DRAM Write Protected, Cacheable for Code x010= Write Only x011= Read/write,Non-Cacheable x111= Read/write,Cacheable BIT=3210 ; E0000h..E3FFFh, 16 KB xx00= DRAM Disabled, Accesses directed to PCI x001= Read Only DRAM Write Protected, Non-Cacheable x101= Read Only, DRAM Write Protected, Cacheable for Code x010= Write Only x011= Read/write,Non-Cacheable x111= Read/write,Cacheable ;********************************************************** INDEX=5Fh ;PAM6 Programmable Attribute Register 6 r/w ;********************************************************** BIT=7654 ; EC000h..EFFFFh, 16 KB xx00= DRAM Disabled, Accesses directed to PCI x001= Read Only DRAM Write Protected, Non-Cacheable x101= Read Only, DRAM Write Protected, Cacheable for Code x010= Write Only x011= Read/write,Non-Cacheable x111= Read/write,Cacheable BIT=3210 ; E8000h..EBFFFh, 16 KB xx00= DRAM Disabled, Accesses directed to PCI x001= Read Only DRAM Write Protected, Non-Cacheable x101= Read Only, DRAM Write Protected, Cacheable for Code x010= Write Only x011= Read/write,Non-Cacheable x111= Read/write,Cacheable ;********************************************************** INDEX=60h ; DRB0, DRAM Row Boundary Register r/w INDEX=61h ; DRB1, DRAM Row Boundary Register r/w INDEX=62h ; DRB2, DRAM Row Boundary Register r/w INDEX=63h ; DRB3, DRAM Row Boundary Register r/w ;********************************************************** INDEX16=68 ;Memory Hole 0 Register ;********************************************************** BIT=15 ;0/1 Memory Hole 0 BIT=14..12 ;Memory Hole 0 Size 000=64 KByte 001=128 KByte 010=256 KByte 011=512 KByte 100=1 MByte 101=2 MByte 110=4 MByte 111=8 MByte BIT=10..00 ;Memory Hole-0-Address ;********************************************************** INDEX16=6A ;Memory Hole 1 Register ;********************************************************** BIT=15 ;0/1 Memory Hole 1 BIT=14..12 ;Memory Hole 1 Size 000=64 KByte 001=128 KByte 010=256 KByte 011=512 KByte 100=1 MByte 101=2 MByte 110=4 MByte 111=8 MByte BIT=10..00 ;Memory Hole-1-Address