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Magazyn Enter 1999 January
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IBM486.CFG
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1993-12-06
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5KB
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131 lines
;**********************************************************
; Blue Lightning
NAME=486DLC3 ; (oder 486SLC2) IBMs Blue Lightning
;**********************************************************
MODE=RDMSR ; special Registers
;**********************************************************
INDEX=1000:2 ; Processor Operation Register, Byte 2
;**********************************************************
BIT=76543 ; reserved
BIT=2 ;0/1 LPPLA: Low Power PLA
BIT=1 ;0/1 BUSRD: Bus Read (ignore Cache)
BIT=0 ;0/1 CPGE: Cache Parity Enable Error
;**********************************************************
INDEX=1000:1 ; Processor Operation Register, Byte 1
;**********************************************************
BIT=7 ;0/1 CNPX: Cachability of NPX Operands
BIT=6 ; reserved
BIT=5 ;0/1 LPH: Low Power Halt
BIT=4 ;0/1 XTOUT: Extended Out Instruction
BIT=3 ;0/1 CRLD: Cache Reload
BIT=2 ;0/1 IKEN: Internal KEN
BIT=1 ;0/1 DCLM: Disable CACHE Lock Mode
BIT=0 ; reserved
;**********************************************************
INDEX=1000:0 ; Processor Operation Register, Byte 0
;**********************************************************
BIT=7 ;0/1 CE: Internal Cache
BIT=6 ;0/1 DBCS: Cache Double Byte Character Set
BIT=5 ;0/1 PMI: Power Management Interrupt
BIT=4 ;0/1 ASNP: ADS# Snooping
BIT=3 ;0/1 SNP: Snooping
BIT=2 ;0/1 A20M: A20_Mask
BIT=1 ;0/1 CPC: Cache Parity Checking
BIT=0 ; CPE: Cache Parity Error
0= not occured
1= occured
;**********************************************************
INDEX=1001:6 ; Cache Region Control Register Byte 6
;**********************************************************
BIT=76543210 ; ECMLR ..4GB Extended Cache Mem Limit Hi-Byte
;**********************************************************
INDEX=1001:5 ; Cache Region Control Register Byte 5
;**********************************************************
BIT=76543210 ; ECMLR ..4GB Extended Cache Mem Limit Lo-Byte
;**********************************************************
INDEX=1001:4 ; Cache Region Control Register Byte 4
;**********************************************************
BIT=76543210 ; CMLR 1..16 MB Cache Mem Limit
;**********************************************************
INDEX=1001:3 ; Cache Region Control Register Byte 3
;**********************************************************
BIT=76543210 ; LMROR 1Meg READ Only Hi-Byte
;**********************************************************
INDEX=1001:2 ; Cache Region Control Register Byte 2
;**********************************************************
BIT=76543210 ; LMROR 1Meg READ Only Lo-Byte
;**********************************************************
INDEX=1001:1 ; Cache Region Control Register Byte 1
;**********************************************************
BIT=76543210 ; LMCR: 1Meg Cacheable hi-Byte
;**********************************************************
INDEX=1001:0 ; Cache Region Control Register Byte 0
;**********************************************************
BIT=76543210 ; LMCR: 1Meg Cacheable Lo-Byte
;**********************************************************
INDEX=1002:3 ; Clock Control Register Byte 3
;**********************************************************
BIT=5 ; 0/1 EDFS: External Dynamic Frequency Shift
BIT=4 ;0/1 DFSRDY:Dynamic Frequency Shift Ready
BIT=3 ;0/1 DFSREQ:Dynamic Frequency Shift Request
BIT=210 ;Clock Mode Selection
000= 1:1 Clock Mode
011= 2:1 Clock Mode
100= 3:1 Clock Mode
;**********************************************************
INDEX=1004:3 ; Processor Control Register Byte 3 /(DLC3 only)
;**********************************************************
BIT=7 ; OS2B:
0= for DD1-Hardware
1= for DD0-Hardware for OS/2-Boot
BIT=6 ; CR0: MOV CR0 Decode
0= for DD0, DD1A, DD1B, DD1D-Hardware
1= for DD1C-Hardware
BIT=5 ; reserved
BIT=4 ; CLP: Cache Low Power
0= DD0: ever, DD1 Cache stays on
1= DD1: Disable Cache when not in Use
BIT=3 ; reserved
BIT=2 ; NOP:
0= DD0: NOP 2T, DD1: NOP 3T
1= DD0: NOP 3T, DD1: NOP 2T
BIT=1 ;0/1 NA16: Bus Pipelining for 16 Bit
;**********************************************************
INDEX=1004:0 ; Processor Control Register Byte 0 (DLC3 only)
;**********************************************************
BIT=4 ;0/1 MOVS Split
BIT=3 ;0/1 Power Saving Cache Feature
BIT=2 ;Reserved
BIT=1 ;0/1 Enable MOV CRx-Decode (DD1B, DD1C is reversed)
BIT=0 ;Reserved