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1987-08-26
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5KB
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213 lines
TITLE B8ZS_DECODER
PATTERN B8ZS DECODER PAL
REVISION 1.04
AUTHOR THERESA SHAFER
COMPANY MMI
DATE 11/24/86
CHIP B8ZS_DECODER PAL16R8
T1_CK /RST PPI NPI NC NC NC NC NC GND
/OE NC Q0 Q1 Q2 Q3 /BPV /B8ZS DATA VCC
;
; INPUTS: T1_CK EXTERNAL CLOCK
; /OE ACTIVE LOW OUTPUT ENABLE SIGNAL
; /RST ACTIVE LOW MASTER RESET SIGNAL
; PPI SERIAL POSITIVE PUSLE DATA STREAM
; TO BE DECODED
; NPI SERIAL NEGATIVE PUSLE DATA STREAM
; TO BE DECODED
; OUTPUTS: DATA DATA WHICH IS LOADED INTO THE SHIFT
; REGISTER
; Q3 - Q0 STATE MACHINE OUTPUTS
; /BPV LOW ACTIVE SIGNAL WHICH INDICATES THAT
; BIPOLAR VIOLATION HAS OCCURRED
; /B8ZS LOW ACTIVE SIGNAL WHICH INDICATES THAT
; ZERO SUBSTITUTION HAS OCCURRED
EQUATIONS
; DATA OUTPUT
/DATA := /PPI * /NPI;
; /BPV AND /B8ZS FLAGS
BPV := PPI * /Q2 * Q1
+ PPI * /Q3 * Q2 * /Q0
+ NPI * Q2 * Q1
+ NPI * /Q3 * Q1 * /Q0
+ /PPI * /Q2 * /Q1 * Q0
+ /PPI * Q3 * /Q1 * Q0
+ /NPI * /Q3 * Q2 * /Q1
+ /NPI * Q2 * /Q1 * /Q0;
B8ZS := /PPI * NPI * /Q3 * Q2 * /Q1 * Q0
+ PPI * /NPI * Q3 * Q2 * /Q1 * Q0;
; STATE MACHINE WHICH DETECTS B8ZS SEQUENCE
; STATE VARIABLES [Q3,Q2,Q1,Q0]
; WITH THE FOLLOWING STATE ASSIGNMENTS
; SP0 = [0,0,1,1]
; SP1 = [1,0,1,1]
; SP2 = [1,0,1,0]
; SP3 = [0,0,0,0]
; SP4 = [0,1,0,0]
; SP5 = [0,0,1,0]
; SP6 = [1,1,0,0]
; SP7 = [1,1,0,1]
; SN0 = [1,1,1,1]
; SN1 = [0,1,1,1]
; SN2 = [1,1,1,0]
; SN3 = [1,0,0,0]
; SN4 = [1,0,0,1]
; SN5 = [0,1,1,0]
; SN6 = [0,0,0,1]
; SN7 = [0,1,0,1]
/Q3 := PPI * /RST
+ /NPI * /Q3 * /Q2 * /Q1 * /Q0 * /RST
+ /NPI * Q3 * /Q2 * Q1 * /Q0 * /RST
+ /NPI * /Q3 * Q2 * Q1 * /Q0 * /RST
+ /NPI * Q3 * /Q1 * Q0 * /RST
+ /NPI * Q3 * Q2 * Q0 * /RST
+ NPI * /Q3 * Q2 */Q1 * /Q0 * /RST;
/Q2 := PPI * Q1 * /RST
+ PPI * Q2 * /RST
+ /NPI * /Q3 * Q2 * /Q0 * /RST
+ /NPI * Q3 * Q1 * /Q0 * /RST
+ /PPI * /NPI * /Q3 * /Q1 * /RST
+ /NPI * /Q2 * Q1 * Q0 * /RST
+ Q3 * /Q2 * /Q1 * /Q0 * /RST
+ /Q3* Q2 * /Q1 * /Q0 * /RST;
/Q1 := PPI * /Q3 * /Q2 * /Q1 * /RST
+ /PPI * /NPI * /Q2 * /Q0 * /RST
+ /PPI * /NPI * Q1 * /Q0 * /RST
+ /PPI * NPI * Q3 * /Q1 * /Q0 * /RST;
/Q0 := PPI * /Q3 * /Q2 * /Q1 * /Q0 * /RST
+ PPI * Q3 * /Q2 * /Q1 * Q0 * /RST
+ /PPI * /NPI * /Q2 * /Q0 * /RST
+ /PPI * /NPI * Q3 * /Q0 * /RST
+ /PPI * /NPI * /Q3 * /Q2 * /Q1 * /RST
+ /PPI * /NPI * Q3 * /Q2 * Q1 * /RST
+ /PPI * /NPI * /Q3 * Q2 * Q1 * Q0 * /RST
+ /PPI * NPI * /Q3 * Q2 * /Q1 * /Q0 * /RST;
; .........................................................
; .........................................................
SIMULATION
TRACE_ON T1_CK /OE /RST PPI NPI
Q3 Q2 Q1 Q0 /BPV /B8ZS
SETF OE ; ENABLE OUTPUT
RST ; RESET
/PPI /NPI
CLOCKF T1_CK
SETF RST
CLOCKF T1_CK
SETF /PPI /NPI
/RST
CLOCKF T1_CK
; NORMAL DECODING
SETF PPI /NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF /PPI NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF PPI /NPI
CLOCKF T1_CK
SETF /PPI NPI
CLOCKF T1_CK
SETF PPI /NPI
CLOCKF T1_CK
; DETECT B8ZS SEQUENCE
; + SEQUENCE
SETF /PPI /NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF PPI /NPI
CLOCKF T1_CK
SETF /PPI NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF /PPI NPI
CLOCKF T1_CK
SETF PPI /NPI
CLOCKF T1_CK
; SET-UP FOR NEXT SEQUENCE
SETF /PPI NPI
CLOCKF T1_CK
; - SEQUENCE
SETF /PPI /NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF /PPI NPI
CLOCKF T1_CK
SETF PPI /NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF PPI /NPI
CLOCKF T1_CK
SETF /PPI NPI
CLOCKF T1_CK
; DETECT BIPOLAR VIOLATIONS
SETF /PPI /NPI
CLOCKF T1_CK
SETF PPI /NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF PPI /NPI
CLOCKF T1_CK
SETF /PPI NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF /PPI NPI
CLOCKF T1_CK
SETF PPI /NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF /PPI /NPI
CLOCKF T1_CK
SETF PPI /NPI
CLOCKF T1_CK
TRACE_OFF