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- PAL20R6 PAL DESIGN SPECIFICATION
- TESTING OUTPUTS USING PAL20R4 Bob Metzler 12/30/90
- 13-INPUT REGISTERED PRIORITY ENCODER
- EMERALD CITY,WASHINGTON
- CLK I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 GND
- /OC I10 FLAG Q3 Q2 NC NC Q1 Q0 I11 I12 VCC
-
- ; equations go here
-
- /Q0 := /I0* I1
- + /I0*/I1*/I2* I3
- + /I0*/I1*/I2*/I3*/I4* I5
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6* I7
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8* I9
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10* I11
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12
-
- /Q1 := /I0*/I1* I2
- + /I0*/I1*/I2* I3
- + /I0*/I1*/I2*/I3*/I4*/I5* I6
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6* I7
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9* I10
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10* I11
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12
-
- /Q2 := /I0*/I1*/I2*/I3* I4
- + /I0*/I1*/I2*/I3*/I4* I5
- + /I0*/I1*/I2*/I3*/I4*/I5* I6
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6* I7
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11* I12
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12
-
- /Q3 := /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7* I8
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8* I9
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9* I10
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10* I11
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11* I12
- + /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12
-
- /FLAG = /I0*/I1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/I11*/I12
-
- FUNCTION TABLE
-
- CLK /OC I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 Q3 Q2 Q1 Q0 FLAG
-
- ; CHIP FIFTEEN INPUTS --OUTPUTS--
- ;CONTROL 111 QQQQ
- ;CLK /OC 2109876543210 3210 FLAG COMMENTS
- ------------------------------------------------------------------------
- C L XXXXXXXXXXXXH HHHH H I0 INTERRUPT HIGHEST PRIORITY
- C L XXXXXXXXXXXHL HHHL H I1 INTERRUPT
- C L XXXXXXXXXXHLL HHLH H I2 INTERRUPT
- C L XXXXXXXXXHLLL HHLL H I3 INTERRUPT
- C L XXXXXXXXHLLLL HLHH H I4 INTERRUPT
- C L XXXXXXXHLLLLL HLHL H I5 INTERRUPT
- C L XXXXXXHLLLLLL HLLH H I6 INTERRUPT
- C L XXXXXHLLLLLLL HLLL H I7 INTERRUPT
- C L XXXXHLLLLLLLL LHHH H I8 INTERRUPT
- C L XXXHLLLLLLLLL LHHL H I9 INTERRUPT
- C L XXHLLLLLLLLLL LHLH H I10 INTERRUPT
- C L XHLLLLLLLLLLL LHLL H I11 INTERRUPT
- C L HLLLLLLLLLLLL LLHH H I12 INTERRUPT LOWEST PRIORITY
- C L LLLLLLLLLLLLL LLLL L NO INTERRUPT
- X H XXXXXXXXXXXXX ZZZZ X TEST HI-Z
- ------------------------------------------------------------------------
-
- DESCRIPTION
- The 13-input registered priority encoder accepts 13 active low inputs
- (I0-I12) to load the binary weighted code of the priority order into
- the output registers (Q3-Q0) on the rising edge of the clock (CLK).
-