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  1. ----------------------------------------------------------------
  2. |                                                              |
  3. |                                                              |
  4. |                Digital Equipment Corporation                 |
  5. |                                                              |
  6. |        L          SSSSS     III            1      1          |
  7. |        L         S     S     I            11     11          |
  8. |        L         S           I             1      1          |
  9. |        L          SSSSS      I     XXX     1      1          |
  10. |        L               S     I             1      1          |
  11. |        L         S     S     I             1      1          |
  12. |        LLLLLLL    SSSSS     III           111    111         |
  13. |                                                              |
  14. |        LSI-11 MICROPROCESSOR Instruction Set Summary         |
  15. |                                                              |
  16. |                                                              |
  17. |                                                              |
  18. |                                                              |
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  28. |XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
  29. |XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
  30. |XXXXX  X XXX  XXX XXXXXXXX XXX  XXX XX  XXXX XXXXXXXX XXX  XXX|
  31. |XXXXX  X XXXXXXXX XXXXXXXX XXXXXXXX XX  XXXX XXXXXXXX XXX  XXX|
  32. |XX     X XXX  XXX XX    XX XXX  XXX X    XXX XX    XX XXX  XXX|
  33. |X  XX  X XXX  XXX X  XX  X XXX  XXX XX  XXXX XXXXX  X XXX  XXX|
  34. |X  XX  X XXX  XXX X  XX  X XXX  XXX XX  XXXX XX     X XXX  XXX|
  35. |X  XX  X XXX  XXX X  XX  X XXX  XXX XX  XXXX X  XX  X XXX  XXX|
  36. |XX     X XXX  XXX XX     X XXX  XXX XXX   XX XX     X XXX  XXX|
  37. |XXXXXXXX XXXXXXXX XXXXX  X XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
  38. |XXXXXXXX XXXXXXXX XX    XX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
  39. |XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
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  64. |                                                              |
  65. |                                                              |
  66. |                                                              |
  67. |                                                              |
  68. |Written by     Jonathan Bowen                                 |
  69. |               Programming Research Group                     |
  70. |               Oxford University Computing Laboratory         |
  71. |               8-11 Keble Road                                |
  72. |               Oxford OX1 3QD                                 |
  73. |               England                                        |
  74. |                                                              |
  75. |               Tel +44-865-273840                             |
  76. |                                                              |
  77. |Created        August 1981                                    |
  78. |Updated        April 1985                                     |
  79. |Issue          1.1                Copyright (C) J.P.Bowen 1985|
  80. ----------------------------------------------------------------
  81. ----------------------------------------------------------------
  82. |Mnemonic |Opcode|NZVC|Description               |Notes        |
  83. |---------+------+----+--------------------------+-------------|
  84. |ADCb d   |B055DD|****|Add Carry                 |d=d+C        |
  85. |ADD  s,d |06SSDD|****|Add                       |d=s+d        |
  86. |ASH  s,r |072RSS|****|Arithmetic Shift          |r=r*2^s (EIS)|
  87. |ASHC s,r |073RSS|****|Arithmetic Shift Combined |        (EIS)|
  88. |ASLb d   |B063DD|****|Arithmetic Shift Left     |d=d*2        |
  89. |ASRb d   |B062DD|****|Arithmetic Shift Right    |d=d/2        |
  90. |BCC  a   |1030XX|----|Branch if Carry Clear     |If C=0       |
  91. |BCS  a   |1034XX|----|Branch if Carry Set       |If C=1       |
  92. |BEQ  a   |0014XX|----|Branch if Equal           |If Z=0       |
  93. |BGE  a   |0020XX|----|Branch if Greater or Equal|If NxV=0     |
  94. |BGT  a   |0030XX|----|Branch if Greater Than    |If Zv{NxV}=0 |
  95. |BICb s,d |B4SSDD|**0-|Bit Clear                 |d=d&{~s}     |
  96. |BISb s,d |B5SSDD|**0-|Bit Set (OR)              |d=dvs        |
  97. |BITb s,d |B3SSDD|**0-|Bit Test (AND)            |d&s          |
  98. |BHI  a   |1010XX|----|Branch if Higher          |If CvZ=0     |
  99. |BHIS a   |1030XX|----|Branch if Higher or Same  |If C=0       |
  100. |BLE  a   |0034XX|----|Branch if Less or Equal   |If Zv{NxV}=1 |
  101. |BLT  a   |0024XX|----|Branch if Less Than       |If NxV=1     |
  102. |BLO  a   |1034XX|----|Branch if Lower           |If C=1       |
  103. |BLOS a   |1014XX|----|Branch if Lower or Same   |If CvZ=1     |
  104. |BMI  a   |1004XX|----|Branch if Minus           |If N=1       |
  105. |BNE  a   |0010XX|----|Branch if Not Equal       |If Z=1       |
  106. |BPL  a   |1000XX|----|Branch if Plus            |If N=0       |
  107. |BPT      |000003|----|Breakpoint Trap           |Vector at 14 |
  108. |BR   a   |0004XX|----|Branch                    |PC=PC+2*XX   |
  109. |BVC  a   |1020XX|----|Branch if Overflow Clear  |If V=0       |
  110. |BVS  a   |1024XX|----|Branch if Overflow Set    |If V=1       |
  111. |CALL d   |0047DD|----|Call subroutine           | (= JSR PC,d)|
  112. |CCC      |000257|0000|Clear all Condition Codes |{C,N,V,Z}=0  |
  113. |CLC      |000241|---0|Clear Carry               |C=0          |
  114. |CLN      |000250|0---|Clear Negative            |N=0          |
  115. |CLRb d   |B050DD|0100|Clear                     |d=0          |
  116. |CLV      |000242|--0-|Clear Overflow            |V=0          |
  117. |CLZ      |000244|-0--|Clear Zero                |Z=0          |
  118. |CMPb s,d |B2SSDD|****|Compare                   |s-d          |
  119. |COMb d   |B051DD|**01|Complement                |d=~d         |
  120. |DECb d   |B053DD|***-|Decrement                 |d=d-1        |
  121. |DIV  s,r |071RSS|****|Divide                    |r=r/s   (EIS)|
  122. |EMT  t   |1040TT|----|Emulator Trap             |Vector at 30 |
  123. |FADD r   |07500R|**00|Floating Add              |        (FIS)|
  124. |FDIV r   |07503R|**00|Floating Divide           |        (FIS)|
  125. |FMUL r   |07502R|**00|Floating Multiply         |        (FIS)|
  126. |FSUB r   |07501R|**00|Floating Subtract         |        (FIS)|
  127. |HALT     |000000|----|Halt                      |             |
  128. |INCb d   |B052DD|***-|Increment                 |d=d+1        |
  129. |IOT      |000004|----|Input/Output Trap         |Vector at 20 |
  130. |JMP  d   |0001DD|----|Jump                      |PC=d         |
  131. |JSR  r,d |004RDD|----|Jump to Subroutine        |r=PC,PC=d    |
  132. |MARK n   |0064NN|----|Mark stack                |RTS aid      |
  133. |MFPS d   |1067DD|**0-|Move From Processor Status|d=PS   (byte)|
  134. |MOVb s,d |B1SSDD|**0-|Move                      |d=s          |
  135. |MTPS s   |1064SS|****|Move To Processor Status  |PS=s   (byte)|
  136. |MUL  s,r |070RSS|**0*|Multiply                  |r=r*s   (EIS)|
  137. |NEGb d   |B054DD|****|Negate                    |d=-d         |
  138. |NOP      |000240|----|No Operation              |             |
  139. |RESET    |000005|----|Reset external bus        |             |
  140. |RETURN   |000207|----|Return from subroutine    |   (= RTS PC)|
  141. |ROLb d   |B061DD|****|Rotate Left               |d={C,d}<-    |
  142. |RORb d   |B060DD|****|Rotate Right              |d=->{C,d}    |
  143. |RTI      |000002|----|Return from Interrupt     |{PC,PS}=(SP)+|
  144. |RTS  r   |00020R|----|Return from Subroutine    |PC=r,r=(SP)+ |
  145. |RTT      |000006|----|Return from interrupt     |Inhibit T-bit|
  146. |SBCb d   |B056DD|****|Subtract Carry            |d=d-C        |
  147. |SCC      |000277|1111|Set all Condition Codes   |{C,N,V,Z}=1  |
  148. |SEC      |000261|---1|Set Carry                 |C=1          |
  149. |SEN      |000270|1---|Set Negative              |N=1          |
  150. |SEV      |000262|--1-|Set Overflow              |V=1          |
  151. |SEZ      |000264|-1--|Set Zero                  |Z=1          |
  152. |SOB  r,a |077RNN|----|Subtract One and Branch   |PC=PC-2*NN   |
  153. |SUB  s,d |16SSDD|****|Subtract                  |d=d-s        |
  154. |SWAB d   |0003DD|**00|Swap Bytes                |             |
  155. |SXT  d   |0067DD|-*0-|Sign Extend               |d=0 or -1    |
  156. |TRAP t   |1044TT|----|Trap                      |Vector at 34 |
  157. |TSTb d   |B055DD|**00|Test                      |d            |
  158. |WAIT     |000001|----|Wait for interrupt        |             |
  159. |XOR  r,d |074RDD|**0-|Exclusive OR              |d=dxr        |
  160. ----------------------------------------------------------------
  161. ----------------------------------------------------------------
  162. |Mnemonic |Opcode|NZVC|Description                             |
  163. |---------+------+----+----------------------------------------|
  164. |         |     B|    |0 for word, 1 for byte (1 bit)          |
  165. |         |    DD|    |Destination field (6 bits)              |
  166. |         |     N|    |Number (3 bits)                         |
  167. |         |    NN|    |Number (6 bits)                         |
  168. |         |     R|    |Register (3 bits, R0-5/SP/PC)           |
  169. |         |    SS|    |Source field (6 bits)                   |
  170. |         |    TT|    |Number (8 bits)                         |
  171. |         |    XX|    |Offset (8 bits, -128 to +127)           |
  172. |----------------+----+----------------------------------------|
  173. | PSW            |-*01|Flag unaffected/affected/reset/set      |
  174. |                |    |Priority interrupt (Bit 7)              |
  175. | T              |    |Trace trap (Bit 4)                      |
  176. | N              |N   |Negative (Bit 3)                        |
  177. | Z              | Z  |Zero (Bit 2)                            |
  178. | V              |  V |Overflow (Bit 1)                        |
  179. | C              |   C|Carry (Bit 0)                           |
  180. |---------------------+----------------------------------------|
  181. | r                   |Register (mode 0)                       |
  182. | (r)                 |Register deferred (mode 1)              |
  183. | @r                  | ditto                                  |
  184. | (r)+                |Auto-increment (mode 2)                 |
  185. | @(r)+               |Auto-increment deferred (mode 3)        |
  186. | -(r)                |Auto-decrement (mode 4)                 |
  187. | @-(r)               |Auto-decrement deferred (mode 5)        |
  188. | nn(r)               |Index (mode 6)                          |
  189. | @nn(r)              |Index deferred (mode 7)                 |
  190. | #nn                 |Immediate (mode 2, r=PC)                |
  191. | @#nn                |Absolute (mode 3, r=PC)                 |
  192. | nn                  |Relative (mode 6, r=PC)                 |
  193. | @nn                 |Relative deferred (mode 7, r=PC)        |
  194. |---------------------+----------------------------------------|
  195. | Rn                  |General purpose Register (16-bit, n=0-5)|
  196. | SP                  |Stack Pointer (16-bit, R6)              |
  197. | PC                  |Program Counter (16-bit, R7)            |
  198. | PS                  |Processor Status (16-bit)               |
  199. |---------------------+----------------------------------------|
  200. | a                   |Relative address                        |
  201. | b                   |Blank or B for word or byte operand(s)  |
  202. | d                   |Destination                             |
  203. | n                   |Register Number (0 to 5)                |
  204. | nn                  |16-bit expression (0 to 65535)          |
  205. | r                   |Register (Rn,SP,PC)                     |
  206. | s                   |Source                                  |
  207. | t                   |Trap number                             |
  208. | +                   |Arithmetic addition                     |
  209. | -                   |Arithmetic subtraction                  |
  210. | *                   |Arithmetic multipication                |
  211. | /                   |Arithmetic division                     |
  212. | ^                   |Arithmetic exponent                     |
  213. | &                   |Logical AND                             |
  214. | ~                   |Logical NOT                             |
  215. | v                   |Logical inclusive OR                    |
  216. | x                   |Logical exclusive OR                    |
  217. | <-                  |Rotate left                             |
  218. | ->                  |Rotate right                            |
  219. | { }                 |Combination of operands                 |
  220. |---------------------+----------------------------------------|
  221. | DEC                 |Digital Equipment Corporation           |
  222. | EIS                 |Extended fixed point Instruction Set    |
  223. | FIS                 |Floating point Instruction Set          |
  224. | LSI                 |Large Scale Integration                 |
  225. | PSW                 |Processor Status Word                   |
  226. |---------------------+----------------------------------------|
  227. | 000                 |Reserved vector                         |
  228. | 004                 |Time-out/system error vector            |
  229. | 010                 |Illegal and reserved instruction vector |
  230. | 014                 |BPT instruction vector                  |
  231. | 020                 |IOT instruction vector                  |
  232. | 024                 |Power fail vector                       |
  233. | 030                 |EMT instruction vector                  |
  234. | 034                 |TRAP instruction vector                 |
  235. | 060                 |Console input device vector             |
  236. | 064                 |Console output device vector            |
  237. | 100                 |External event line interrupt vector    |
  238. | 244                 |FIS vector (optional)                   |
  239. | 160000-177776       |Device addresses                        |
  240. ----------------------------------------------------------------
  241.