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  1. ----------------------------------------------------------------
  2. |                                                              |
  3. |                                                              |
  4. |                            Intel                             |
  5. |                                                              |
  6. |        88888      000      88888      000        A           |
  7. |       8     8    0   0    8     8    0   0      A A          |
  8. |       8     8   0   0 0   8     8   0   0 0    A   A         |
  9. |        88888    0  0  0    88888    0  0  0   AAAAAAA        |
  10. |       8     8   0 0   0   8     8   0 0   0   A     A        |
  11. |       8     8    0   0    8     8    0   0    A     A        |
  12. |        88888      000      88888      000     A     A        |
  13. |                                                              |
  14. |         8080A MICROPROCESSOR Instruction Set Summary         |
  15. |                                                              |
  16. |                                                              |
  17. |                                                              |
  18. |                                                              |
  19. |                                                              |
  20. |                    _________    _________                    |
  21. |                  _|         \__/         |_                  |
  22. |         <-- A10 |_|1                   40|_| A11 -->         |
  23. |                  _|                      |_                  |
  24. |             Vss |_|2                   39|_| A14 -->         |
  25. |                  _|                      |_                  |
  26. |         <--> D4 |_|3                   38|_| A13 -->         |
  27. |                  _|                      |_                  |
  28. |         <--> D5 |_|4                   37|_| A12 -->         |
  29. |                  _|                      |_                  |
  30. |         <--> D6 |_|5                   36|_| A15 -->         |
  31. |                  _|                      |_                  |
  32. |         <--> D7 |_|6                   35|_| A9 -->          |
  33. |                  _|                      |_                  |
  34. |         <--> D3 |_|7                   34|_| A8 -->          |
  35. |                  _|                      |_                  |
  36. |         <--> D2 |_|8                   33|_| A7 -->          |
  37. |                  _|                      |_                  |
  38. |         <--> D1 |_|9                   32|_| A6 -->          |
  39. |                  _|                      |_                  |
  40. |         <--> D0 |_|10      8080A       31|_| A5 -->          |
  41. |                  _|                      |_                  |
  42. |             Vbb |_|11                  30|_| A4 -->          |
  43. |                  _|                      |_                  |
  44. |       --> RESET |_|12                  29|_| A3 -->          |
  45. |                  _|                      |_                  |
  46. |        --> HOLD |_|13                  28|_| Vdd             |
  47. |                  _|                      |_                  |
  48. |         --> INT |_|14                  27|_| A2 -->          |
  49. |                  _|                      |_                  |
  50. |        --> CLK2 |_|15                  26|_| A1 -->          |
  51. |                  _|                      |_                  |
  52. |        <-- INTE |_|16                  25|_| A0 -->          |
  53. |                  _|                      |_                  |
  54. |        <-- DBIN |_|17                  24|_| WAIT -->        |
  55. |              __  _|                      |_                  |
  56. |          <-- WR |_|18                  23|_| READY <--       |
  57. |                  _|                      |_                  |
  58. |        <-- SYNC |_|19                  22|_| CLK1 <--        |
  59. |                  _|                      |_                  |
  60. |             Vcc |_|20                  21|_| HLDA -->        |
  61. |                   |______________________|                   |
  62. |                                                              |
  63. |                                                              |
  64. |                                                              |
  65. |                                                              |
  66. |                                                              |
  67. |                                                              |
  68. |Written by     Jonathan Bowen                                 |
  69. |               Programming Research Group                     |
  70. |               Oxford University Computing Laboratory         |
  71. |               8-11 Keble Road                                |
  72. |               Oxford OX1 3QD                                 |
  73. |               England                                        |
  74. |                                                              |
  75. |               Tel +44-865-273840                             |
  76. |                                                              |
  77. |Created        May 1983                                       |
  78. |Updated        April 1985                                     |
  79. |Issue          1.1                Copyright (C) J.P.Bowen 1985|
  80. ----------------------------------------------------------------
  81. ----------------------------------------------------------------
  82. |Mnemonic |Op|SZAPC|~s|Description               |Notes        |
  83. |---------+--+-----+--+--------------------------+-------------|
  84. |ACI n    |CE|*****| 7|Add with Carry Immediate  |A=A+n+CY     |
  85. |ADC r    |8F|*****| 4|Add with Carry            |A=A+r+CY(21X)|
  86. |ADC M    |8E|*****| 7|Add with Carry to Memory  |A=A+[HL]+CY  |
  87. |ADD r    |87|*****| 4|Add                       |A=A+r   (20X)|
  88. |ADD M    |86|*****| 7|Add to Memory             |A=A+[HL]     |
  89. |ADI n    |C6|*****| 7|Add Immediate             |A=A+n        |
  90. |ANA r    |A7|****0| 4|AND Accumulator           |A=A&r   (24X)|
  91. |ANA M    |A6|****0| 7|AND Accumulator and Memory|A=A&[HL]     |
  92. |ANI n    |E6|**0*0| 7|AND Immediate             |A=A&n        |
  93. |CALL a   |CD|-----|17|Call unconditional        |-[SP]=PC,PC=a|
  94. |CC a     |DC|-----|11|Call on Carry             |If CY=1(17~s)|
  95. |CM a     |FC|-----|11|Call on Minus             |If S=1 (17~s)|
  96. |CMA      |2F|-----| 4|Complement Accumulator    |A=~A         |
  97. |CMC      |3F|----*| 4|Complement Carry          |CY=~CY       |
  98. |CMP r    |BF|*****| 4|Compare                   |A-r     (27X)|
  99. |CMP M    |BF|*****| 7|Compare with Memory       |A-[HL]       |
  100. |CNC a    |D4|-----|11|Call on No Carry          |If CY=0(17~s)|
  101. |CNZ a    |C4|-----|11|Call on No Zero           |If Z=0 (17~s)|
  102. |CP a     |F4|-----|11|Call on Plus              |If S=0 (17~s)|
  103. |CPE a    |EC|-----|11|Call on Parity Even       |If P=1 (17~s)|
  104. |CPI n    |FE|*****| 7|Compare Immediate         |A-n          |
  105. |CPO a    |E4|-----|11|Call on Parity Odd        |If P=0 (17~s)|
  106. |CZ a     |CC|-----|11|Call on Zero              |If Z=1 (17~s)|
  107. |DAA      |27|*****| 4|Decimal Adjust Accumulator|A=BCD format |
  108. |DAD B    |09|----*|10|Double Add BC to HL       |HL=HL+BC     |
  109. |DAD D    |19|----*|10|Double Add DE to HL       |HL=HL+DE     |
  110. |DAD H    |29|----*|10|Double Add HL to HL       |HL=HL+HL     |
  111. |DAD SP   |39|----*|10|Double Add SP to HL       |HL=HL+SP     |
  112. |DCR r    |3D|****-| 5|Decrement                 |r=r-1   (0X5)|
  113. |DCR M    |35|****-|10|Decrement Memory          |[HL]=[HL]-1  |
  114. |DCX B    |0B|-----| 5|Decrement BC              |BC=BC-1      |
  115. |DCX D    |1B|-----| 5|Decrement DE              |DE=DE-1      |
  116. |DCX H    |2B|-----| 5|Decrement HL              |HL=HL-1      |
  117. |DCX SP   |3B|-----| 5|Decrement Stack Pointer   |SP=SP-1      |
  118. |DI       |F3|-----| 4|Disable Interrupts        |             |
  119. |EI       |FB|-----| 4|Enable Interrupts         |             |
  120. |HLT      |76|-----| 7|Halt                      |             |
  121. |IN p     |DB|-----|10|Input                     |A=[p]        |
  122. |INR r    |3C|****-| 5|Increment                 |r=r+1   (0X4)|
  123. |INR M    |3C|****-|10|Increment Memory          |[HL]=[HL]+1  |
  124. |INX B    |03|-----| 5|Increment BC              |BC=BC+1      |
  125. |INX D    |13|-----| 5|Increment DE              |DE=DE+1      |
  126. |INX H    |23|-----| 5|Increment HL              |HL=HL+1      |
  127. |INX SP   |33|-----| 5|Increment Stack Pointer   |SP=SP+1      |
  128. |JMP a    |C3|-----|10|Jump unconditional        |PC=a         |
  129. |JC a     |DA|-----|10|Jump on Carry             |If CY=1(10~s)|
  130. |JM a     |FA|-----|10|Jump on Minus             |If S=1 (10~s)|
  131. |JNC a    |D2|-----|10|Jump on No Carry          |If CY=0(10~s)|
  132. |JNZ a    |C2|-----|10|Jump on No Zero           |If Z=0 (10~s)|
  133. |JP a     |F2|-----|10|Jump on Plus              |If S=0 (10~s)|
  134. |JPE a    |EA|-----|10|Jump on Parity Even       |If P=1 (10~s)|
  135. |JPO a    |E2|-----|10|Jump on Parity Odd        |If P=0 (10~s)|
  136. |JZ a     |CA|-----|10|Jump on Zero              |If Z=1 (10~s)|
  137. |LDA a    |3A|-----|13|Load Accumulator direct   |A=[a]        |
  138. |LDAX B   |0A|-----| 7|Load Accumulator indirect |A=[BC]       |
  139. |LDAX D   |1A|-----| 7|Load Accumulator indirect |A=[DE]       |
  140. |LHLD a   |2A|-----|16|Load HL Direct            |HL=[a]       |
  141. |LXI B,nn |01|-----|10|Load Immediate BC         |BC=nn        |
  142. |LXI D,nn |11|-----|10|Load Immediate DE         |DE=nn        |
  143. |LXI H,nn |21|-----|10|Load Immediate HL         |HL=nn        |
  144. |LXI SP,nn|31|-----|10|Load Immediate Stack Ptr  |SP=nn        |
  145. |MOV r1,r2|7F|-----| 5|Move register to register |r1=r2   (1XX)|
  146. |MOV M,r  |77|-----| 7|Move register to Memory   |[HL]=r  (16X)|
  147. |MOV r,M  |7E|-----| 7|Move Memory to register   |r=[HL]  (1X6)|
  148. |MVI r,n  |3E|-----| 7|Move Immediate            |r=n     (0X6)|
  149. |MVI M,n  |36|-----|10|Move Immediate to Memory  |[HL]=n       |
  150. |NOP      |00|-----| 4|No Operation              |             |
  151. |ORA r    |B7|**0*0| 4|Inclusive OR Accumulator  |A=Avr   (26X)|
  152. |ORA M    |B6|**0*0| 7|Inclusive OR Accumulator  |A=Av[HL]     |
  153. |ORI n    |F6|**0*0| 7|Inclusive OR Immediate    |A=Avn        |
  154. |OUT p    |D3|-----|10|Output                    |[p]=A        |
  155. |PCHL     |E9|-----| 5|Jump HL indirect          |PC=[HL]      |
  156. |POP B    |C1|-----|10|Pop BC                    |BC=[SP]+     |
  157. |POP D    |D1|-----|10|Pop DE                    |DE=[SP]+     |
  158. |POP H    |E1|-----|10|Pop HL                    |HL=[SP]+     |
  159. |POP PSW  |F1|-----|10|Pop Processor Status Word |{PSW,A}=[SP]+|
  160. ----------------------------------------------------------------
  161. ----------------------------------------------------------------
  162. |Mnemonic |Op|SZAPC|~s|Description               |Notes        |
  163. |---------+--+-----+--+--------------------------+-------------|
  164. |PUSH B   |C5|-----|11|Push BC                   |-[SP]=BC     |
  165. |PUSH D   |D5|-----|11|Push DE                   |-[SP]=DE     |
  166. |PUSH H   |E5|-----|11|Push HL                   |-[SP]=HL     |
  167. |PUSH PSW |F5|-----|11|Push Processor Status Word|-[SP]={PSW,A}|
  168. |RAL      |17|----*| 4|Rotate Accumulator Left   |A={CY,A}<-   |
  169. |RAR      |1F|----*| 4|Rotate Accumulator Righ   |A=->{CY,A}   |
  170. |RET      |C9|-----|10|Return                    |PC=[SP]+     |
  171. |RC       |D8|-----| 5|Return on Carry           |If CY=1(11~s)|
  172. |RM       |F8|-----| 5|Return on Minus           |If S=1 (11~s)|
  173. |RNC      |D0|-----| 5|Return on No Carry        |If CY=0(11~s)|
  174. |RNZ      |C0|-----| 5|Return on No Zero         |If Z=0 (11~s)|
  175. |RP       |F0|-----| 5|Return on Plus            |If S=0 (11~s)|
  176. |RPE      |E8|-----| 5|Return on Parity Even     |If P=1 (11~s)|
  177. |RPO      |E0|-----| 5|Return on Parity Odd      |If P=0 (11~s)|
  178. |RZ       |C8|-----| 5|Return on Zero            |If Z=1 (11~s)|
  179. |RLC      |07|----*| 4|Rotate Left Circular      |A=A<-        |
  180. |RRC      |0F|----*| 4|Rotate Right Circular     |A=->A        |
  181. |RST z    |C7|-----|11|Restart              (3X7)|-[SP]=PC,PC=z|
  182. |SBB r    |9F|*****| 4|Subtract with Borrow      |A=A-r-CY(23X)|
  183. |SBB M    |9E|*****| 7|Subtract with Borrow      |A=A-[HL]-CY  |
  184. |SBI n    |DE|*****| 7|Subtract with Borrow Immed|A=A-n-CY     |
  185. |SHLD a   |22|-----|16|Store HL Direct           |[a]=HL       |
  186. |SPHL     |F9|-----| 5|Move HL to SP             |SP=HL        |
  187. |STA a    |32|-----|13|Store Accumulator         |[a]=A        |
  188. |STAX B   |02|-----| 7|Store Accumulator indirect|[BC]=A       |
  189. |STAX D   |12|-----| 7|Store Accumulator indirect|[DE]=A       |
  190. |STC      |37|----1| 4|Set Carry                 |CY=1         |
  191. |SUB r    |97|*****| 4|Subtract                  |A=A-r   (22X)|
  192. |SUB M    |96|*****| 7|Subtract Memory           |A=A-[HL]     |
  193. |SUI n    |D6|*****| 7|Subtract Immediate        |A=A-n        |
  194. |XCHG     |EB|-----| 4|Exchange HL with DE       |HL<->DE      |
  195. |XRA r    |AF|**0*0| 4|Exclusive OR Accumulator  |A=Axr   (25X)|
  196. |XRA M    |AE|**0*0| 7|Exclusive OR Accumulator  |A=Ax[HL]     |
  197. |XRI n    |EE|**0*0| 7|Exclusive OR Immediate    |A=Axn        |
  198. |XTHL     |E3|-----|18|Exchange stack Top with HL|[SP]<->HL    |
  199. |------------+-----+--+----------------------------------------|
  200. | PSW        |-*01 |  |Flag unaffected/affected/reset/set      |
  201. | S          |S    |  |Sign (Bit 7)                            |
  202. | Z          | Z   |  |Zero (Bit 6)                            |
  203. | AC         |  A  |  |Auxilary Carry (Bit 4)                  |
  204. | P          |   P |  |Parity (Bit 2)                          |
  205. | CY         |    C|  |Carry (Bit 0)                           |
  206. |---------------------+----------------------------------------|
  207. | a p                 |Direct addressing                       |
  208. | M z                 |Register indirect addressing            |
  209. | n nn                |Immediate addressing                    |
  210. | r                   |Register addressing                     |
  211. |---------------------+----------------------------------------|
  212. |DB n(,n)             |Define Byte(s)                          |
  213. |DB 'string'          |Define Byte ASCII character string      |
  214. |DS nn                |Define Storage Block                    |
  215. |DW nn(,nn)           |Define Word(s)                          |
  216. |---------------------+----------------------------------------|
  217. | A B C D E H L       |Registers (8-bit)                       |
  218. | BC DE HL            |Register pairs (16-bit)                 |
  219. | PC                  |Program Counter register (16-bit)       |
  220. | PSW                 |Processor Status Word (8-bit)           |
  221. | SP                  |Stack Pointer register (16-bit)         |
  222. |---------------------+----------------------------------------|
  223. | a                   |16-bit address quantity (0 to 65535)    |
  224. | n                   |8-bit data quantity (0 to 255)          |
  225. | nn                  |16-bit data quantity (0 to 65535)       |
  226. | p                   |8-bit I/O port number (0 to 255)        |
  227. | r                   |Register (X=B,C,D,E,H,L,M,A)            |
  228. | z                   |Vector (X=0H,8H,10H,18H,20H,28H,30H,38H)|
  229. |---------------------+----------------------------------------|
  230. | +  -                |Arithmetic addition/subtraction         |
  231. | &  ~                |Logical AND/NOT                         |
  232. | v  x                |Logical inclusive/exclusive OR          |
  233. | <-  ->              |Rotate left/right                       |
  234. | <->                 |Exchange                                |
  235. | [ ]                 |Indirect addressing                     |
  236. | [ ]+  -[ ]          |Indirect addr. auto-increment/decrement |
  237. | { }                 |Combination of operands                 |
  238. | ( X )               |Octal op code where X is a 3-bit code   |
  239. | If ( ~s)            |Number of cycles if condition true      |
  240. ----------------------------------------------------------------
  241.