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  1. ----------------------------------------------------------------
  2. |                                                              |
  3. |                                                              |
  4. |                            Intel                             |
  5. |                                                              |
  6. |             88888      000         4     X     X             |
  7. |            8     8    0   0       44      X   X              |
  8. |            8     8   0   0 0     4 4       X X               |
  9. |             88888    0  0  0    4  4        X                |
  10. |            8     8   0 0   0   4444444     X X               |
  11. |            8     8    0   0        4      X   X              |
  12. |             88888      000         4     X     X             |
  13. |                                                              |
  14. |                  8048 MICROCOMPUTER family                   |
  15. |                   Instruction Set Summary                    |
  16. |                                                              |
  17. |                                                              |
  18. |                                                              |
  19. |                                                              |
  20. |                                                              |
  21. |                                                              |
  22. |                                                              |
  23. |                                                              |
  24. |                                                              |
  25. |                                                              |
  26. | XXXXX                      XXXXX                       XXXXX |
  27. | XXXXX                      XXXXX                       XXXXX |
  28. |                            XXXXX                       XXXXX |
  29. | XXXXX XXXXX  XXXXXXXX      XXXXX                       XXXXX |
  30. | XXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXX                    XXXXX |
  31. | XXXXX XXXXXX       XXXXXX  XXXXX                       XXXXX |
  32. | XXXXX XXXXX         XXXXX  XXXXX                       XXXXX |
  33. | XXXXX XXXXX         XXXXX  XXXXX          XXXXX        XXXXX |
  34. | XXXXX XXXXX         XXXXX  XXXXX      XXXXXXXXXXXXX    XXXXX |
  35. | XXXXX XXXXX         XXXXX  XXXXX    XXXXXX     XXXXXX  XXXXX |
  36. | XXXXX XXXXX         XXXXX  XXXXX   XXXXX         XXXXX XXXXX |
  37. | XXXXX XXXXX         XXXXX  XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX   |
  38. | XXXXX XXXXX         XXXXX    XXXXXXXXX                       |
  39. |                                    XXXXX                     |
  40. |                                     XXXXXX     XXXXXX        |
  41. |                                       XXXXXXXXXXXXX          |
  42. |                                           XXXXX              |
  43. |                                                              |
  44. |                                                              |
  45. |                                                              |
  46. |                                                              |
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  48. |                                                              |
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  60. |                                                              |
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  62. |                                                              |
  63. |                                                              |
  64. |                                                              |
  65. |                                                              |
  66. |                                                              |
  67. |                                                              |
  68. |Written by     Jonathan Bowen                                 |
  69. |               Programming Research Group                     |
  70. |               Oxford University Computing Laboratory         |
  71. |               8-11 Keble Road                                |
  72. |               Oxford OX1 3QD                                 |
  73. |               England                                        |
  74. |                                                              |
  75. |               Tel +44-865-273840                             |
  76. |                                                              |
  77. |Created        May 1983                                       |
  78. |Updated        April 1985                                     |
  79. |Issue          1.1                Copyright (C) J.P.Bowen 1985|
  80. ----------------------------------------------------------------
  81. ----------------------------------------------------------------
  82. |Mnemonic  |Op|CA|F|~|Description              |Notes          |
  83. |----------+--+--+-+-+-------------------------+---------------|
  84. |ADD  A,rr |68|**|A|1|Add register             |A=A+rr         |
  85. |ADD  A,@r |60|**|B|1|Add memory               |A=A+[r]        |
  86. |ADD  A,#n |03|**|C|2|Add immediate            |A=A+n          |
  87. |ADDC A,rr |X8|**|A|1|Add with Carry register  |A=A+rr+C       |
  88. |ADDC A,@r |X0|**|B|1|Add with Carry memory    |A=A+[r]+C      |
  89. |ADDC A,#n |13|**|C|2|Add with Carry immediate |A=A+n+C        |
  90. |ANL  A,rr |58|--|A|1|AND Logical register     |A=A&rr         |
  91. |ANL  A,@r |50|--|B|1|AND Logical memory       |A=A&[r]        |
  92. |ANL  A,#n |53|--|C|2|AND Logical Immediate    |A=A&n          |
  93. |ANL  pp,#n|98|--|D|2|AND Logical I/O port     |pp=pp&n        |
  94. |ANLD ep,A |9C|--|E|2|AND Logical expander port|ep=ep&A        |
  95. |CALL a    |14|--|F|2|Call subroutine          |[SP]+={PSW,PC},|
  96. |CLR  A    |2X|--|G|1|Clear accumulator        |A=0        PC=a|
  97. |CLR  C    |9X|0-|G|1|Clear carry status       |C=0            |
  98. |CLR  F0   |85|--|G|1|Clear flag #0            |F0=0           |
  99. |CLR  F1   |A5|--|G|1|Clear flag #1            |F1=0           |
  100. |CPL  A    |3X|--|G|1|Complement accumulator   |A=~A           |
  101. |CPL  C    |AX|*-|G|1|Complement carry status  |C=~C           |
  102. |CPL  F0   |95|--|G|1|Complement flag #0       |F0=~F0         |
  103. |CPL  F1   |B5|--|G|1|Complement flag #1       |F1=~F1         |
  104. |DA   A    |5X|--|G|1|Decimal Adjust acc.      |A=BCD{A}       |
  105. |DEC  A    |0X|--|G|1|Decrement accumulator    |A=A-1          |
  106. |DEC  rr   |C8|--|A|1|Decrement register       |rr=rr-1        |
  107. |DIS  I    |15|--|G|1|Disable external int.    |               |
  108. |DIS  TCNTI|35|--|G|1|Disable timer interrupt  |               |
  109. |DJNZ rr,l |E8|--|H|2|Dec. and Jump if Non-Zero|rr=rr-1,if rr  |
  110. |EN   I    |05|--|G|1|Enable external interrupt|               |
  111. |EN   TCNTI|25|--|G|1|Enable timer interrupt   |               |
  112. |ENT0 CLK  |X5|--|G|1|Enable timer output      |               |
  113. |IN   A,p  |08|--|I|2|Input from I/O port      |A=p            |
  114. |IN   A,DBB|22|--|G|1|Input from data bus      |A=BUS    (8041)|
  115. |INC  A    |1X|--|G|1|Increment accumulator    |A=A+1          |
  116. |INC  rr   |18|--|A|1|Increment register       |rr=rr+1        |
  117. |INC  @r   |10|--|B|1|Increment memory         |[r]=[r]+1      |
  118. |INS  A,BUS|08|--|G|2|Input bus with strobe    |A=BUS          |
  119. |JBn  l    |12|--|J|2|Jump if Bit set (n=0-X)  |If A<n>=1      |
  120. |JC   l    |F6|--|K|2|Jump if Carry set        |If C=1         |
  121. |JF0  l    |B6|--|K|2|Jump if Flag #0 set      |If F0=1        |
  122. |JF1  l    |X6|--|K|2|Jump if Flag #1 set      |If F1=1        |
  123. |JMP  a    |04|--|F|2|Unconditional Jump       |PC=a           |
  124. |JMPP @A   |B3|--|G|2|Jump on accumulator      |PC=PC<8:11>+A  |
  125. |JNC  l    |E6|--|K|2|Jump if Not Carry        |If C=0         |
  126. |JNI  l    |86|--|K|2|Jump if Not Interrupt    |If I=0         |
  127. |JNIBF l   |D6|--|K|2|Jump if Not IBF          |If IBF=0 (8041)|
  128. |JNT0 l    |26|--|K|2|Jump if Not Test i/p #0  |If T0=0        |
  129. |JNT1 l    |46|--|K|2|Jump if Not Test i/p #1  |If T1=0        |
  130. |JNZ  l    |96|--|K|2|Jump if Not Zero         |If A<>0        |
  131. |JOBF l    |86|--|K|2|Jump if OBF set          |If OBF=1       |
  132. |JTF  l    |16|--|K|2|Jump if Timer Flag set   |If TF=1, TF=0  |
  133. |JT0  l    |36|--|K|2|Jump if Test i/p #0 set  |If T0=1        |
  134. |JT1  l    |56|--|K|2|Jump if Test i/p #1 set  |If T1=1        |
  135. |JZ   l    |C6|--|K|2|Jump if Zero             |If A=0         |
  136. |MOV  A,#n |23|--|C|2|Move from immediate      |A=n            |
  137. |MOV  A,PSW|CX|--|G|1|Move from PSW            |A=PSW          |
  138. |MOV  A,rr |F8|--|A|1|Move from register       |A=rr           |
  139. |MOV  A,@r |F0|--|B|1|Move from memory         |A=[r]          |
  140. |MOV  A,T  |42|--|G|1|Move from timer          |A=T            |
  141. |MOV  PSW,A|DX|**|G|1|Move to PSW              |PSW=A          |
  142. |MOV  rr,A |A8|--|A|1|Move to register         |rr=A           |
  143. |MOV  rr,#n|B8|--|L|2|Move immediate to reg.   |rr=n           |
  144. |MOV  @r,A |A0|--|B|1|Move to memory           |[r]=A          |
  145. |MOV  @r,#n|B0|--|M|2|Move immediate to memory |[r]=n          |
  146. |MOV  T,A  |62|--|G|1|Move to timer            |T=A            |
  147. |MOVD A,ep |0C|--|E|2|Move from expander port  |A=ep           |
  148. |MOVD ep,A |3C|--|E|2|Move to expander port    |ep=A           |
  149. |MOVP A,@A |A3|--|G|1|2|Move from memory       |A=[PC<8:11>+A] |
  150. |MOVP3 A,@A|E3|--|G|2|Move from memory         |A=[300H+A]     |
  151. |MOVX A,@r |80|--|B|2|Move from external memory|A=[r]          |
  152. |MOVX @r,A |90|--|B|2|Move to external memory  |[r]=A          |
  153. |NOP       |00|--|G|1|No Operation             |               |
  154. |ORL  A,rr |48|--|A|1|OR Logical register      |A=Avrr         |
  155. |ORL  A,@r |40|--|B|1|OR Logical memory        |A=Av[r]        |
  156. |ORL  A,#n |43|--|C|2|OR Logical immediate     |A=Avn          |
  157. |ORL  pp,#n|88|--|D|2|OR Logical I/O port      |pp=ppvn        |
  158. |ORLD ep,A |8C|--|E|2|OR Logical expander port |ep=epvA        |
  159. |OUT  DBB,A|02|--|G|1|Output to bus            |BUS=A    (8041)|
  160. ----------------------------------------------------------------
  161. ----------------------------------------------------------------
  162. |Mnemonic  |Op|CA|F|~|Description              |Notes          |
  163. |----------+--+--+-+-+-------------------------+---------------|
  164. |OUTL BUS,A|02|--|G|2|Output to bus            |BUS=A          |
  165. |OUTL p,A  |38|--|I|2|Output to I/O port       |p=A            |
  166. |RAD       |80|--|G| |Read Analogue input      |A=A/D reg(8022)|
  167. |RET       |83|--|G|2|Return from subroutine   |PC=[SP]-       |
  168. |RET  I    |93|**|G|2|Return from Interrupt    |RETR     (8022)|
  169. |RETR      |93|**|G|2|Return and Restore status|{PC,PSW}=[SP]- |
  170. |RL   A    |EX|--|G|1|Rotate Left              |A={A}<-        |
  171. |RLC  A    |FX|*-|G|1|Rotate Left thru Carry   |A={A,C}<-      |
  172. |RR   A    |XX|--|G|1|Rotate Right             |A=->{A}        |
  173. |RRC  A    |6X|*-|G|1|Rotate Right thru Carry  |A=->{C,A}      |
  174. |SEL  ANk  |85|--|N|1|Select Analogue input    |         (8022)|
  175. |SEL  MBk  |E5|--|N|1|Select Memory Bank       |PC<11>=k       |
  176. |SEL  RBk  |C5|--|N|1|Select Register Bank     |Reg bank=k     |
  177. |STOP TCNT |65|--|G|1|Stop timer/counter       |               |
  178. |STRT CNT  |45|--|G|1|Start counter            |               |
  179. |STRT T    |55|--|G|1|Start timer              |               |
  180. |SWAP A    |4X|--|G|1|Swap accumulator nibbles |A<0:3><->A<4:X>|
  181. |XCH  A,rr |28|--|A|1|Exchange register        |A<->rr         |
  182. |XCH  A,@r |20|--|B|1|Exchange memory          |A<->[r]        |
  183. |XCHD A,@r |30|--|B|1|Exchange lower nibbles   |A<0:3><->[r<:>]|
  184. |XRL  A,rr |D8|--|A|1|Exclusive OR register    |A=Axrr         |
  185. |XRL  A,@r |D0|--|B|1|Exclusive OR memory      |A=Ax[r]        |
  186. |XRL  A,#n |D3|--|C|2|Exclusive OR immediate   |A=Axn          |
  187. |-------------+--+-+-+-----------------------------------------|
  188. | PSW         |-*| | |Flag unaffected/affected or zero (0)     |
  189. | C           |C | | |Carry (Bit X)                            |
  190. | AC          | A| | |Auxilary Carry (Bit 6)                   |
  191. | F0   F1     |  | | |Flags (F0, bit 5, F1 bit 4)              |
  192. | SP          |  | | |Stack Pointer (Bits 0-2)                 |
  193. |----------------+-+-+-----------------------------------------|
  194. | -----nnn       |A| |nnn = R0/R1/R2/R3/R4/R5/R6/RX (3 bits)   |
  195. | -------r       |B| |r   = R0/R1 (1 bit)                      |
  196. | -------- MM    |C| |MM  = 8 bits of immediate data           |
  197. | ------pp MM    |D| |pp  = BUS/P1/P2/? (2 bits)               |
  198. | ------ee       |E| |ee  = P4/P5/P6/PX (2 bits)               |
  199. | xxx----- XX    |F| |xxx = high-order 3 bits of memory address|
  200. | --------       |G| |XX  = low-order 8 bits of memory address |
  201. | -----nnn XX    |H| |nnn = as above                           |
  202. | ------qq       |I| |qq  = ?/P1/P2/? (2 bits)                 |
  203. | bbb----- XX    |J| |bbb = 3-bit bit number of accumulator    |
  204. | -------- XX    |K| |XX  = as above                           |
  205. | -----nnn MM    |L| |nnn = as above                           |
  206. | -------r MM    |M| |r   = as above                           |
  207. | ---k----       |N| |k   = 0/1 (1 bit)                        |
  208. |--------------------+-----------------------------------------|
  209. | A                  |Accumulator (8-bit)                      |
  210. | BUS                |Bus I/O port (8-bit)                     |
  211. | IBF  OBF           |Input/Output Buffer Full flags (1-bit)   |
  212. | P1   P2            |I/O Ports (8-bit)                        |
  213. | PC                 |Program Counter register (12-bit)        |
  214. | PORT               |I/O Port P1 and P2                       |
  215. | PSW                |Processor Status Word (8-bit)            |
  216. | Rn   Rn'           |Registers/alternative regs (8-bit, n=0-X)|
  217. | T0   T1            |Test inputs                              |
  218. |--------------------+-----------------------------------------|
  219. | a                  |11-bit address quantity (0 to 204X)      |
  220. | ep                 |8243 expander port P4, P5, P6 or PX      |
  221. | k                  |1-bit data quantity (0 or 1)             |
  222. | l                  |Low-order 8 bits of a memory address     |
  223. | n                  |8-bit data quantity (0 to 255)           |
  224. | p    pp            |I/O port P1 or P2 / BUS, PORT, P1 or P2  |
  225. | r    rr            |Register R0 or R1 / Rn (n=0-X)           |
  226. |--------------------+-----------------------------------------|
  227. | +    -             |Arithmetic addition/subtraction          |
  228. | &    ~             |Logical AND/NOT                          |
  229. | v    x             |Logical inclusive/exclusive OR           |
  230. | <-   ->            |Rotate left/right                        |
  231. | <->                |Exchange                                 |
  232. | < >  < : >         |Bit number/range                         |
  233. | [ ]  [ ]+  -[ ]    |Indirect address/auto-increment/decrement|
  234. | { }                |Combination of operands                  |
  235. |--------------------+-----------------------------------------|
  236. | 00H to 0XH         |General purpose registers R0-RX (8-bit)  |
  237. | 08H to 1XH         |Stack area S0-SX (16-bit)                |
  238. | 18H to 1FH         |Alternative registers R0'-RX' (8-bit)    |
  239. | 20H to 3FH         |General scratchpad memory area           |
  240. ----------------------------------------------------------------
  241.