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Graphics Interchange Format  |  1995-09-26  |  78.3 KB  |  339x561  |  8-bit (186 colors)
   ocr: Dual CPU Disk drives 1/0 CPU CPU LAN segment External External cache cache MPSA bus Dual Dual Dual (25MBps) CPU CPU CPU Main bus (100MBps) Memory External cache CPU Figure 4: NePRAMES mitiprocessing arcbitecture bas a Dierarchical processor and bus design. The bigh-speed bis operates at 100MBPS and is shbared by the main processing unit and muittiple MPSA buses theit operate at 25MBpS. Each MPSA bis bas up to ttuo 1/O or application processors. Allbough tbis arcbitecture appears to be different front the symmetric mttprocessor design in Figure 3. fis verg similar ifyou ignore tbe MPSA bis cont ...