ocr: 4-Mbit SRAM Core Processor Two independent: 2-Mbit banks, Timer Cache dual ported JTAG Addr Procossor Data Port Data VOPort Addr Testa Emulation and DAG1 DAG2 Program IT - - - - - a : de Sequencer * E XX PM. Address Bus; 24 External Port Address DM, Address Bus 32 - Bus - de a 1 - - & - Host MUX Multiprocassor Port and PM Data Bus 48 Intenace Bus Data Connect DM Data Bus 40 BUS MUX * TE 9 DMA Register IOP Control File Ragister 16x40 Seral Pors Muiplier Barrel Shifter ALU Mapper) (Memory 01 L LMKE 0.1-2,3.4.5 Ports - VO Processor Figure 1: ADSP-21060 block diagram.
