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rEMARK OF THE EDITOR OF THIS DOCUMENT: tHE DOCUMENT CONTAINS SOME SCHEMATICS. i USED THE ascii CHARACTERSET TO DRAW LINES ETC. sO THEY MAY LOOK WEIRD. i'M SORRY FOR ANY INCONVENIENCE. tHERE EXISTS ONE WITH THE ibm-CHARACTERSET AND IS AS SO ONLY (???) READABLE WITH A TEXT-EDITOR UNDER dos. iN THIS VERSION THE gREEK phi CHARACTER OF THE ibm-SET HAS BEEN REPLACED BY THE CAPITAL p. i TRIED TO LET THE DRAWINGS LOOK LIKE THE ORIGINALS BUT THAT WAS NOT ALWAYS POSSIBLE. iN ONE CASE THE SCHEMATIC WAS TOO COMPLEX SO i DRAW IT USING uLTIcAP AND MADE A gif-FILE OF THE RESULT. i FOUND SEVERAL ERRORS BUT DID NOT CORRECT THEM UNLESS THEY COULD LEAD TO SEVERE CONFUSION. rUUD bALTISSEN cREDITS: gER rOZEMA FOR LENDING ME HIS SCANNER. ============================================================================ mos microcomputers hardware manual ============================================================================ pUBLICATIONS nUMBER 6500-10a mcs6500 microcomputer family hardware manual january 1976 tHE INFORMATION IN THIS MANUAL HAS BEEN REVIEWED AND IS BELIEVED TO BE ENTIRELY RELIABLE. hOWEVER, NO RESPONSIBILITY IS ASSUMED FOR INACCURACIES. tHE MATERIAL IN THIS MANUAL IS FOR INFORMATIONAL PURPOSES ONLY AND IS SUBJECT TO CHANGE WITHOUT NOTICE. sECOND eDITION (c) mos technology, inc. 1976 "aLL rIGHTS rESERVED" mos technology, inc 9s0 rITTENHOUSE rOAD nORNSTOWN, pa 19401 rEVISION a ============================================================================ preface tHE mos tECHNOLOGY, iNC. mgs6500 mICROCOMPUTER sYSTEM OFFERING COMBINES THE BEST FEATURES OF SECOND GENERATION FAMILIES INTO A PRODUCT LINE THAT IS BOTH A PRICE AND PERFORMANCE LEADER. a GROWING ARRAY OF PRODUCTS AND A UNIQUE MICRO- PROCESSOR FAMILY PROVIDE THE CUSTOMER WITH ANSWERS TO THE COMPLEX DESIGN PROB- LEMS CONFRONTING TODAY'S PROGRAMTTTERS AND DESIGNERS. iNTEGRATED CIRCUIT FABRICATION TECHNIQUES HAVE MOVED MICROPROCESSORS TO THE FOREFRONT OF COMPLEX, SOPHISTICATED COMPONENTS. tHE mcs6500 FAMILY BENEFITS FROM AN ADVANCED BUT PROVEN PROCESS TECHNOLOGY; n-cHANNEL, sILICON gATE, AND dE- PLETION lOADS ARE THE KEY ELEMENTS PROVIDING THE HIGH PERFORMANCE CHARACTERIS- TICS OBTAINABLE IN THE SINGLE SUPPLY 5-VOLT SYSTEM USAGE OF THE mcs6500 FAMILY. tHE n-cHANNEL, sILICON gATE TECHNOLOGY IS ENHANCED BY USE OF dEPLETION lOADS WHICH PROVIDES GREATER SPEED, LOWER POWER AND SMALLER CHIP SIZE THAN PREVIOUS PROCESSING APPROACHES. iON iMPLEMENTATION TECHNIQUES ARE BASIC ELEMENTS IN PRO- VIDING CONTROL AND STABILITY OF ALL PROCESSING PARAMETERS NECESSARY TO ACHIEVE THE ELECTRICAL CHARACTERISTICS OF THE mcs6500 PRODUCT LINE. tHESE CHARACTER- ISTICS PROVIDE A PRICE/PERFORMANCE COMBINATION WHICH ESTABLISHES THE mcs6500 FAMILY AS THE PRODUCT OFFERING BEST MEETING THE ECONOMIC AND TECHNICAL DEMANDS OF TODAY'S SYSTEM DESIGNS. a WORD OF EXPLANATION IS IN ORDER REGARDING THE mcs6500 PRODUCT LINE, SINCE THE CONCEPT OF "mICROPROCESSOR fAMILY" IS INDEED UNIQUE TO THE INDUSTRY. iT IS HELPFUL TO UNDERSTAND THE BASIC PRODUCT STRUCTURE OF THE mcs6500 FAMILY. tHE mcs650x sERIES REPRESENTS THE mICROPROCESSOR fAMILY. wITHIN THIS FAMILY WILL EXIST A SERIES OF 8-BIT DEVICES OFFERING A WIDE RANGE OF OPTIONS AND CAPABILITIES FOR THE CUSTOMER. fOR THE SINGLE-APPLICATION CUSTOMER, A VARIED SELECTION OF DEVICES IS AT HIS DISPOSAL IN CHOOSING THE ONE THAT BEST MEETS HIS SPECIFIC NEEDS. tHE "mICROPROCESSOR fAMILY" CONCEPT HAS AN EVEN GREATER IMPACT -II- ============================================================================ TO THE USER WHO HAS A VARIETY OF APPLICATIONS, EACH OF WHICH CAN BEST BE SERVED BY A SPECIFIC MEMBER OF THE FAMILY. iT IS IMPORTANT TO THIS USER THAT ALL OF THE DIFFERENT MICROPROCESSORS HE SELECTS MAINTAIN COMPATIBILITY--BOTH HARDWARE (FROM THE STANDPOINT OF BUS AND ELECTRICAL SPECIFICATIONS) AND SOFTWARE. tHE mcs650x PRODUCT LINE IS THE FIRST MICROPROCESSOR FAMILY TO ACHIEVE SUCH A LEVEL OF COMPATIBILITY BECAUSE IT WAS INDEED CONCEPTUALIZED AS A TOTALLY SOFTWARE AND HARDWARE COMPATIBLE FAMILY OF MICROPROCESSORS OFFERING A RANGE OF PERFORMANCE OPTIONS FROM WHICH THE DESIGNER CAN SELECT. tHE mcs6501 AND mcs6502 ARE THE FIRST TWO 40-PIN MEMBERS OF THE mcs650x FAMILY, EACH OFFERING 65k BYTES OF ADDRESSABLE MEMORY. tHE mcs6503, mcs6504 AND mcs6505 ARE THE FIRST 28-PIN VERSIONS WITH VARIOUS OPTIONS OF ADDRESSING CAPABILITY AND CONTROL FUNCTIONS FROM WHICH TO CHOOSE. tHE mcs652x sERIES REPRESENTS pERIPHERAL iNPUT/oUTPUT DEVICES, THE FIRST BEING THE mcs652o WHICH IS A DIRECT REPLACEMENT FOR THE mOTOROLA mc682o pERIPH- ERAL iNTERFACE aDAPTER (pia). sUBSEQUENT MEMBERS OF THIS SERIES WILL INCLUDE DEVICES WITH EXPANDED i/o CAPABILITIES. tHE mcs653x sERIES REPRESENTS COMBINATIONAL DEVICES--THOSE CONSISTING OF VARIOUS TRADEOFFS IN ram, rom, i/o, AND tIMING. tHE FIRST OF THESE IS THE mcs6530 WHICH CONTAINS 1k BYTES OF rom, 64 BYTES OF ram, AN iNTERVAL tIMER AND 16 i/o LINES. sUBSEQUENT PRODUCTS IN THIS SERIES WILL PROVIDE THE CUSTOMER WITH DIFFERENT COMBINATIONS AND NEW IMPLEMENTATIONS OF i/o, tIMING AND mEMORY. tHE mcs654x sERIES REPRESENTS rEAD oNLY mEMORIES SPECIFICALLY TAILORED TO MEET THE NEEDS OF LARGE PROGRAM STORAGE REQUIRED IN MANY OF THE APPLICATIONS OF THE mcs6500 FAMILY OF PRODUCTS. tHE FIRST OF THESE WILL BE A 16k (2k X 8) rom, THE mcs6540. aLL OF THE mcs6500 PRODUCT LINES OUTLINED UTILIZE THE SAME FABRICATION TECHNIQUES AND MEET IDENTICAL ELECTRICAL SPECIFICATIONS. wITH THIS FAMILY OF COMPATIBLE PRODUCTS THE DESIGNER OF TODAY HAS AT HIS DISPOSAL THE ELEMENTS NECESSARY TO DEVELOP A SYSTEM CONFIGURED TO MEET THE MOST DEMANDING TASKS. cOMPLEMENTING THE mcs6500 FAMILY IS A SELECTION OF rANDOM aCCESS mEMORIES TOTALLY COMPATIBLE WITH THE MICROCOMPUTER FAMILY. tHE FIRST OF THESE WILL BE THE mc56102, A 2102 EQUIVALENT, AND THE nc56111, A 2111 EQUIVALENT. tO ALLOW FOR MINIMUM i/o COST AND MAXIMUM USER FLEXIBILITY, ALL OF THE mcs6500 PRODUCTS ARE COMPATIBLE WITH THE m6800 BUS STRUCTURE. -III- ============================================================================ blank -IV- ============================================================================ disappeared -V- ============================================================================ 1.4 tHE mICROPROCESSORS 30 1.4.1 tHE mcs6soL 30 1.4.1.1 iNTRODUCTION 30 1.4.1.2 tHE mcs6501 pINOUTS 32 1.4.1.2.1 vCC, vSS--sUPPLY lINES 32 1.4.1.2.2 aboo - ab15--aDDRESS bUS 32 1.4.1.2.3 dbo - db7--dATA bUS 34 1.4.1.2.4 r/w--rEAD/wRITE 36 1.4.1.2.5 dbe--dATA bUS eNABLE 36 1.4.1.2.6 vma--vALID mEMORY aDDRESS 36 1.4.1.2.7 ba--bUS aVAILABLE 37 1.4.1.2.8 rdy--rEADY 37 1.4.1.2.9 nmi--nON-mASKABLE iNTERRUPT 38 1.4.1.2.10 irq--iNTERRUPT rEQUEST 38 1.4.1.2.11 res--rESET 40 1.4.2 tHE mcs6502 41 1.4.2.1 pRODUCT cHARACTERISTICS 41 1.4.2.2 dEVICE tIMING--rEQUIREMENTS AND gENERATION . 41 1.4.2.3 sync sIGNAL 44 1.4.2.4 s.o--sET oVERFLOW 44 1.4.3 tHE mcs6503, mcs6504 AND mcs6505 47 1.5 pERIPHERAL iNTERFACE dEVICE--mcs6520 50 1.5.1 iNTRODUCTION 50 1.5.2 oRGANIZATION OF THE mcs6520 51 1.5.2.1 dATA iNPUT rEGISTER 54 1.5.2.2 cONTROL rEGISTERS (cra AND crb) 54 1.5.2.3 dATA dIRECTION rEGISTERS (ddra, ddrb) 55 1.5.2.4 pERIPHERAL oUTPUT rEGISTERS (ora, orb) 55 1.5.2.5 iNTERRUPT sTATUS cONTROL 55 1.5.2.6 pERIPHERAL iNTERFACE bUFFERS (a, b) AND dATA bUS bUFFERS (dbb) 55 1.5.3 iNTERFACE bETWEEN mcs6520 AND THE mcs650x fAMILY OF mICROPROCESSORS 56 1.5.3.1 dATA bUS (do-d7) 56 1.5.3.2 eNABLE (e) 56 1.5.3.3 rEAD/wRITE (r/w) 56 1.5.3.4 cHIP-sELECT lINES (csL, c52, c53) 56 1.5.3.5 rEGISTER-sELECT lINES (rs, rs1) 58 1.5.3.5.1 rEADING THE pERIPHERAL a i/o pORT 59 1.5.3.5.2 rEADING THE pERIPHERAL b i/o pORT 59 1.5.3.6 rESET (res) 63 1.5.3.7 iNTERRUPT rEQUEST lINE (irqa, irqb) 63 1.5.3.7.1 cONTROL OF irqa 63 1.5.3.7.2 cONTROL OF irqb 64 -VI- ============================================================================ 1.5.4 iNTERFACE bETWEEN mcs6520 AND pERIPHERAL dEVICES 64 1.5.4.1 pERIPHERAL i/o pORTS 64 1.5.4.1.1 pERIPHERAL a i/o pORT (pa0-pa7) 65 1.5.4.1.2 pERIPHERAL b i/o pORT (pb0-pb7) 65 1.5.4.2 iNTERRUPT iNPUT/pERIPHERAL cONTROL lINES (ca1, ca2, cb1, cb2) 66 1.5.4.2.1 pERIPHERAL a iNTERRUPT iNPUT/pERIPHERAL cONTROL lINES (cb1, cb2) 66 1.5.4.2.2 pERIPHERAL b iNTERRUPT iNPUT/pERIPHERAL cONTROL lINES (cb1, cb2) 67 1.5.5 sUMMARY OF mcs6520 oPERATION 67 1.5.5.1 cONTROL rEGISTER oPERATION 67 1.5.5.2 mcs6520 oPERATION IN mc6500 sYSTEMS 70 1.6 pERIPHERAL iNTERFACE/mEMORY dEVICE--mcs6530 71 1.6.1 iNTRODUCTION 71 1.6.2 pINOUT dESCRIPTION 71 1.6.2.1 rESET (res) 71 1.6.2.2 iNPUT cLOCK 73 1.6.2.3 rEAD/wRITE (r/w) 73 1.6.2.4 iNTERRUPT rEQUEST (irq) 73 1.6.2.5 dATA bUS (d-d7) 73 1.6.2.6 pERIPHERAL dATA pORTS 73 1.6.2.7 aDDRESS lINES (a0-a9) 74 1.6.3 iNTERNAL oRGANIZATION 74 1.6.3.1 rom--1k bYTE (8k bITS) 74 1.6.3.2 ram--64 bYTES (512 bITS) 76 1.6.3.3 iNTERNAL pERIPHERAL rEGISTERS 76 1.6.3.4 iNTERVAL tIMER 76 1.6.4 aDDRESSING 78 1.6.4.1 oNE-cHIP aDDRESSING 80 1.6.4.2 sEVEN-cHIP aDDRESSING 80 1.6.4.3 i/o rEGISTER--tIMER aDDRESSING 80 chapter 2 configuring the microcomputer system 2.1 tHE sYSTEM cONFIGURATION tASK 84 2.2 iNPUT/oUTPUT tECHNIQUES 85 2.2.1 tHE gENERAL pURPOSE iNPUT/oUTPUT (i/o) pORT 85 2.2.2 tHE sPECIAL pURPOSE pERIPHERAL iNTERFACE dEVICE 85 2.2.3 cONFIGURING THE gENERAL pURPOSE i/o pORT 87 2.2.3.1 aSSIGNMENT OF oUTPUTS 88 2.2.3.2 aSSIGNMENT OF iNPUTS 88 2.2.4 pOWER-oN cONSIDERATIONS 90 -VII- ============================================================================ 2.2.5 hANDSHAKING 94 2.2.5.1 hANDSHAKING ON dATA tRANSFERS FROM THE pROCESSOR 94 2.2.5.2 hANDSHAKING ON dATA tRANSFERS INTO THE pROCESSOR 95 2.3 cONFIGURING THE iNTERFACE bETWEEN THE mICROPROCESSOR AND THE sUPPORT cHIPS 99 2.3.1 aSSIGNMENT OF aDDRESSES IN THE mcs6500 sYSTEM 99 2.3.1.1 rom aDDRESS aSSIGNMENT 102 2.3.1.2 ram aDDRESS aSSIGNMENT 102 2.3.2 aDDITIONAL aDDRESS aSSIGNMENT tECHNIQUES 104 2.3.3 iNTERRUPTS 104 2.3.3.1 iNTERRUPT pRIORITIZING 106 2.3.3.2 eXAMPLE 1: sELECTING THE iNTERRUPT vECTOR 106 2.3.3.3 eXAMPLE 2: uSING THE pROCESSOR sOFTWARE pOWER 108 2.3.4 tHE aPPLICATION OF roy TO cONTROLLING THE mEM- ORY iNTERFACE 108 2.3.4.1 iNTERFACE sLOW promS 108 2.3.4.2 dIRECT mEMORY aDDRESS (dma) tECHNIQUES 112 2.3.4.3 cONTROL OF dYNAMIC ramS IN THE mcs6500 sYSTEM 113 2.3.5 hOLD-tIME cONTROL--mcs65o1 117 2.4 aDDITIONAL sYSTEM cONSIDERATIONS 119 2.4.1 pERIPHERAL iNTERFACE dEVICES 119 2.4.2 ram 119 2.4.3 rom 2.5 eVALUATING sYSTEM pERFORMANCE 121 chapter 3 bringing up the mcs6500 3.0 iNTRODUCTION TO mICROCOMPUTER tESTING 123 3.1 sTATIC tESTING 124 3.1.1 iNTRODUCTION 124 3.1.2 sINGLE cYCLE eXECUTION 124 3.1.3 sINGLE iNSTRUCTION eXECUTION 127 3.2 dYNAMIC tESTING 130 3.2.1 iNTRODUCTION 130 3.2.2 eXTERNALLY iNDUCED lOOPS 130 3.2.3 sOFTWARE lOOPS 132 -VIII- ============================================================================ 3.3sYSTEM dIAGNOSIS uSING hARDWARE pROGRAMMER aIDS 133 3.3.1 kim kEYBOARD iNPUT mONITOR 135 3.3.2 tim--tELETYPE iNPUT mONITOR 136 3.3.3 mdt--mICROCOMPUTER dEVELOPMENT tERMINAL 138 3.4 mICROPROCESSOR sTART-uP pROCEDURE 139 3.4.1 iNTRODUCTION 139 3.4.2 sYSTEM pOWER--sTEP 1 139 3.4.3 bASIC sYSTEM tIMING--sTEP 2 140 3.4.4 sYSTEM rESET--sTEP 3 140 3.4.4.1 sTATIC aNALYSIS OF sYSTEM dETAILS 144 3.4.4.2 dYNAMIC aNALYSIS OF sYSTEM dETAILS 145 3.4.4.2.1 aDDRESS bUS vERIFICATION 145 3.4.4.2.2 dATA bUS vERIFICATION 146 3.4.5 dETAILED cOMPONENT cBECK 148 appendix a a-1 -IX- ============================================================================ list of figures chapter 1 the mcs6500 microcomputer system 1.1 oRGANIZATION OF mICROCOMPUTER sYSTEM 5 1.2 aDDRESS bUS AND rELATION TO mEMORY fIELD 7 1.3 pORTION OF rEAD oNLY mEMORY mATRIX 9 1.4 pINOUT cOMPARISON: mos tECHNOLOGY mcs6501, mOTOROLA mc6800 13 1.5 cLOCK AND rEAD/wRITE tIMING tABLE (1 mhZ oPERATION) 17 1.6 tWO-pHASE cLOCK tIMING 18 1.7 tIMING FOR rEADING dATA FROM mEMORY OF pERIPHERALS 18 1.8 tIMING FOR wRITING dATA TO mEMORY OR pERIPHERALS 19 1.9 iNTERRUPT wIRE or'D hARDWARE cONFIGURATION FROM pERIPHERAL iNTERFACE dEVICES TO mICROPROCESSOR 24 1.10 sEQUENCE TO sERVICE irq 26 1.11 mcs650x iNTERNAL aRCHITECTURE 29 1.12 mcs6501 pINOUT dESIGNATIONS 33 1.13 mcs650x sYSTEM tIMING dIAGRAM 35 1.14 eXAMPLES OF iNTERRUPT rECOGNITION BY mcs650x 39 1.15 mcs6502 pINOUT dESIGNATION 42 1.16 mcs6502 tIME bASE gENERATION--cRYSTAL cONTROLLED 43 L.16A mcs6502 pARALLEL mODE cRYSTAL cONTROLLED oSCILLATOR 43 L.16B mcs6502 sERIES nODE cRYSTAL cONTROLLED oSCILLATOR 43 1.17 mcs6502 tIME bASE gENERATOR--rc nETWORK 43 1.18 mcs6502 sync sIGNAL 45 1.19 fUNCTIONAL fEATURES OF mcs6503, mcs6504, mcs6505 46 1.20 mcs6503, mcs6504, mcs6505 pINOUT dESIGNATIONS 48 1.21 mcs6503, mcs6504, mcs6505 tIME bASE gENERATION cRYSTAL cONTROLLED 49 1.22 mcs6503, mcs6504, mcs6505 tIME eASE gENERATION rc nETWORK 49 1.23 bASIC mcs6520 iNTERFACE dIAGRAM 50 1.24 mcs6520 pINOUT dESIGNATIONS pERIPHERAL iNTERFACE aDAPTOR. 52 1.25 mcs6520 iNTERNAL aRCHITECTURE 53 L.26A mICROPROCESSOR iNTERFACE tIMING--rEAD 57 L.26B mICROPROCESSOR iNTERFACE tIMING--wRITE 57 L.27A pERIPHERAL a iNTERFACE tIMING 60 L.27B pERIPHERAL b iNTERFACE tIMING 61 L.28A pERIPHERAL i/o pORT a bUFFER 62 1.28B pERIPHERAL i/o pORT b bUFFER 62 1.29 cONTROL rEGISTER bIT dESIGNATIONS 67 -X- ============================================================================ 1.30 cONTROL OF iNTERRUPT iNPUTS caL, cbL 68 L.31A cONTROL OF ca2 (cb2) AS iNTERRUPT iNPUTS (bIT 5 = "0") 68 L.31B cONTROL OF ca2 oUTPUT mODES 69 L.31C cONTROL OF cb2 oUTPUT mODES 69 1.32 mcs6530 pINOUT dESIGNATION 72 1.33 mcs6530 iNTERNAL aRCHITECTURE 75 1.34 bASIC eLEMENTS OF iNTERVAL tIMER 77 1.35 eXAMPLE OF iNTERRUPT gENERATED BY iNTERVAL tIMER 79 1.36 mcs6530 oNE-cHIP aDDRESS eNCODING dIAGRAM 81 1.37 mcs6530 sEVEN-cHIP aDDRESSING sCHEME 82 1.38 aDDRESSING dECODE FOR i/o rEGISTER AND tIMER 83 chapter 2 configuring the microcomputer system 2.1 cONTROL OF lOW oRDER bIT OF mcs6520 oUTPUT rEGISTER 89 2.2 mcs6520 cONTROL OF tRANSISTOR dRIVEN sOLENOIDS 91 2.3A mcs6520 cONTROL OF pnp tRANSISTOR dRIVING sOLENOID cOIL . 93 2.3B mcs6520 cONTROLLING bOTH pOWER AND dRIVERS OF sOLENOID cELL 93 2.4 mcs6520 dRIVING ttl bUFFERS 93 2.5 mcs6520 cONTROLLING sOLENOIDS WITH eNABLE sIGNAL AND ttl iNTERFACE 94 2.6 wRITE hANDSHAKE sEQUENCE 97 2.7 rEAD hANDSHAKE sEQUENCE 98 2.8 oRGANIZATION OF mICROCOMPUTER sYSTEM 100 2.9 eXAMPLE OF "and" fUNCTION uSING hIGH oRDER aDDRESS lINES 101 2.10 tYPICAL aDDRESS aSSIGNMENTS 103 2.11 pAGE zERO cHIP-sELECT aDDRESSING sCHEME 105 2.12 sELECTING THE iNTERRUPT vECTOR 107 2.13 uSING mcs6520 FOR jUMP iNDIRECT iNTERRUPT rOUTINES 109 2.14A pRIORITY eNCODER cONNECTED TO lOW oRDER bITS OF mcs6520 . 110 2.14B pRIORITY eNCODER TO pERIPHERAL iNTERFACE sCHEME 111 2.15 sOFTWARE pROGRAM TO iMPLEMENT iNTERRUPT FROM ABOVE hARDWARE cONFIGURATION 111 2.16 iNTERFACING sCHEME FOR sLOW promS 114 2.17 lOGIC uSED TO gENERATE bUS aVAILABLE sIGNAL FOR dma aPPLICATIONS 114 2.18 cONTROL lOGIC FOR rEFRESH sIGNAL FOR dYNAMIC ramS 116 2.19 tIMING aNALYSIS OF dATA hOLD tIME 118 -XI- ============================================================================ chapter 3 bringing up the mcs6500 3.1 sUGGESTED sTATIC tEST cONTROL lOGIC 125 3.2 sINGLE cYCLE tIMING 126 3.3 mICROPROCESSOR sINGLE cYCLE dATA tRAP 128 3.4 sINGLE iNSTRUCTION eXECUTION 129 3.5 sUGGESTED cONFIGURATION FOR dYNAMIC rESET tESTING 131 3.6 mcs6501 cLOCK tIMING sIGNALS 141 3.6A iMPROPER cLOCKS 141 3.6B pROPER cLOCKS 141 3.7 aDDRESS lINES IN mcs650x sYSTEMS 142 3.7A pROPER aDDRESS lINES 142 3.7B eXCESS aDDRESS lINE lOADING 142 3.8 tHE dATA bUS IN mcs650x sYSTEMS 143 -XII- ============================================================================ chapter 1 the mcs6500 microcomputer system tHE PAST SEVERAL YEARS HAVE SEEN THE DEVELOPMENT OF AN EXCITING NEW CONCEPT IN ELECTRICAL DESIGN. cONVENTIONAL SYSTEM DESIGN IS RAPIDLY BEING REVOLUTION- IZED BY THE LARGE-SCALE, SINGLE-CHIP PROGRAMMABLE MICROPROCESSOR. tHE MICRO- COMPUTER STARTED OUT AS A RELATIVELY SIMPLE, DIFFICULT-TO-USE PROGRAMMABLE DEVICE CAPABLE OF HANDLING SIMPLE CONTROL OR COMPUTATIONAL PROBLEMS. hOWEVER, IT HAS SINCE MATURED INTO A POWERFUL, INEXPENSIVE, EASY-TO-USE DEVICE CAPABLE OF CONTROLLING ALL BUT THE MOST COMPLEX OF SYSTEMS. tHREE PRIMARY ATTRIBUTES OF MICROPROCESSOR-BASED SYSTEMS ARE BRINGING ABOUT THIS REVOLUTION. tHEY ARE: 1. mICROPROCESSORS ALLOW A SIGNIFICANT REDUCTION IN OVERALL SYSTEMS COST FOR PRODUCTS CURRENTLY IN PRODUCTION. rE-DESIGNING THEIR PRODUCTS AROUND THE MICROPROCESSOR IS PERMITTING MANY MANUFACTURERS TO DEVELOP OR MAINTAIN A PRICE ADVANTAGE OVER COMPETITORS. 2. tHE REDUCTION IN COST OF MICROCOMPUTER SYSTEMS IS OPENING UP VAST NEW MARKETS FOR MICROPROCESSORS. a GREAT NUMBER OF SYSTEMS WHICH WERE SIMPLY IMPOSSIBLE OR WERE AT BEST IMPRACTICAL, ARE BEING DESIGNED AND MARKETED TODAY USING THE MODERN, LOW-COST MICROPROCESSORS. 3. aT THE SAME TIME THE PRICE OF MICROPROCESSORS IS DROPPING, THE CAP- ABILITY IS RAPIDLY EXPANDING. tHIS ALSO ALLOWS THEM TO BE DESIGNED INTO MORE SYSTEMS THAN EVER BEFORE. aNYONE CONTEMPLATING A NEW DESIGN OR TRYING TO REDUCE COST IN AN EXISTING DESIGN MUST ASK HIMSELF IF A MICROPROCESSOR WILL SOLVE HIS PROBLEM. tHE SUCCESS OF THE MICROPROCESSOR IS BASED ON THE FACT THAT IT ALLOWS THE DESIGN ENGINEER AND PROGRAMMER TO APPLY THEIR EXPERTISE IN SOLVING A MULTITUDE OF DESIGN PROBLEMS USING COST EFFECTIVE icS. a SMALL NUMBER OF LARGE INTE- GRATED CIRCUITS CAN BE CONFIGURED TO SOLVE DESIGN PROBLEMS FROM THE SIMPLEST TO THE MOST COMPLEX. -1- ============================================================================ iF THE SAME INTEGRATED CIRCUITS ARE USED TO SOLVE A MULTITUDE OF UNIQUE DESIGNS, THE FIRST QUESTION ONE MUST ASK IS, "wHAT MAKES THEM UNIQUE?" tHE ANSWER IS: pROGRAMMING. aLTHOUGH MANY DIFFERENT DESIGNS MAY SHARE COMMON HARD- WARE, EACH HAS ITS OWN UNIQUE PROGRAM. tHIS BRINGS US TO ANOTHER VERY IMPORTANT CHARACTERISTIC OF MICROCOMPUTERS. tHE INTEGRATED CIRCUIT WHICH MAKES EACH SYS- TEM UNIQUE IS THE "rEAD-oNLY mEMORY" (rom) WHICH STORES THE SYSTEM PROGRAM. iT IS RELATIVELY EASY FOR THE INTEGRATED CIRCUIT MANUFACTURER TO ESTABLISH THE PARTICULAR PATTERN WHICH UNIQUELY DEFINES THE DATA IN A rom. aS A RESULT, THE TYPICAL CHARGE FOR "DESIGNING" A rom IS GENERALLY LESS THAN 10% OF THE COST OF DESIGNING A TOTALLY CUSTOM LOGIC CHIP. fURTHER, THE USER BENEFITS FROM HIGH VOLUME STANDARD PRODUCT WHICH IS STILL UNIQUE FOR HIS OWN APPLICATION DUE TO THE "CUSTOMIZATION" OF ONE ELEMENT OF HIS SYSTEM. -2- ============================================================================ 1.0 designing with microcomputer systems iT WILL PROBABLY SURPRISE MANY DESIGNERS WHO ARE APPROACHING THE SUBJECT OF MICROCOMPUTER DESIGN FOR THE FIRST TIME WHEN THEY DISCOVER THAT DESIGNING A SYSTEM AROUND A MICROPROCESSOR IS MUCH THE SAME AS DESIGNING AROUND CONVENTIONAL LOGIC. tHE TOTAL APPROACH IS THE SAME; THE PROCESS DIFFERS ONLY IN THE IMPLE- MENTATION OF EACH STEP. a BRIEF EXAMINATION OF THE SYSTEM DESIGN PROCESS WILL HELP TO PUT MICRO- COMPUTER DESIGN IN PERSPECTIVE AND WILL ALSO ASSIST IN CLARIFYING THE PURPOSE OF THIS MANUAL. oNE CAN EXPECT TO PERFORM THE FOLLOWING STEPS IN DESIGNING A SYSTEM: 1. dEFINE THE REQUIREMENTS OF THE SYSTEM. wHAT FUNCTIONS SHOULD IT PERFORM? 2. dEFINE BASIC SYSTEM COMPONENTS. 3. cOMPLETE DESIGN DETAILS. 4. bUILD AND TEST PROTOTYPES. 5. fINALIZE DESIGN AND BEGIN PRODUCTION. sTEP 1 IS TRUE FOR ANY SYSTEM AND, IN GENERAL, FOR ANY PRODUCT. sTEP 2 IS THE FIRST POINT OF DEPARTURE FOR MICROPROCESSOR BASED DESIGNS. iT IS AT THIS TIME THAT THE DESIGNER MUST CONSIDER THE POSSIBILITY OF USING A MICROPROCESSOR IN HIS SYSTEM. fOR THE VERY COST-SENSITIVE APPLICATION HE MUST LOOK VERY CARE- FULLY AT TOTAL SYSTEMS COST. cAN A MICROPROCESSOR DO THE JOB WITHIN THE PRICE CONSTRAINTS IMPOSED? aT THE OTHER END OF THE DESIGN SPECTRUM, THE SYSTEM DE- SIGNER MUST EVALUATE THE CAPABILITY OF MICROPROCESSORS TO ASSURE HIMSELF THAT THE AVAILABLE DEVICES CAN IN FACT PERFORM THE REQUIRED FUNCTION. wILL A MICRO- PROCESSOR BE FAST ENOUGH TO RUN THE SYSTEM? wILL IT TAKE MORE THAN ONE PROCES- SOR? tHE PURPOSE OF THIS MANUAL IS TO TEACH THE DESIGNER HOW TO EFFECTIVELY CON- FIGURE A MICROPROCESSOR-BASED SYSTEM AND TO EVALUATE THE PERFORMANCE OF THE SYS- TEM. aFTER THIS STEP, THE DESIGN WILL BE COMPLETED BY DEVELOPMENT OF THE SYSTEM PROGRAM. iMPLEMENTATION OF THE SYSTEM PROGRAM IS DISCUSSED IN THE pROGRAMMING mANUAL. -3- ============================================================================ 1.1 introduction to microcomputer systems 1.1.1 oRGANIZATION OF A mICROCOMPUTER sYSTEM fIGURE 1.1 ILLUSTRATES THE BASIC ORGANIZATION OF A MICROCOMPUTER SYSTEM. iT IS IMPORTANT THAT THE DESIGNER UNDERSTAND THE OPERATION OF EACH COMPONENT AS WELL AS THE OPERATION OF EACH DATA PATH IN THE SYSTEM. eACH OF THESE IS DISCUSSED SEPARATELY BELOW. iN ADDITION, THE FOLLOWING DISCUS- SION DESCRIBES THE OPERATION OF THE OVERALL SYSTEM AND THE USE OF THE VARI- OUS SIGNAL PATHS. 1.1.2 bASIC oPERATION tHE MICROCOMPUTER IS A SYSTEM WHICH CAN BE CHARACTERIZED AS VERY SIMPLE IN ITS DETAIL AND VERY COMPLEX IN ITS OVERALL OPERATION. iT CARRIES OUT RATHER COMPLEX TASKS BY PERFORMING A LARGE NUMBER OF SIMPLE OPERATIONS. cONTROL OF THE SYSTEM IS PRIMARILY THE RESPONSIBILITY OF THE PROCESSOR. bY PUTTING OUT ADDRESSES TO PROGRAM MEMORY, IT CONTROLS THE SEQUENCE OF OPERATIONS PERFORMED AND BY INTERPRETING AND EXECUTING THE INSTRUCTIONS WHICH IT RECEIVES FROM THE PROGRAM MEMORY, IT CONTROLS THE ACTUAL OPERATIONS CARRIED OUT BY THE SYSTEM. tHE PROCESSOR IS BY FAR THE MOST COMPLEX DEVICE IN THE SYSTEM. fOR THIS REASON, IT IS IMPORTANT TO OVERALL SYSTEM COST THAT THIS PART STAY THE SAME FOR MANY DIFFERENT APPLI- CATIONS. iN THIS WAY, THE RELATIVELY HIGH DEVELOPMENT COST CAN BE SHARED BY THOUSANDS OF USERS. iN ADDITION, THOSE THOUSANDS OF USERS CAN ALL BENE- FIT FROM THE ECONOMICS OF LARGE-SCALE PRODUCTION. tHE PROCESSOR CAUSES THE SYSTEM TO PERFORM THE DESIRED OPERATIONS BY READING THE FIRST INSTRUCTION IN THE PROGRAM, AND PERFORMING THE VERY SIMPLE TASK DICTATED BY THE SPECIFIC PATTERN OF BITS IN THIS INSTRUCTION (REFERRED TO AS "EXECUTING" THAT INSTRUCTION). iT THEN GOES ON TO THE NEXT INSTRUC- TION IN THE PROGRAM AND EXECUTES IT. tHIS SIMPLE OPERATION OF FETCHING AN INSTRUCTION AND EXECUTING IT IS PERFORMED OVER AND OVER, EACH TIME ON THE NEXT INSTRUCTION IN SEQUENCE. iN THIS WAY THE PROGRAM INSTRUCTS THE PRO- CESSOR TO BRING ABOUT THE DESIRED SYSTEM OPERATION. 1.1.3 aDDRESSING tERMS AND cONCEPTS bEFORE ENTERING INTO A DETAILED DISCUSSION OF THE SYSTEM OPERATION, IT WOULD BE USEFUL TO DEFINE A FEW TERMS AND TO INTRODUCE A FEW CONCEPTS CONCERNING ADDRESSING. tHIS SHOULD ASSIST IN AN UNDERSTANDING OF THE DETAILED DISCUSSIONS WHICH FOLLOW. -4- ============================================================================ i/o port ____^____ / \ ^ ^ ^ ^ ^ ^ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ----------- ----------- --+-+-+-+-+-+-- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} program {$7c} {$7c} data {$7c} {$7c} peripheral {$7c} {$7c} memory {$7c} {$7c} memory {$7c} {$7c} interface {$7c} {$7c} (rom) {$7c} {$7c} (ram) {$7c} {$7c} device {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ----------- ----------- --------------- ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ h h {$7c} {$7c} {$7c} h h {$7c} h h {$7c} {$7c} h h ------------O-+-h-h----------- h h {$7c} {$7c} h h {$7c} {$7c} h h h h {$7c} {$7c} ==#==h==================h=#=============h==#============= address h {$7c} {$7c} h h {$7c} {$7c} bus h {$7c} {$7c} h h {$7c} {$7c} h {$7c} {$7c} h h {$7c} {$7c} =====#==================#===============#================ data {$7c} {$7c} {$7c} {$7c} bus {$7c} {$7c} {$7c} {$7c} write <----------------O-+----------------------- {$7c} enable {$7c} {$7c} {$7c} {$7c} {$7c} ------------------ {$7c} ------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} clock +-----O-->{$7c} microprocessor {$7c}<--- {$7c} {$7c} {$7c} {$7c} interrupts {$7c} generator {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}----> other ------------- {$7c} {$7c} control {$7c} {$7c}<---- signals {$7c} {$7c} ------------------ oRGANIZATION OF mICROCOMPUTER sYSTEM figure 1.1 -5- ============================================================================ 1.1.3.1 bIT tHE TERM "bIT" IS A GENERAL TERM REFERRING TO ANYTHING THAT CAN BE ASSIGNED TO BINARY VALUE, I.E., ANYTHING THAT CAN BE GIVEN A VALUE OF 0 OR 1. tHUS, AN EIGHT-BIT DATA BUS IS A SET OF 8 LINES WHICH CAN BE ASSIGNED A VALUE OF LOGIC 0 OR LOGIC 1. oN THESE LINES, THE LOGIC VALUES ARE REPRE- SENTED BY TWO DIFFERENT VOLTAGES OR CURRENTS. sIMILARLY, A 16-BIT BINARY DISPLAY CAN BE BUILT WITH 16 INDIVIDUAL LAMPS. tHE LOGIC 1 IS REPRESENTED BY THE LAMP BEING ON. iN THIS TEXT, REFERENCE IS MADE TO AN 8-BIT DATA BUS, A 16-BIT ADDRESS BUS, 4 BITS OF DATA, 8-BIT REGISTERS, ETC. iN ALL CASES, DEFINI- TION OF A BIT REMAINS THE SAME. 1.1.3.2 aDDRESS sPACE tHE CONCEPT OF AN ADDRESS SPACE IS VERY USEFUL IN UNDERSTANDING MICROCOMPUTER SYSTEMS. tHE TERM "ADDRESS SPACE" REFERS TO THE TOTAL SET OF ADDRESSES WHICH THE MICROPROCESSOR CAN GENERATE. fOR EXAMPLE, IF A PRO- CESSOR HAD ONLY 4 ADDRESS LINES, IT COULD GENERATE THE ADDRESSES 0 - 15 (BINARY 0000 TO BINARY 1111). tHIS WOULD NOT BE ADEQUATE FOR ANY MICROCOM- PUTER OPERATION AND, CONSEQUENTLY, THE TYPICAL PROCESSOR HAS BETWEEN 12 AND 16 ADDRESS LINES. sINCE EACH LINE CAN ASSUME A VALUE OF 0 OR 1, THESE DE- VICES CAN USUALLY ADDRESS FROM 4,096 TO 65,536 SEPARATE ADDRESSES. fIGURE 1.2 CONTAINS A PICTORIAL REPRESENTATION OF THE ADDRESS SPACE AVAILABLE IN A TYPICAL 8-BIT MICROCOMPUTER WITH SIXTEEN ADDRESS LINES. iN ADDITION TO THE GENERAL ADDRESS SPACE, THIS FIGURE INTRODUCES THE page CONCEPT DIS- CUSSED BELOW. 1.1.3.3 tHE aDDRESS pAGE tHE CONCEPT OF A page IN MEMORY IS VERY IMPORTANT IN 8-BIT MICRO- COMPUTER SYSTEMS. tHE INTERNAL ORGANIZATION OF AN 8-BIT PROCESSOR IS AROUND 8-BIT REGISTERS, 8-BIT PARALLEL DATA PATHS, ETC. mOST ARITHMETIC OPERATIONS, LOGIC OPERATIONS, ETC. TAKE PLACE ON 8 BITS OF DATA AT A TIME. lIKEWISE, THE 16-BIT COUNTER WHICH DETERMINES WHICH INSTRUCTION IS BEING EXECUTED IS ACTUALLY DIVIDED INTO TWO 8-BIT BUSSES. oNE CONTAINS BITS 0 - 7 (LOW ORDER ADDRESS BITS) AND THE OTHER CONTAINS BITS 8 TO 15 (HIGH ORDER ADDRESS BITS). wITH THIS IN MIND, ONE CAN THINK OF THE ADDRESS SPACE SHOWN IN fIGURE 1.2 AS CONSISTING OF 256 BLOCKS, EACH CONSISTING OF 256 SPECIFIC ADDRESS LOCATIONS. eACH OF THESE BLOCKS IS REFERRED TO AS A "page" -6- ============================================================================ lANDSCAPE FIGURE REPRESENTING NUMBERS IN BINARY, DECIMAL AND HEX FORMAT. -7- ============================================================================ OF MEMORY. tHE HIGH ORDER 8 BITS OF THE ADDRESS (adh) THEREFORE INDICATES IN WHICH PAGE THE ADDRESS IS LOCATED, AND THE LOW ORDER 8 BITS (adl) INDI- CATES A SPECIFIC ADDRESS ON THAT PAGE. tHE FIRST PAGE IN MEMORY (adh = 00) IS REFERRED TO AS PAGE ZERO. tHE NEXT HIGHER ORDER PAGE (adh = 01) IS REFERRED TO AS PAGE 1, ETC. 1.1.4 sYSTEM cOMPONENTS tHE BLOCK DIAGRAM IN fIGURE 1.1 SHOWS THE BASIC COMPONENTS WHICH COMPRISE ALL MICROCOMPUTER SYSTEMS. eACH OF THESE BLOCKS MAY CONSIST OF ONE OR MORE INTEGRATED CIRCUITS AND, IN FACT, THE FUNCTIONS MAY BE COM- BINED INTO SINGLE CHIPS. hOWEVER, THE BASIC OPERATION OF EACH REMAINS THE SAME. 1.1.4.1 cLOCK gENERATOR tHE CLOCK GENERATOR PRODUCES A CONTINUOUS WAVEFORM WHICH IS NORMALLY USED TO CONTROL ALL SIGNAL TRANSITIONS WITHIN THE SYSTEM. iT ACTS AS THE "HEART" OF THE SYSTEM. iN THE TYPICAL MICROCOMPUTER SYSTEM THE ADDRESS BUS WILL CHANGE DURING ONE HALF OF THE CLOCK CYCLE AND THE DATA WILL BE TRANSFERRED DURING THE SECOND HALF. iN ADDITION TO INTERPRETING THE ADDRESS, DATA AND CONTROL LINES, THE PROCESSOR AND SUPPORT CHIPS MUST ALSO EXAMINE THE SYSTEM CLOCK TO KNOW WHEN TO PUT oUT DATA OR WHEN TO LATCH IN DATA GENERATED BY ANOTHER DEVICE. 1.1.4.2 pROGRAM mEMORY tHE PROGRAM MEMORY STORES THE SEQUENCE OF INSTRUCTIONS WHICH COM- PRISES THE SYSTEM PROGRAM. lIKE ANY MEMORY, THIS UNIT PUTS A PATTERN OF 1'S AND 0'S ON THE DATA BUS IN RESPONSE TO THE ADDRESS ON THE ADDRESS BUS INPUT. eACH UNIQUE ADDRESS SELECTS A SET OF 8 BINARY BITS AND PLACES THIS DATA ON THE DATA BUS. nOTE THAT IT DOES NOT MATTER WHERE THE ADDRESS IS GENERATED OR WHERE THE DATA IS USED; THE MEMORY SIMPLY OBEYS THE RULE THAT, GIVEN AN ADDRESS, IT WILL PUT THE CORRESPONDING 8 BITS OF DATA ON THE DATA BUS. a UNIQUE CHARACTERISTIC OF MOST MICROPROCESSOR-BASED SYSTEMS IS THAT THE PROGRAM IS USUALLY STORED IN "read-only" MEMORIES. tHE DATA IS STORED IN A FIXED PATTERN OF BITS IN THE MEMORY. fIGURE 1.3 SHOWS A SEC- TION OF A SEMICONDUCTOR read-only mEMORY (rom). -8- ============================================================================ [ pICTURE OF THE SILICON CHIP INSIDE THE rom ] pORTION OFrEAD oNLY mEMORY mATRIX figure 1.3 sINCE THE DATA IS STORED IN THE PHYSICAL CONFIGURATION OF THE DEVICE, THE DATA WILL NOT BE LOST WHEN POWER IS DISCONNECTED FROM THE CHIP. iN ADDI- TION, IT IS ONLY NECESSARY TO INSERT THE DEVICE INTO ITS SOCKET TO PRO- VIDE THE SYSTEM PROGRAM. tHE TERM "rEAD-oNLY mEMORY" REFERS TO THE FACT THAT, IN SYSTEM OPERATION, IT IS IMPOSSIBLE FOR THE PROCESSOR TO CAUSE DATA TO BE STORED IN THE DEVICE. tHE PROCESSOR CAN ONLY "read" THE DATA STORED IN THE DEVICE DURING THE MANUFACTURING PROCESS. "reading" A MEMORY IN- VOLVES THE SIMPLE PROCESS OF SUPPLYING AN ADDRESS TO THE DEVICE TO OBTAIN THE CORRESPONDING 8 BITS OF DATA ON THE DATA BUS. 1.1.4.3 dATA mEMORY fOR TEMPORARY STORAGE OF INPUT DATA, THE RESULTS OF ARITHMETIC OPERATIONS, ETC., THE MICROCOMPUTER USES A rEAD/wRITE mEMORY, COMMONLY RE- FERRED TO AS A ram (rANDOM aCCESS mEMORY). tHE PROCESSOR CAN STORE DATA IN THE ram (CALLED "writing" THE ram), OR IT CAN READ BACK THE DATA IT HAS STORED. aS IN THE rom, EACH ADDRESS CORRESPONDS TO EIGHT MEMORY CELLS. hOWEVER, IN A ram THE DATA MUST BE PLACED INTO THE MEMORY BY THE PROCESSOR AND IS STORED IN CROSS-COUPLED LATCHES. tURNING OFF THE POWER TO THE CHIP WILL CAUSE THE LOSS OF ALL DATA STORED THERE. tHE DATA IS SAID TO BE -9- ============================================================================ "VOLATILE." dATA IN A rom IS NOT LOST WHEN POWER IS DISCONNECTED FROM THE DEVICE; THE DATA IS THEREFORE REFERRED TO AS "NON-VOLATILE." "writing" DATA INTO A ram TAKES PLACE WHEN THE wRITE-eNABLE SIGNAL GOES TO THE WRITE STATE. aT THIS TIME THE DATA ON THE DATA BUS WILL BE STORED INTO THE EIGHT MEMORY CELLS CORRESPONDING TO THE ADDRESS ON THE AD- DRESS BUS. tHE PROCESSOR CAN read THIS SAME DATA BY SUPPLYING THE PROPER ADDRESS AND KEEPING THE wRITE-eNABLE LINE IN THE rEAD STATE. 1.1.4.4 iNPUT/oUTPUT dEVICES tHE iNPUT/oUTPUT dEVICES ARE THE CIRCUITS WHICH INTERFACE THE PRINTER, KEYBOARD, DISPLAYS, ETC. TO THE PROCESSOR. tHESE ALLOW THE PRO- CESSOR TO READ DATA FROM THE KEYBOARD, TO TEST THE STATE OF SENSORS AND SWITCHES, AND TO DISPLAY OR TO PRINT THE RESULTS OF INTERNAL OPERATIONS. nO MATTER WHERE DATA IS GENERATED, IT MUST BE IN THE FORM OF 1'S AND 0'S BEFORE THE PROCESSOR CAN WORK WITH IT. lIKEWISE, ACTIONS TO BE INITIATED BY THE PROCESSOR MUST BE TRIGGERED BY 1'S AND 0'S TRANSFERRED BY THE PROCESSOR TO A SET OF OUTPUT LINES. tHE TRANSFER OF DATA FROM THE PROCESSOR TO AN OUTPUT DEVICE IS USUALLY ACCOMPLISHED BY "writing" THE DATA OUT IN MUCH THE SAME MANNER AS THE PROCESSOR WRITES DATA INTO ram. eACH SET OF 8 INPUT OR OUTPUT LINES (REFERRED TO AS "port") IS GIVEN AN ADDRESS AND THE PROCESSOR SIMPLY WRITES DATA TO THAT ADDRESS. fOR EACH "1" WRITTEN OUT TO THE PERIPHERAL PORT AN OUTPUT IS SET HIGH AND FOR EACH "0," THE CORRESPONDING OUTPUT IS SET LOW. aLTHOUGH THE BASIC CONCEPT OF PERIPHERAL CONTROL IS SIMPLE, THE ACTUAL IMPLEMENTATION OF THESE INTERFACES CAN INVOLVE MANY SOPHISTICATED TECHNIQUES DESIGNED TO ALLOW THE PROCESSOR TO MAXIMIZE ITS ABILITY TO CON- TROL PERIPHERALS AND PERFORM INTERNAL OPERATIONS CONCURRENTLY. tHESE TECH- NIQUES ARE DISCUSSED IN DETAIL IN cHAPTER 2 OF THIS MANUAL. 1.1.4.5 tHE mICROPROCESSOR aT FIRST GLANCE IT MAY SEEM STRANGE TO DISCUSS THE SUPPORT CHIPS IN THE MICROPROCESSOR-BASED SYSTEM BEFORE MENTIONING THE PROCESSOR. hOW- EVER, THIS APPROACH IS NECESSITATED BY THE FACT THAT MOST OF THE INPUTS AND OUTPUTS ON THE PROCESSOR ARE AIMED AT PROPERLY CONTROLLING THE SUPPORT CHIPS AND PERIPHERAL DEVICES DISCUSSED ABOVE. tHE ADDRESS BUS, THE BI-DIRECTIONAL DATA BUS AND THE wRITE-eNABLE LINE ALLOW THE PROCESSOR TO EXERCISE DIRECT CONTROL OVER THE REST OF THE SYSTEM. tHE ADDRESS BUS PUTS OUT ADDRESSES TO CONTROL THE SOURCE OR DESTINATION OF DATA TRANSFERS. tHESE ADDRESSES ARE DERIVED FROM VARIOUS -10- ============================================================================ SOURCES WITHIN THE PROCESSOR. dURING THE FETCH OF INSTRUCTIONS FROM PRO- GRAM MEMORY, THE ADDRESSES ARE USUALLY DERIVED FROM A COUNTER WHICH CON- TROLS EXECUTION OF SEQUENTIAL INSTRUCTIONS. aDDRESSES FOR DATA TRANSFERS BETWEEN THE PROCESSOR AND ram ARE USUALLY DERIVED DIRECTLY FROM THE PROGRAM OR ARE CALCULATED FROM THE DATA IN THE PROGRAM AND DATA IN INTERNAL REGIS- TERS. tHE BI-DIRECTIONAL DATA BUS SERVES AS A PATH FOR TRANSFERRING DATA INTO AND OUT OF THE PROCESSORS. tHE DIRECTION OF THE DATA TRANSFER IS DE- TERMINED BY THE wRITE-eNABLE LINE. aNOTHER SPECIAL FUNCTION FOUND IN MODERN MICROCOMPUTER SYSTEMS IS THE INTERRUPT. tHIS FUNCTION ALLOWS THE PERIPHERAL DEVICES TO DIRECTLY AFFECT THE OPERATION OF THE PROCESSOR. wHEN THE INTERRUPT SIGNAL IS GENER- ATED, THE PROCESSOR USUALLY COMPLETES ITS CURRENT INSTRUCTION AND THEN, UNDER PROGRAM CONTROL, WILL RESPOND TO THE INTERRUPT. tHE IMPORTANCE OF THIS FUNCTION IS THAT IT ALLOWS THE PROCESSOR TO EXECUTE THE SYSTEM PROGRAM WITHOUT REQUIRING THE SYSTEM PROGRAM TO MONITOR THE STATUS OF THE PERIPHERAL DEVICE. tHE SOFTWARE WHICH HANDLES THE OPERATION OF EACH PERIPHERAL WILL BE EXECUTED ONLY WHEN REQUIRED. -11- ============================================================================ 1.2 introduction to the mcs6sox microprocessor famtH y tHE INITIAL mos tECHNOLOGY, iNC. MICROPROCESSOR OFFERING CONSISTS OF THE mcs6501, WHICH IS mc6800 COMPATIBLE; THE mCs6502, WHICH HAS CLOCK DRIVERS ON- CHIP; AND THREE 28-PIN PROCESSORS, THE mcs6503, mCs6504, AND mcs6505. aLL OF THESE DEVICES ARE AIMED AT A SPECIFIC RANGE OF APPLICATIONS. tHEREFORE, IT IS IMPORTANT TO DEVELOP AN UNDERSTANDING OF THE CAPABILITIES OF EACH AND THE DIF- FERENCES BETWEEN THEM. tHE mcs6501 HAS APPLICATION IN EXISTING n6800 SYSTEMS WHERE CONVERSION TO THE mos tECHNOLOGY, iNC. PROCESSOR IS TO BE PERFORMED. tHIS PROCESSOR REQUIRES THE FULL HIGH-LEVEL TWO-PHASE CLOCKS OF THE n6800 SYSTEM. tHE mCs6502 IS EX- PECTED TO FIND APPLICATION IN ALL NEW DESIGNS WHICH REQUIRE A FULL 16-BIT AD- DRESS BUS. hOWEVER, IN THE SMALL COST-SENSITIVE SYSTEM, THE 28-PIN PROCESSORS CAN REPRESENT A SAVINGS IN BOTH PROCESSOR COST AND PRINTED CIRCUIT BOARD AREA. tHE mcs6503, mcs6504, AND mcs6505 WILL FIND APPLICATION IN ALL NEW DESIGNS WHERE THE SYSTEM WILL OPERATE WITHIN THE ADDRESSING LIMITS. 1.2.1 tHE mcs6501 tHE mCS6501 IS THE FIRST MEMBER OF THE MICROPROCESSOR FAMILY TO BE INTRODUCED. iT IS DESIGNED TO BE PIN COMPATIBLE WITH THE m6800 AND THERE- FORE CONVERSION FROM THE mc6800 TO THE mos tECHNOLOGY, iNC. mCs6501 RE- QUIRES ONLY THAT THE SYSTEM BE REPROGRAMMED. tHIS ALLOWS THE m6800 USER TO TAKE FULL ADVANTAGE OF THE SOFTWARE POWER (ADDRESSING MODES, ETC.) OF THE mcs650x PROCESSOR FAMILY. aLTHOUGH THE CONVERSION PROCESS IS FAIRLY SIMPLE, IT IS IMPORTANT TO KEEP IN MIND THE DIFFERENCES BETWEEN THE mc6800 AND THE mcs6501. tHE PINS ON THE mcs6501 ALL DO THE SAME GENERAL FUNCTION AS THOSE ON THE mc6800 BUT THE FUNCTION PERFORMED MAY DIFFER SOMEWHAT IN DETAIL. fIGURE 1.4 CONTAINS A DETAILED, PIN-FOR-PIN COMPARISON OF THESE TWO PROCESSORS. a THOROUGH UNDERSTANDING OF THIS TABLE, ALONG WITH AN UNDERSTANDING OF THE mcs650x SOFTWARE WILL ALLOW THE SYSTEM DESIGNER TO PERFORM THE CONVERSION WITH VERY LITTLE DIFFICULTY. tHE mcs6501 PROVIDES A FULL 16-BIT ADDRESS BUS, 8-BIT DATA BUS AND TWO INTERRUPTS. -12- ============================================================================ -------------------------------------+---------------------------------- motorola mos technology {$7c} motorola mos technology pin # 6800 6501 {$7c} pin # 6800 6501 -------------------------------------+---------------------------------- 1 vSS vSS {$7c} 21 vSS vSS 2* hALT rEADY {$7c} 22 a12 a12 3 p1 (IN) p1 (IN) {$7c} 23 a13 a13 4 irq irq {$7c} 24 a14 a14 5* vma vma {$7c} 25 a15 a15 6 nmi nmi {$7c} 26 d7 d7 7 ba ba {$7c} 27 d6 d6 8 vDD vDD {$7c} 28 d5 d5 9* a0 a0 {$7c} 29 d4 d4 10 a1 a1 {$7c} 30 d3 d3 11 a2 a2 {$7c} 31 d2 d2 12 a3 a3 {$7c} 32 d1 d1 13 a4 a4 {$7c} 33 d0 d0 14 a5 a5 {$7c} 34 r/w r/w 15 a6 a6 {$7c} 35 n.c. n.c. 16 a7 a7 {$7c} 36 dbe dbe 17 a8 a8 {$7c} 37 p2 (IN) p2 (IN) 18 a9 a9 {$7c} 38* n.c. n.c. 19 a10 a10 {$7c} 39* tsc 20 a11 aLL {$7c} 40 rESET rESET {$7c} -------------------------------------+---------------------------------- * differences ------------------------------------------------------------------------ pin # motorola 6800 mos technology 6501 ------------------------------------------------------------------------ 2 hALT - sTOPS PROCESSOR AFTER rEADY - sTOPS pROCESSOR DURING COMPLETING CURRENT INSTRUCTION. CURRENT INSTRUCTION. aDDRESS aDDRESS bUS IN OFF STATE. bUS REFLECTS CURRENT ADDRESS BEING READ. 5 vma - sIGNAL DETERMINES WHEN vma - nO NEED FOR vALID mEMORY ADDRESS FRON PROCESSOR IS aDDRESS sIGNAL. aLL ADDRESSES vALID. ARE VALID AT ALL TIMES. tHIS PIN IS INTERNALLY TIED TO vDD AND CAN BE USED AS A vma SIGNAL IN HIGH STATE. 9 aDDRESS bUS USES tRI-sTATE aDDRESS bUS USES ttl LEVEL oUTPUT bUFFERS. oUTPUT dRIVERS. 38 nO cONNECTION 39 t.s.c. - tHREE-sTATE cONTROL n.c. - nO NEED FOR tsc SINCE cONTROLS ALL tHREE-sTATE aDDRESS IS NOT tHREE-sTATE AND bUFFERS, aDDRESS bUS AND dbe cONTROLS tHREE-sTATE OF dATA bUS. dATA bUS. pINOUT cOMPARISON mos technology inc. mcs65o1, motorola mc6800 figure 1.4 -13- ============================================================================ 1.2.2 tHE mcs6502 tHE SECOND MEMBER OF THE PROCESSOR FAMILY IS A 40-PIN DEVICE WHICH PROVIDES ALL THE FEATURES OF THE mcs6501, ALONG WITH AN "ON-THE-CHIP" OSCIL- LATOR AND CLOCK DRIVERS. tHIS DEVICE SHOULD BE USED IN ALL NEW DESIGNS WHICH REQUIRE THE CAPABILITY OF THE 40-PIN PROCESSORS. tHE CLOCK DRIVERS CAN BE DRIVEN WITH A SINGLE ttl LEVEL SQUARE WAVE OR WITH THE INTERNAL OSCILLATOR. tHE FREQUENCY OF OPERATION OF THE INTERNAL OSCILLATOR CAN BE SET BY ATTACHING AN r-c COMBINATION TO THE CHIP AND, IF THE CLOCK STABILITY IS REQUIRED, BY ATTACHING A CRYSTAL BETWEEN THE OSCILLATOR AND GROUND. tHIS FEATURE TOTALLY ELIMINATES THE PROBLEMS ENCOUNTERED IN GENERATING mc6800 TYPE CLOCK SIGNALS. aS IN THE mcs6501, THE mcs6502 PROVIDES A FULL 16-BIT ADDRESS BUS, 8-BIT BI-DIRECTIONAL DATA BUS AND TWO INTERRUPTS. iN ADDITION, THE mcs6502 PROVIDES A SYNC SIGNAL WHICH INDICATES THOSE CYCLES IN WHICH THE PROCESSOR IS FETCHING AN OPERATION CODE FROM PROGRAM MEMORY. 1.2.3 tHE mcs6503, mcs6504 AND mcs6505 tHREE 28-PIN VERSIONS OF THE PROCESSOR ARE AVAILABLE. tHESE THREE DIFFER IN THE NUMBER OF ADDRESS LINES AND THE NUMBER OF INTERRUPTS PROVIDED. hAVING ALL THREE OPTIONS AVAILABLE ALLOWS THE DESIGNER TO TAILOR HIS PRO- CESSOR TO HIS PARTICULAR APPLICATION. tHE mgs6504 PROVIDES A TOTAL OF 13 ADDRESS PINS AND CAN, THEREFORE, ADDRESS A FULL 8k BYTES IN ITS MEMORY SPACE. hOWEVER, THIS PART PROVIDES ONLY ONE INTERRUPT REQUEST INPUT, irq. tHE NON-MASKABLE INTERRUPT (nmi) IS NOT INCLUDED IN THE PINOUTS OF THIS DEVICE. tHE mcs6503 AND mcs6505 PROVIDE ONE LESS ADDRESS LINE. iN THE mcs6503, THIS ADDRESS LINE IS REPLACED WITH A SECOND INTERRUPT INPUT, nmi. iN THE mcs6505, THIS ADDRESS LINE IS REPLACED BY THE rdy SIGNAL. a1L OTHER FUNCTIONS ON THESE PROCESSORS ARE THE SAME. tHE DETAILS OF EACH OF THESE PINS ARE DISCUSSED IN THE FOLLOWING SECTIONS. tHE OPERATION OF THE VARIOUS BUSSES, CONTROL SIGNALS, ETC. IS EX- ACTLY THE SAME ON ALL mcs650x PRODUCTS WITH ALL PROCESSORS OBEYING THE SYS- TEM SPECIFICATIONS DISCUSSED IN sECTION 1.3 OF THIS MANUAL. -14- ============================================================================ 1.3 mcs6soo system concepts 1.3.1 bUS sTRUCTURE tHE mcs6500 MICROCOMPUTER SYSTEM IS ORGANIZED AROUND TWO PRIMARY BUSSES. eACH BUS CONSISTS OF A SET OF PARALLEL PATHS WHICH CAN BE USED TO TRANSFER BINARY INFORMATION BETWEEN THE DEVICES IN A SYSTEM. tHE FIRST BUS, KNOWN AS THE address bus, IS USED TO TRANSFER THE ADDRESS GENERATED BY THE PROCESSOR TO THE ADDRESS INPUTS OF THE MEMORY AND PERIPHERAL INTERFACE DEVICES. tHE PROCESSOR IS THE ONLY SOURCE OF ADDRESSES IN A NORMAL SYSTEM, SO THIS BUS IS REFERRED TO AS "UNIDIRECTIONAL." tHE ADDRESS BUS CONSISTS OF 16 LINES ON THE mcs6501 AND mcs6502. tHIS ALLOWS THE PROCESSOR TO ACCESS (read OR write) UP TO A TOTAL OF 65,536 MEMORY WORDS, REGISTERS, ETC. iN THE mcs6503, mcs6504, AND mcs65o5, THE ADDRESS BUS CONTAINS FEWER LINES; THEREFORE, THEY OPERATE WITH A SMALLER "ADDRESS SPACE." tHIS IS DISCUSSED IN DETAIL IN sECTION 1.1.3. tHE DATA BUS IN THE mcs6500 MICROCOMPUTER SYSTEM CONSISTS OF AN 8-BIT BI-DIRECTIONAL DATA PATH. tHESE LINES TRANSFER DATA FROM THE PROCESSOR TO THE SELECTED MEMORY WORD, ETC. DURING A write OPERATION AND FROM MEMORY INTO THE PROCESSOR DURING A read OPERATION. aLL DATA AND ALL INSTRUCTIONS ARE TRANSMITTED ON THE DATA BUS. tHE DIRECTION OF THE DATA TRANSFERS IS CONTROLLED BY THE read/write (r/w) LINE ON THE PROCESSOR. tHIS LINE PERFORMS THE wRITE eNABLE FUNCTION DESCRIBED IN sECTION 1.1.4.3. aS LONG AS THE r/w LINE IS HIGH (> 2.4V dc), ALL DATA TRANSFERS WILL TAKE PLACE FROM MEMORY TO THE PROCESSOR (read OPERA- TION). tHIS LINE WILL GO LOW ONLY WHEN THE PROCESSOR IS GOING TO write DATA OUT TO MEMORY. aS IN MOST MICROCOMPUTER SYSTEMS, THE TIMING OF ALL DATA TRANSFERS IS CONTROLLED BY THE SYSTEM CLOCK. tHE CLOCK ITSELF IS ACTUALLY TWO NON- OVERLAPPING SQUARE WAVES. tHIS TWO-PHASE CLOCK SYSTEM CAN BEST BE THOUGHT OF AS TWO ALTERNATING POSITIVE-GOING PULSES. tHIS TEXT WILL REFER TO THE CLOCKS AS pHASE oNE AND pHASE tWO. a pHASE oNE CLOCK PULSE IS THE POSITIVE PULSE DURING WHICH THE ADDRESS LINES CHANGE AND A pHASE tWO CLOCK PULSE IS THE POSITIVE PULSE DURING WHICH THE DATA IS TRANSFERRED. tHE TIMING OF THE SIGNALS ON THE aDDRESS bUS, dATA bUS, AND r/w LINE ARE SHOWN IN fIGURES 1.5 THROUGH 1.8. aLL SIGNAL TRANSITIONS ARE SPECIFIED WITH RESPECT TO THE pHASE oNE AND pHASE tWO CLOCK SIGNALS. -15- ============================================================================ iN PARTICULAR, THE ADDRESS LINES AND THE r/w LINE WILL STABILIZE DURING pHASE oNE, AND ALL DATA TRANSFERS WILL TAKE PLACE DURING pHASE tWO. tHE SPECIFIC TIMING SPECIFICATIONS FOR OPERATING AT A 1 mhZ CLOCK RATE ARE ALSO GIVEN IN fIGURE 1.5. nOTE THAT THE SEQUENCE OF OPERATIONS WILL BE THE SAME FOR ALL PROCESSORS. hOWEVER, THESE TIMING SPECIFICATIONS WILL CHANGE FOR DEVICES WHICH ARE SPECIFIED TO OPERATE FASTER THAN 1.0 mhZ. tHE ADDRESS IS GUARANTEED TO BE STABLE 300 NANOSECONDS AFTER THE LEADING EDGE OF pHASE oNE, AND THE DATA MUST BE STABLE 100 NANOSECONDS BEFORE THE TRAILING EDGE OF pHASE tWO. aT 1.0 mhZ OPERATION, THIS ALLOWS THE MEMORY DEVICES APPROXIMATELY 575 NS TO MAKE DATA AVAILABLE ON THE DATA BUS. aL- THOUGH THERE ARE MANY FACTORS WHICH DETERMINE THE ACTUAL DATA AND ADDRESS GENERATED WITHIN THE SYSTEM, IT IS IMPORTANT TO KEEP IN MIND THAT THE BASIC OPERATION SHOWN IN fIGURES 1.6, 1.7 AND 1.8 DOES NOT CHANGE. tHESE FIGURES SPECIFY THE SYSTEM BUS DISCIPLINE WHICH APPLIES TO ALL mos tECHNOL- OGY, iNC. PROCESSORS AND SUPPORT CHIPS. 1.3.2 pROCESSOR iNTERRUPTS tHROUGH THE GENERATION OF PROCESSOR INTERRUPT SIGNALS, THE PERI- PHERAL DEVICES (PRINTERS, KEYBOARDS, ETC.) CAN REQUEST SERVICE FROM THE PROCESSOR. aLTHOUGH THIS TECHNIQUE IS RELATIVELY SIMPLE IN CONCEPT, THE PROPER GENERATION AND CONTROL OF INTERRUPTS IS ONE OF THE MOST IMPORTANT PROBLEMS WHICH THE DESIGNER WILL FACE. tOTAL SYSTEM CAPABILITY CAN BE GREATLY EXPANDED IF THE PROCESSOR IS REQUIRED TO EXECUTE THE PERIPHERAL SOFTWARE ONLY WHEN IT IS ABSOLUTELY NECESSARY. tHIS IS THE GOAL OF A WELL- PLANNED INTERRUPT STRUCTURE. tHE INTERRUPT STRUCTURE IS VERY MUCH A SYS- TEMS SOPHISTICATION PROBLEM SINCE IT IS THE ENTIRE SYSTEM WHICH MUST PRO- PERLY RESPOND TO THE INTERRUPT INPUTS. iN FACT, THE ACTUAL SIGNALS TO WHICH THE SYSTEM MUST RESPOND ARE USUALLY APPLIED TO THE INPUTS OF A PERI- PHERAL INTERFACE DEVICE. iN THIS DEVICE, THE INTERRUPTS ARE ENABLED, DIS- ABLED AND LATCHED UNTIL THE INTERRUPT IS PROCESSED. tHE PERIPHERAL INTER- FACE DEVICE GENERATES SIGNALS WHICH MEET THE REQUIREMENTS OF THE PROCESSOR INTERRUPT INPUTS. tHERE ARE TWO INTERRUPT INPUT LINES TO THE MICROPROCESSOR, irq (iNTERRUPT rEQUEST) AND nmi (nON-mASKABLE iNTERRUPT). sINCE THE REQUIREMENTS OF THE TWO INTERRUPT INPUTS DIFFER, THEY WILL BE DISCUSSED SEPARATELY BELOW. tHE RESPONSE OF THE PROCESSOR TO THESE IN- PUTS IS VERY SIMILAR, HOWEVER, AFTER THE INTERRUPT IS RECOGNIZED. fOR THIS -16- ============================================================================ tHE FOLLOWING THREE PAGES CONTAIN fIGURE 1.5 TO 1.8 SHOWING DATA AND DIAGRAMS ABOUT THE IN- AND EXTERNAL TIMING OF THE 650x WHICH CAN BE FOUND IN ANY DATABOOK ABOUT THE 6502. -17, 18, 19- ============================================================================ REASON, THE INTERNAL OPERATION OF THE PROCESSOR DURING INTERRUPT SERVICING IS DISCUSSED IN THE DETAILED ANALYSIS OF THE PROCESSOR CHIP. iNSTEAD, THIS SECTION WILL CONCENTRATE ON THE SYSTEM LEVEL CONSIDERATIONS WHICH ARE RE- QUIRED TO ASSURE PROPER OPERATION OF THE INTERRUPT STRUCTURE. 1.3.2.1 aPPLICATIONS FOR iNTERRUPTS oNE OF THE MOST IMPORTANT TASKS FACING THE MICROCOMPUTER SYSTEM DESIGNER IS THE DETERMINATION OF THOSE SIGNALS WHICH WILL CAUSE PROCESSOR INTERRUPTS AND THOSE OPERATIONS WHICH WILL TAKE PLACE IN RESPONSE TO THESE INTERRUPTS. a DETAILED DISCUSSION OF THESE CONSIDERATIONS IS INCLUDED IN cHAPTER 2 OF THE MANUAL; HOWEVER, A FEW EXAMPLES OF INTERRUPT-DRIVEN OPERA- TIONS WILL BE PRESENTED HERE TO HELP THE DESIGNER DEVELOP AN UNDERSTANDING FOR WHY THIS TECHNIQUE IS USED EXTENSIVELY IN MICROCOMPUTER SYSTEMS. eXAMPLE 1--a fULLY-dECODED kEYBOARD tHE PROBLEM OF DATA ENTRY IS SOLVED IN MANY SYSTEMS BY A KEY- BOARD. iN SMALL SYSTEMS, THE INTERPRETATION OF THE BINARY CODE ASSOCIATED WITH EACH KEY CAN BE DETERMINED BY THE PROCESSOR. hOWEVER, IN LARGE DATA TERMINALS, THE KEYBOARD USUALLY INCLUDES AN ENCODER WHICH GENERATES THE UNIQUE CODE CORRESPONDING TO EACH KEY. wHEN A KEY IS CLOSED, THE CORRE- SPONDING CODE IS PLACED ON THE OUTPUT PINS AND A STROBE SIGNAL IS GENERATED TO INDICATE THAT A KEY HAS BEEN PRESSED. tHE KEYBOARD REPRESENTS A PERFECT CANDIDATE FOR INTERRUPT- DRIVEN OPERATION. tHE INTERRUPTS OCCUR RELATIVELY INFREQUENTLY AND THE OPERATION TO BE PERFORMED IS RELATIVELY SIMPLE. tHE KEYBOARD STROBE LINE IS CONNECTED DIRECTLY TO AN INTERRUPT INPUT ON A PERIPHERAL INTERFACE DE- VICE. eACH TIME A STROBE SIGNAL IS GENERATED, AN INTERRUPT OCCURS, THE PROCESSOR READS THE DATA ON THE PERIPHERAL PORT INTO MEMORY, ANALYZES THIS DATA AND THEN RETURNS TO THE PROGRAM THAT WAS IN PROCESS. iF NO KEYS ARE PRESSED, THE PROCESSOR SPENDS NO TIME AT ALL IN SERVICING THE KEYBOARD. wITHOUT THE INTERRUPTS, THE PROCESSOR WOULD HAVE TO READ THE KEYBOARD DATA INTO MEMORY PERIODICALLY IN ORDER TO DETECT AN ACTIVE KEY. tHIS OPERATION WOULD BE PERFORMED ABOUT EVERY FIFTY TO ONE HUNDRED MILLI- SECONDS. iN ADDITION TO DETECTING AN ACTIVE KEY, THE PROCESSOR MUST MAKE SURE THAT EACH SEPARATE ACTIVATION OF A KEY IS DETECTED ONCE AND ONLY ONCE. tHIS IS DISCUSSED IN sECTIONS 1.3.2.5 AND 1.3.2.6. tHIS SOFTWARE IS MUCH MORE COMPLEX THAN THE SIMPLE INTERRUPT ROUTINE. aNOTHER DRAWBACK OF NON- INTERRUPT PROCESSING IS THAT THE PROCESSOR IS REQUIRED TO SPEND A PERIODIC -20- ============================================================================ PORTION OF ITS TIME ON THE KEYBOARD. iN MANY SYSTEMS, THIS IS NOT A PROB- LEM, BUT IN LARGE TERMINALS, ETC., THE TIME SPENT CHECKING FOR KEYBOARD STROBES COULD BE BETTER SPENT IN OTHER OPERATIONS. tHE DESIGNER MUST, THEREFORE, ASK HIMSELF IF THE SYSTEM UNDER DEVELOPMENT IS SUCH THAT THE PROCESSOR CAN PERFORM THE KEYBOARD STROBE CHECKING FUNCTION WHILE STILL COMPLETING ITS OTHER TASKS. eXAMPLE 2--a sCANNED dISPLAY aLTHOUGH TIME IS A MAJOR FACTOR IN DETERMINING THE NECESSITY OF INTERRUPTS, THE INTERRUPT TECHNIQUE CAN ALSO BE EXTREMELY USEFUL WHEN PER- FORMING PARALLEL OPERATIONS. a PRIME EXAMPLE OF THIS CAN BE FOUND IN A SYSTEM WHICH CONTAINS A DIGITAL DISPLAY AND/OR PRINTER. a DIGITAL DISPLAY IS USUALLY "SCANNED" SUCH THAT EACH DIGIT IS DRIVEN FOR A SHORT PERIOD OF TIME IN SEQUENCE. tHE ENTIRE DISPLAY IS SCANNED AT A RATE WHICH THE EYE CANNOT DETECT. hOWEVER, IT CAN BE NOTED HERE THAT THE DISPLAY REQUIRES SCAN-RELATED ATTENTION FROM THE PROCESSOR AT FIXED INTERVALS. iT IS VERY DIFFICULT FOR THE PROCESSOR TO CALCULATE REPETITIVE TIME INTERVALS WHILE IT IS PERFORMING ITS NORMAL SYSTEM PROGRAM ROUTINES. tHE PROCESSOR WOULD MUCH PREFER TO RUN THE SYSTEM PROGRAM WITH- OUT CONSIDERATION FOR THE DISPLAY TIME INTERVALS, ONLY EXECUTING THE DISPLAY SOFTWARE WHEN IT IS REQUIRED. a SOLUTION TO THE ABOVE PROBLEM IS THE GENERATION OF PROCESSOR INTERRUPTS AT FIXED INTERVALS USING AN EXTERNAL COUNTER OR CLOCK. eACH TIME AN INTERRUPT OCCURS, THE DATA FOR THE NEXT DIGIT IN THE DISPLAY IS PLACED ON AN OUTPUT PORT. tHE PROCESSOR THEN RETURNS TO THE PROGRAM IT HAD BEEN EXECUTING. bOTH OF THE OPERATIONS DESCRIBED ABOVE REPRESENT SOLUTIONS TO SYSTEM PROBLEMS. eVENTS WHICH HAPPEN VERY INFREQUENTLY AND EVENTS WHICH MUST BE PERFORMED IN PARALLEL WITH OTHER EVENTS OR IN PARALLEL WITH THE MAIN SYSTEM PROGRAM SHOULD BE SERIOUSLY CONSIDERED AS CANDIDATES FOR INTER- RUPTS. aDDITIONAL CONSIDERATIONS ARE DESCRIBED IN cHAPTER 2 OF THIS MANUAL; HOWEVER, IT IS IMPORTANT TO NOTE HERE THAT THE TYPICAL SYSTEM MAY HAVE SEVERAL SOURCES OF INTERRUPTS, EACH WITH ITS OWN TIMING AND EACH WITH ITS OWN SET OF OPERATIONS WHICH MUST BE PERFORMED IN RESPONSE TO THE INTERRUPTS. -21- ============================================================================ 1.3.2.2 iNTERRUPT pRIORITIZING aFTER A CAREFUL ANALYSIS OF THE TOTAL SYSTEM AND A DETERMINATION OF ALL THE SOURCES OF INTERRUPTS, THE DESIGNER MUST ASK HIMSELF, "wHAT HAP- PENS IF MORE THAN ONE INTERRUPT SOURCE REQUIRES ATTENTION AT ONE TIME?" a PRIORITY LEVEL MUST BE ESTABLISHED BETWEEN THE VARIOUS INTERRUPT SOURCES. wHICH ONES MUST BE TAKEN CARE OF WITHIN A VERY SHORT PERIOD? wHICH ONES CAN BE PUT OFF FOR A WHILE? tHIS PRIORITIZING AND THE TECHNIQUE FOR SELECT- ING AMONG SEVERAL CONCURRENT INTERRUPTS IS VERY IMPORTANT TO THE SYSTEM OPERATION AND SHOULD BE ESTABLISHED EARLY IN THE SYSTEM DEVELOPMENT PROCESS. tHE mcs650x-BASED SYSTEM CAN EMPLOY SEVERAL HARDWARE METHODS OF DETERMINING THE HIGHEST PRIORITY ACTIVE INTERRUPT. tHESE USUALLY INVOLVE USING A SPECIAL "PRIORITY ENCODER" WHICH ALLOWS THE PROCESSOR TO GO DI- RECTLY TO THE SOFTWARE WHICH SERVICES THE HIGHEST PRIORITY INTERRUPT. aFTER THIS IS COMPLETE, IT WILL GO TO THE NEXT HIGHER PRIORITY AND EXECUTE THAT SOFTWARE. hOWEVER, THE mcs650x FAMILY PROVIDES A MUCH LESS EXPENSIVE METHOD OF INTERRUPT PRIORITIZING. tHIS IS THE "POLLED" INTERRUPT. wITH THIS TECHNIQUE, EACH TIME AN ACTIVE INTERRUPT SOURCE IS DETECTED, THE PRO- CESSOR EXECUTES A "POLLED" INTERRUPT PROGRAM THAT INTERROGATES THE HIGHEST PRIORITY INTERRUPT, THEN THE NEXT HIGHEST AND SO ON UNTIL AN ACTIVE INTER- RUPT IS LOCATED. tHE PROGRAM SERVICES THAT INTERRUPT AND RETURNS TO THE "POLLED" INTERRUPT PROGRAM AND CONTINUES TO INTERROGATE THE NEXT HIGHEST PRIORITY INTERRUPT UNTIL ALL HAVE BEEN INTERROGATED OR CLEARS THE INTERRUPT DISABLE TO ALLOW NESTED INTERRUPTS. tHE "POLLED" INTERRUPT PROGRAM IS AL- WAYS EXECUTED WHEN AN INTERRUPT OCCURS SO THAT ALL INTERRUPTS THAT OCCUR CONCURRENTLY WILL BE SERVICED IN ORDER OF PRIORITY LEVEL. sEVERAL HARDWARE TECHNIQUES FOR PRIORITIZING INTERRUPTS ARE DIS- CUSSED IN cHAPTER 2 OF THIS MANUAL. tHE NEXT SECTION, HOWEVER, DESCRIBES THE SYSTEM INTERCONNECT WHICH ALLOWS USE OF THE SIMPLE "POLLED" INTERRUPT. 1.3.2.3 sYSTEM iNTERCONNECT FOR iNTERRUPTS iN THE SIMPLE "POLLED" INTERRUPT TECHNIQUE FOR PRIORITIZING INTER- RUPTS, THE INTERRUPT SOFTWARE ACTUALLY DETERMINES THE HIGHEST PRIORITY ACTIVE INTERRUPT. tHE irq OR nmi INTERRUPT REQUEST SIGNALS SIMPLY CAUSE THE PROCESSOR TO JUMP TO THE POLLING SOFTWARE. fOR THIS REASON, IT IS POSSIBLE TO "or" THE VARIOUS INTERRUPT SIGNALS TOGETHER TO FORM THE SIGNAL FOR THE PROCESSOR. aNY ACTIVE INTER- RUPT SOURCE WILL THEN CAUSE THE PROCESSOR TO DO THE INTERRUPT POLLING AND -22- ============================================================================ SERVICING OPERATION. pROVISION FOR GENERATION OF THIS or FUNCTION IS PRO- VIDED IN THE mcs6500 FAMILY PERIPHERAL INTERFACE DEVICES. sINCE THESE PERIPHERAL ADAPTERS PERFORM MANY OF THE ENABLING AND LATCHING FUNCTIONS NECESSARY FOR PROPER INTERRUPT SERVICING, THE PERIPHERAL ADAPTOR INTERRUPT OUTPUT THEN PROVIDES THE ACTUAL SIGNAL WHICH INTERRUPTS THE PROCESSOR. tHESE INTERRUPT OUTPUTS CAN BE "wire-or'D" BY CONNECTING THEM ALL TOGETHER AND THEN CONNECTING THIS SINGLE LINE TO THE PROCESSOR. tHIS INPUT SHOULD THEN BE PULLED TO +5v WITH A RESISTOR. aNY ONE OF THE INTERRUPT OUTPUTS ON THE PERIPHERAL ADAPTORS CAN THEN PULL THIS INTERRUPT LOW. tHIS SIMPLE CONFIGURATION IS SHOWN IN fIGURE 1.9. 1.3.2.4 iNTERRUPT sERVICING aLTHOUGH A GREAT DEAL HAS BEEN SAID PREVIOUSLY ABOUT THE PROCESS OF ESTABLISHING INTERRUPTS AND DETERMINING JUST WHAT HAPPENS IN RESPONSE TO AN INTERRUPT, IT WOULD BE USEFUL TO DETAIL THE SEQUENCE WHICH TAKES PLACE WHEN AN INTERRUPT IS RECOGNIZED BY THE PROCESSOR. tHIS WILL ESTABLISH A BASIS FOR UNDERSTANDING OF THE DETAILS OF THE PROCESSOR INTERRUPT INPUTS. aN INTERRUPT REQUEST IS SIGNALED BY A gnd (< 0.4V) SIGNAL ON THE INTERRUPT REQUEST INPUT. tHIS INTERRUPT WILL BE RECOGNIZED AFTER THE PRO- CESSOR COMPLETES THE INSTRUCTION WHICH IT IS CURRENTLY EXECUTING. tHE NEXT STEP IS TO STORE ENOUGH OF THE CONTENTS OF THE INTERNAL PROCESSOR REGISTERS TO ASSURE THAT THE PROCESSOR CAN RESUME EXECUTION OF THE PROGRAM WHICH WAS INTERRUPTED. iN PARTICULAR, THE pROGRAM cOUNTER AND THE pROCESSOR sTATUS rEGISTER ARE STORED IN A SERIES OF MEMORY LOCATIONS SPECIFIED BY ANOTHER INTERNAL REGISTER, THE sTACK pOINTER. aS DISCUSSED IN cHAPTER 9 OF THE pROGRAMMING mANUAL, SAVING THE CONTENTS OF THE pROGRAM cOUNTER AND pROCES- SOR sTATUS REGISTER UNIQUELY DEFINES, IN MEMORY, THE STATE OF THE MICRO- PROCESSOR AT THE TIME THE INTERRUPT OCCURRED. tHE PROCESSOR THEN GOES TO TWO FIXED LOCATIONS IN MEMORY TO DETERMINE THE ADDRESS LOW AND ADDRESS HIGH OF THE INTERRUPT SOFTWARE. tHE OPERATION TO THIS POINT IS AUTOMATIC AND IS DETERMINED BY THE INTERNAL PROCESSOR LOGIC. aFTER THE PROCESSOR HAS PROPERLY SET THE ADDRESS BUS, EXECUTION OF THE INTERRUPT PROGRAM COMMENCES. eVERYTHING WHICH OCCURS SUBSEQUENTLY IS DETERMINED BY THE SYSTEM SOFTWARE. tHE TOTAL INTERRUPT SOFTWARE DESCRIBED ABOVE WILL CONSIST OF A COM- PLEX COMBINATION OF POLLING AND INTERRUPT SERVICING ROUTINES. hOWEVER, UNLESS -23- ============================================================================ +5v o {$7c} -+- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -+- ------------- {$7c} ------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} \ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} mcs650x {$7c}<-----O----->{$7c} mcs6520 +==> {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ------------- {$7c} ------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} O----->{$7c} mcs6520 +==> > i/o ports {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} O----->{$7c} mcs6520 +==> {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} / {$7c} {$7c} {$7c} {$7c} ------------- {$7e} \______ _______/ \/ peripheral interface devices iNTERRUPT wIRE or 'D hARDWARE cONFIGURATION FROM pERIPHERAL iNTERFACE dEVICES TO mICROPROCESSOR figure 1.9 -24- ============================================================================ A HARDWARE PRIORITIZING SCHEME IS USED, THE ACTUAL SYSTEM INTERCONNECTIONS WILL NOT BECOME ANY MORE COMPLEX THAN THAT SHOWN IN fIGURE 1.9. ___ 1.3.2.5 iNTERRUPT rEQUEST (irq) aS STATED IN sECTION 1.3.2, THE TWO INTERRUPT LINES FOR THE MICRO- PROCESSOR ARE irq AND nmi. tHE REQUIREMENTS FOR PROPER OPERATION OF THE MASKABLE iNTERRUPT rEQUEST INPUT (irq) ARE MORE STRINGENT THAN FOR THE SECOND INTERRUPT INPUT, nmi. tHIS IS DUE PRIMARILY TO THE FACT THAT nni IS EDGE-SENSITIVE. wITH THE irq INPUT, THE PROCESSOR WILL BE INTERRUPTED ANY TIME THE SIGNAL ON irq IS gnd (< 0.4V) AND THE INTERNAL iNTERRUPT dIS- ABLE FLAG IS CLEARED. tHE iNTERRUPT dISABLE FLAG (i) IS A SINGLE BIT IN THE INTERNAL pROCESSOR sTATUS rEGISTER. tHE DETAILS OF THIS REGISTER ARE DESCRIBED IN sECTION 3.2 OF THE pROGRAMMING mANUAL. iN THE PROCESSING OF INTERRUPT REQUEST FROM THE irq INPUT, THE i FLAG IS EXTREMELY IMPORTANT. tHIS IS THE ELEMENT WHICH ASSURES THAT AN INTERRUPT WILL BE RECOGNIZED AND SERVICED ONLY ONCE FOR EACH REQUEST AND ONLY WHEN AN INTERRUPT IS DESIRED. tHIS IS DESCRIBED IN DETAIL BELOW. fIGURE 1.10 DETAILS THE SEQUENCE OF OPERATIONS WHICH SHOULD TAKE PLACE DURING THE SERVICING OF AN irq INTERRUPT. a POSITIVE OR NEGATIVE TRANSITION OF THE SIGNAL FROM THE PERIPHERAL DEVICE (PRINTER, KEYBOARD, ETC.) IS DETECTED ON THE EDGE-SENSITIVE INPUTS TO THE PERIPHERAL INTERFACE DEVICE. iF THE INTERRUPT IS ENABLED WITHIN THE PERIPHERAL INTERFACE DE- VICE, THE INTERRUPT REQUEST OUTPUT (irq) ON THIS CHIP WILL GO LOW. tHE INTERRUPT CONDITION IS LATCHED WITHIN THE PERIPHERAL INTERFACE DEVICE TO ALLOW SUFFICIENT TIME FOR THE PROCESSOR TO POLL THE INTERRUPT SOURCES, ASSURING THAT THE INTERRUPT SIGNAL WILL NOT BE CLEARED BEFORE THE POLLING CAN BE COMPLETED. tHIS LATCH IS RESET BY THE PROCESSOR AS IT EXECUTES THE SOFTWARE ASSOCIATED WITH THAT INTERRUPT. dETAILS OF THIS OPERATION ARE DESCRIBED IN sECTION 1.4.1.2.10 tHE iNTERRUPT dISABLE FLAG (i) IS SET AUTOMATICALLY WHEN THE PRO- CESSOR RECOGNIZES AN INTERRUPT. tHIS ASSURES THAT THIS SAME INTERRUPT WILL NOT BE RECOGNIZED AGAIN. rESETTING THIS FLAG CAN BE PERFORMED MANUALLY WITH AN INSTRUCTION IN THE PROGRAM OR AUTOMATICALLY WITH A "rETURN FROM iNTERRUPT" INSTRUCTION. iT IS VERY IMPORTANT THAT "i" NOT BE CLEARED BEFORE THE INTERRUPT INPUT IS RESET. pERFORMING THE "cLEAR i" INSTRUCTION TOO EARLY IN THE PROGRAM CAN CAUSE THIS SAME INTERRUPT TO BE RECOGNIZED AGAIN. -25- ============================================================================ ------------------ --------- 2.4v irq {$7c} {$7c} from perifheral interface {$7c} {$7c} device to microprocessor {$7c} {$7c} -------------------------------------- 0.4v {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ----------------------------------- {$7c} {$7c} {$7c} {$7c} interrupt {$7c} {$7c} {$7c} {$7c} flag(i) {$7c} {$7c} {$7c} {$7c} -------------------------- {$7c} ---- {$7c} {$7c} {$7c} / / / / / / / / / / / {$7c} ________________/ / {$7c} / / {$7c} / / {$7c} / / {$7c} / / {$7c} / / {$7c} interrupt request interrupt flag (i) is set high and upon completion of recognized after the interrupt request IS serviced interrupt routine irq completion of current by the mpu should be reset before mpU instruction. 'i' is reset to avoid double interrupting. sEQUENCE TO sERVICE irq figure 1.10 -26- ============================================================================ tHE PROCESSOR WILL THEN PROCEED TO SERVICE THIS AS IF IT WERE A NEW INTER- RUPT. ___ 1.3.2.6 nON-mASKABLE iNTERRUPT (nmi) tHE nmi INPUT TO THE PROCESSOR IS EDGE-SENSITIVE. tO CAUSE AN INTERRUPT TO OCCUR, THERE MUST BE A NEGATIVE TRANSITION OF THE SIGNAL ON THE nmi INPUT. tHIS NEGATIVE TRANSITION WILL CAUSE A SINGLE INTERRUPT TO OCCUR. aFTER SERVICING THE INTERRUPT, THE PROCESSOR WILL IGNORE THIS INPUT UNTIL THE nmi SIGNAL GOES HIGH (> +2.4V) AND THEN BACK TO GROUND. tHE RESPONSE TO AN nmi INTERRUPT SIGNAL CANNOT BE DISABLED WITHIN THE PROCESSOR. aFTER THE PROCESSOR COMPLETES THE INSTRUCTION BEING EXE- CUTED, IT WILL RECOGNIZE THE INTERRUPT AND WILL PROCEED TO SERVICE THE INTERRUPT AS DESCRIBED IN THE PREVIOUS SECTION. tHE PROPER DISCIPLINE TO EMPLOY IN ALL INTERRUPTS IS FOR THE INTERRUPT SIGNAL TO BE LATCHED UNTIL THE PROCESSOR COMPLETES SERVICING THE INTERRUPT. tHIS METHOD OF OPERATION IS ASSURED IF ALL THE INTERRUPTS ARE CONNECTED TO THE INTERRUPT INPUTS OF THE PERIPHERAL INTERFACE DEVICES IN THE FAMILY. pROCESSING OF MULTIPLE INTERRUPTS IN A POLLED INTERRUPT STRUCTURE REQUIRES THAT ALL OF THE INTERRUPTS BE POLLED BEFORE EXECUTING A "rETURN FROM iNTERRUPT" INSTRUCTION. tHIS IS NECESSITATED BY THE "wire-or" TECH- NIQUE FOR COMBINING THE INTERRUPTS, SINCE NO KNOWLEDGE EXISTS OF WHICH LINE WENT TO GROUND. iF ONE OF THE INTERRUPTS IS LEFT UNSERVICED, IT WILL HOLD THE nmi SIGNAL TO GROUND, DISABLING THE INTERRUPTS FROM ALL OTHER SOURCES SINCE IT IS NECESSARY FOR THE nmi SIGNAL TO GO HIGH (> 2.4V) AND BACK LOW AGAIN FOR AN INTERRUPT TO OCCUR. tHIS IS NOT TRUE FOR THE irq INPUT SINCE THIS LATCH IS LEVEL-SENSITIVE. pERFORMING A "rETURN FROM iNTERRUPT" BEFORE ALL irq INTERRUPT SOURCES ARE SERVICED WILL SIMPLY CAUSE ANOTHER irq INTER- RUPT TO OCCUR. 1.3.3 sYSTEM rESET oNE OF THE BASIC SYSTEM CONTROL FUNCTIONS IS THE SYSTEM reset SIGNAL. wHETHER THIS SIGNAL IS GENERATED AUTOMATICALLY BY EXTERNAL POWER-ON CIRCUITRY OR MANUALLY FROM A PUSH-BUTTON SWITCH, THE SYSTEM COMPONENTS MUST OBEY A FIXED SET OF RULES TO ASSURE PROPER SYSTEM OPERATION. tHIS IS PARTICULARLY TRUE FOR THE PERIPHERAL INTERFACE DEVICES. -27 ============================================================================ iN THE mcs650x-BASED SYSTEMS, AN ASSUMPTION IS MADE THAT reset PINS ON ALL PERIPHERAL INTERFACE DEVICES AND ON THE PROCESSOR WILL BE HELD LOW DURING POWER-ON UNTIL THE SUPPLY VOLTAGES AND THE CLOCKS HAVE STABILIZED. tHIS PROCEDURE ASSURES THAT THE PERIPHERAL PINS WILL REMAIN IN A KNOWN STATE UNTIL THE ENTIRE SYSTEM IS INITIALIZED AND THE PROCESSOR IS READY TO ASSUME CONTROL OF THE OUTPUT LINES, I.E., IS READY TO RUN THE SYSTEM PRO- GRAM. iT SHOULD BE MENTIONED THAT IN THE ENTIRE SET OF MICROCOMPUTER CHIPS, THE CONTENTS OF LATCHES, REGISTERS, ETC. IS TOTALLY RANDOM AFTER POWER IS APPLIED. oN THE PERIPHERAL OUTPUT PINS, RANDOM DATA CAN BE DISASTROUS. tHE ONLY WAY TO FORCE THESE LINES TO A KNOWN CONDITION IS TO APPLY THE reset SIGNAL. tHE DESIGNER CAN THEN MAKE SURE THAT THE KNOWN CONDITION WILL NOT CAUSE SPURIOUS OPERATIONS IN THE PERIPHERAL DEVICES. tHE EFFECT OF reset ON THE PERIPHERAL CHIPS IS DISCUSSED IN THE ANALYSIS OF EACH CHIP. iN THE PROCESSOR, THE SINGLE REGISTER WHICH MUST BE PLACED IN A KNOWN STATE IS THE PROGRAM COUNTER. tHIS IS THE REGISTER WHICH SE- LECTS THE INSTRUCTIONS TO BE EXECUTED. tHE reset INPUT CAUSES THE PROGRAM COUNTER TO GO TO THE FIRST INSTRUCTION IN THE SYSTEM PROGRAM. tHE SPECIFIC DETAILS OF THIS OPERATION ARE DISCUSSED IN sECTION 1.4.1.2.11. tHERE IS ONE OTHER VERY IMPORTANT FUNCTION PERFORMED BY THE reset INPUT ON THE PERIPHERAL INTERFACE DEVICES. aLTHOUGH THE RECOGNITION OF THE PROCESSOR INTERRUPT SIGNALS IS AUTOMATIC AND DOES NOT DEPEND ON SOFTWARE, THE SEQUENCE OF OPERATIONS PERFORMED BY THE PROCESSOR TO TOTALLY SERVICE AN INTERRUPT IS DETERMINED BY THE PROGRAM. uNTIL THE VARIOUS INTERNAL REGIS- TERS IN THE PROCESSOR HAVE BEEN INITIALIZED, THE PROCESSOR IS NOT READY TO RESPOND PROPERLY TO ANY EXTERNAL INTERRUPTS. fOR THIS REASON, IT IS IM- PORTANT THAT THE SYSTEM reset DISABLE ALL EXTERNAL INTERRUPT SIGNALS UNTIL THEY ARE ENABLED BY THE PROCESSOR. tHE PROGRAMMER CAN THEN MAKE SURE THAT THE SYSTEM HAS BEEN PROPERLY INITIALIZED BEFORE THE INTERRUPTS ARE ENABLED. -28- ============================================================================ pICTURE OF INTERNAL ARCHITECTURE OF A 650x WHICH CAN BE FOUND IN ANY GOOD DATABOOK mcs650x iNTERNAL aRCHITECTURE gIGURE 1.11 -29- ============================================================================ 1.4 the microprocessors 1.4.1 tHE mcs6501 1.4.1.1 iNTRODUCTION tHE MEMBERS OF THE mcs650x MICROPROCESSOR FAMILY CONTAIN VERY SIMILAR INTERNAL ARCHITECTURES. a BLOCK DIAGRAM OF THIS ARCHITECTURE IS SHOWN IN fIGURE 1.11. tHIS SECTION BEGINS WITH AN ANALYSIS OF THIS BLOCK DIAGRAM, DISCUSSING THE FUNCTION OF THE VARIOUS REGISTERS, DATA PATHS, ETC. a DETAILED DISCUSSION OF THE OPERATION OF THE VARIOUS PINS ON THE CHIP FOL- LOWS. tHE INTERNAL ORGANIZATION OF THE PROCESSOR CAN BE SPLIT INTO TWO SECTIONS. iN GENERAL, THE INSTRUCTIONS OBTAINED FROM PROGRAM MEMORY ARE EXECUTED BY IMPLEMENTING A SERIES OF DATA TRANSFERS IN ONE SECTION OF THE CHIP (REGISTER SECTION). tHE CONTROL LINES WHICH ACTUALLY CAUSE THE DATA TRANSFERS TO TAKE PLACE ARE GENERATED IN THE OTHER SECTION (CONTROL SECTION). iNSTRUCTIONS ENTER THE PROCESSOR ON THE DATA BUS, ARE LATCHED INTO THE INSTRUCTION REGISTER, AND ARE THEN DECODED ALONG WITH TIMING SIG- NALS TO GENERATE THE REGISTER CONTROL SIGNALS. tHE TIMING CONTROL UNIT KEEPS TRACK OF THE SPECIFIC CYCLE BEING EXECUTED. tHIS UNIT IS SET TO "t0" FOR EACH INSTRUCTION FETCH CYCLE AND IS ADVANCED AT THE BEGINNING OF EACH pHASE oNE CLOCK PULSE. eACH INSTRUC- TION STARTS IN t0 AND GOES TO t1, t2, t3, ETC. FOR AS MANY CYCLES AS ARE REQUIRED TO COMPLETE EXECUTION OF THE INSTRUCTION. eACH DATA TRANSFER, ETC., WHICH TAKES PLACE IN THE REGISTER SECTION IS CAUSED BY DECODING THE CONTENTS OF BOTH THE INSTRUCTION REGISTER AND THE TIMING COUNTER. aDDITIONAL CONTROL LINES WHICH AFFECT THE EXECUTION OF THE INSTRUC- TIONS ARE DERIVED FROM THE iNTERRUPT LOGIC AND FROM THE pROCESSOR sTATUS REGISTER. tHE iNTERRUPT LOGIC CONTROLS THE PROCESSOR INTERFACE TO THE INTERRUPT INPUTS TO ASSURE PROPER TIMING, ENABLING, SEQUENCING, ETC. WHICH THE PROCESSOR RECOGNIZES AND SERVICES. tHE pROCESSOR sTATUS REGISTER CONTAINS A SET OF LATCHES WHICH SERVE TO CONTROL CERTAIN ASPECTS OF THE PROCESSOR OPERATION, TO INDICATE THE RESULTS OF PROCESSOR ARITHMETIC AND LOGIC OPERATIONS, AND TO INDICATE THE STATUS OF DATA EITHER GENERATED BY THE PROCESSOR OR TRANSFERRED INTO THE PROCESSOR FROM OUTSIDE. sINCE THE REAL WORK OF THE PROCESSOR IS CARRIED ON IN THE REGISTER SECTION OF THE CHIP, A DETAILED STUDY WILL BE MADE OF THIS SECTION. tHE COMPONENTS ARE: -30- ============================================================================ * dATA bUS bUFFERS * iNPUT dATA lATCH (dl) * pROGRAM cOUNTER (pcl, pch) * aCCUMULATOR (a) * aRITHMETIC lOGIC uNIT (alu) * sTACK pOINTER (s) * iNDEX rEGISTERS (x, y) * aDDRESS bUS lATCHES (abl, abh) * pROCESSOR sTATUS rEGISTER (p) aT 1 mhZ, THE DATA WHICH COMES INTO THE PROCESSOR FROM THE PROGRAM MEMORY, THE DATA MEMORY, OR FROM PERIPHERAL DEVICES, APPEARS ON THE DATA BUS DURING THE LAST 100 NANOSECONDS OF pHASE tWO. nO ATTEMPT IS MADE TO ACTUALLY OPERATE ON THE DATA DURING THIS SHORT PERIOD. iNSTEAD, IT IS SIMPLY TRANSFERRED INTO THE INPUT DATA LATCH FOR USE DURING THE NEXT CYCLE. tHE DATA LATCH SERVES TO TRAP THE DATA ON THE DATA BUS DURING EACH pHASE tWO PULSE. iT CAN THEN BE TRANSFERRED ONTO ONE OF THE INTERNAL BUSSES AND FROM THERE INTO ONE OF THE INTERNAL REGISTERS. fOR EXAMPLE, DATA BEING TRANSFERRED FROM MEMORY INTO THE ACCUMULATOR (a) WILL BE PLACED ON THE IN- TERNAL DATA BUS AND WILL THEN BE TRANSFERRED FROM THE INTERNAL DATA BUS INTO THE ACCUMULATOR. iF AN ARITHMETIC OR LOGIC OPERATION IS TO BE PER- FORMED USING THE DATA FROM MEMORY AND THE CONTENTS OF THE ACCUMULATOR, DATA IN THE INPUT DATA LATCH WILL BE TRANSFERRED ONTO THE INTERNAL DATA BUS AS BEFORE. fROM THERE IT WILL BE TRANSFERRED INTO THE alu. aT THE SAME TIME THE CONTENTS OF THE ACCUMULATOR WILL BE TRANSFERRED ONTO A BUS IN THE REG- ISTER SECTION AND FROM THERE INTO THE SECOND INPUT TO THE alu. tHE RESULTS OF THE ARITHMETIC OR LOGIC OPERATION WILL BE TRANSFERRED BACK TO THE ACCUMU- LATOR ON THE NEXT CYCLE BY TRANSFERRING FIRST ONTO THE BUS AND THEN INTO THE ACCUMULATOR. aLL OF THESE DATA TRANSFERS TAKE PLACE DURING THE pHASE oNE CLOCK PULSE. tHE PROGRAM COUNTER (pcl, pch) PROVIDES THE ADDRESSES WHICH STEP THE PROCESSOR THROUGH SEQUENTIAL INSTRUCTIONS IN THE PROGRAM. eACH TIME THE PROCESSOR FETCHES AN INSTRUCTION FROM PROGRAM MEMORY, THE CONTENTS OF pcl IS PLACED ON THE LOW ORDER EIGHT BITS OF THE ADDRESS BUS AND THE CON- TENTS OF pch IS PLACED ON THE HIGH ORDER EIGHT BITS. tHIS COUNTER IS INCREMENTED EACH TIME AN INSTRUCTION OR DATA IS FETCHED FROM PROGRAM MEMORY. -31- ============================================================================ tHE ACCUMULATOR IS A GENERAL PURPOSE 8-BIT REGISTER WHICH STORES THE RESULTS OF MOST ARITHMETIC AND LOGIC OPERATIONS. iN ADDITION, THE ACCU- MULATOR USUALLY CONTAINS ONE OF THE TWO DATA WORDS USED IN THESE OPERATIONS. aLL LOGIC AND ARITHMETIC OPERATIONS TAKE PLACE IN THE alu. tHIS INCLUDES INCREMENTING AND DECREMENTING OF INTERNAL REGISTERS (EXCEPT pcl AND pch). hOWEVER, THE alu CANNOT STORE DATA FOR MORE THAN ONE CYCLE. iF DATA IS PLACED ON THE INPUTS TO THE alu AT THE BEGINNING OF ONE CYCLE, THE RESULT IS ALWAYS GATED INTO ONE OF THE STORAGE REGISTERS OR TO EXTERNAL MEMORY DURING THE NEXT CYCLE. eACH BIT OF THE alu HAS TWO INPUTS. tHESE INPUTS CAN BE TIED TO VARIOUS INTERNAL BUSSES OR TO A LOGIC ZERO; THE alu THEN GENERATES THE sum, and, or, ETC. FUNCTION USING THE DATA ON THE TWO INPUTS. tHE STACK POINTER (s) AND THE TWO INDEX REGISTERS (x AND y) EACH CONSIST OF 8 SIMPLE LATCHES. tHESE REGISTERS STORE DATA WHICH IS TO BE USED IN CALCULATING ADDRESSES IN DATA MEMORY. tHE SPECIFIC OPERATION OF EACH OF THESE IS DISCUSSED IN DETAIL IN THE pROGRAMMING mANUAL. tHE ADDRESS BUS BUFFERS (abl, abh) CONSIST OF A SET OF LATCHES AND ttl COMPATIBLE DRIVERS. tHESE LATCHES STORE THE ADDRESSES WHICH ARE USED IN ACCESSING THE PERIPHERAL DEVICES (rom, ram, AND i/o). 1.4.1.2 tHE mcs6501 pINOUTS fIGURE 1.12 SHOWS A DIAGRAM OF THE mcs6501 MICROPROCESSOR WITH THE VARIOUS PINS DESIGNATED. tHESE PINS AND THEIR USE IN MICROCOMPUTER SYSTEMS ARE DISCUSSED SEPARATELY BELOW. 1.4.1.2.1 vCC, vSS--sUPPLY lINES tHE vCC AND vSS PINS ARE THE ONLY POWER SUPPLY CONNECTIONS TO THE CHIP. tHE SUPPLY VOLTAGE ON PIN 8 IS +5.0 v dc + 5%. tHE ABSOLUTE LIMIT ON THE vCC INPUT IS +7.0 v dc. 1.4.1.2.2 ab00-abL5--aDDRESS bUS tHE ADDRESS BUS BUFFERS ON THE mcs650x FAMILY OF MICROPROCESSORS ARE PUSH/PULL TYPE DRIVERS CAPABLE OF DRIVING AT LEAST 130 PF AND 1 STAN- DARD ttl LOAD. tHE ADDRESS BUS WILL ALWAYS CONTAIN KNOWN DATA AS DETAILED IN aPPENDIX a. tHE ADDRESSING TECHNIQUE INVOLVES PUTTING AN ADDRESS ON THE ADDRESS BUS WHICH IS KNOWN TO BE EITHER IN PROGRAM SEQUENCE, ON THE SAME -32- ============================================================================ --------------------------- ___ vss ---+ 1 40+---<------ res ---+ +--- rdy ------>---+ 2 39+--- n.c. ---+ +--- p1 (in) ------>---+ 3 38+---<------ n.c ___ ---+ +--- irq ------>---+ 4 37+---<------ p2 (in) ---+ +--- vma <---------+ 5 36+---<------ dbe ___ ---+ +--- nmi ------>---+ 6 35+--- n.c. ---+ +--- ba <---------+ 7 34+---------> r/w ---+ +--- vcc ---+ 8 33+---\ db0 ---+ +--- {$7c} ab0 /---+ 9 32+--- {$7c} db1 {$7c} ---+ +--- {$7c} ab1 {$7c} ---+10 31+--- {$7c} db2 {$7c} ---+ mcs6501 +--- {$7c} ab2 {$7c} ---+11 30+--- {$7c} db3 {$7c} ---+ +--- >---> ab3 {$7c} ---+12 29+--- {$7c} db4 {$7c} ---+ +--- {$7c} ab4 {$7c} ---+13 28+--- {$7c} db5 {$7c} ---+ +--- {$7c} ab5 {$7c} ---+14 27+--- {$7c} db6 <---< ---+ +--- {$7c} ab6 {$7c} ---+15 26+--- {$7c} db7 {$7c} ---+ +---/ ab7 {$7c} ---+16 25+---\ ab15 {$7c} ---+ +--- {$7c} ab8 {$7c} ---+17 24+--- {$7c} ab14 {$7c} ---+ +--- >---> ab9 {$7c} ---+18 23+--- {$7c} ab13 {$7c} ---+ +--- {$7c} ab10 {$7c} ---+19 22+--- {$7c} ab12 {$7c} ---+ +---/ ab11 {$7c} ---+20 21+--- vss \---+ +--- --------------------------- n.c. = no connection * vma is connected internally to vcc. the vma signal is not required on the mcs6501 as on the mc6800, since the mcs6501 always puts out known addresses on the address bus. mcs6501 pINOUT dESIGNATIONS figure 1.12 -33- ============================================================================ PAGE IN PROGRAM MEMORY OR AT A KNOWN POINT IN ram. a BRIEF STUDY OF aPPEN- DIX a WILL ACQUAINT THE DESIGNER WITH THE DETAILED OPERATION OF THIS BUS. tHE VARIOUS PROCESSORS DIFFER SOMEWHAT IN THE NUMBER OF ADDRESS LINES PROVIDED. iN PARTICULAR, THE mcs6504 PROVIDES THIRTEEN ADDRESS LINES (ab00 - ab12) AND THE mcs6503 AND mcs6505 PROVIDE TWELVE (ab00 - ab11). aS A RESULT, THE mcs6504 CAN ADDRESS 8,192 BYTES OF MEMORY AND THE mcs6503 AND mcs6505 CAN ADDRESS 4,096 BYTES. tHIS TOTAL ADDRESS SPACE SHOULD PROVE TO BE MORE THAN SUFFICIENT FOR THE SMALL, COST-SENSITIVE SYSTEMS WHERE THESE DEVICES SHOULD FIND THEIR GREATEST APPLICATION. tHE SPECIFIC TIMING OF THE ADDRESS BUS IS EXACTLY THE SAME FOR ALL THE PROCESSORS. tHE ADDRESS IS VALID 300 NS (AT 1 mhZ CLOCK RATE) INTO THE O1 CLOCK PULSE AND STAYS STABLE UNTIL THE NEXT O1 PULSE. tHIS SPECIFI- CATION WILL ONLY CHANGE FOR PROCESSORS WHICH ARE SPECIFIED TO OPERATE AT A HIGHER CLOCK RATE. fIGURE 1.13 DETAILS THE RELATION OF ADDRESS BUS TO OTHER CRITICAL SIGNALS. bECAUSE OF THE REDUCED NUMBER OF ADDRESS LINES ON THE 28-PIN PROCESSORS, IT IS POSSIBLE TO WRITE A PROGRAM WHICH ATTEMPTS TO ACCESS NON- EXISTENT MEMORY ADDRESS SPACE, I.E., THE ADDRESS BITS 13, 14, OR 15 SET TO LOGIC "1." tHESE UPPER ADDRESS BITS IN THE PROGRAM WILL BE IGNORED AND THE PROGRAM WILL DROP INTO EXISTING ADDRESS SPACE. tHIS ASSUMES PROPER MEMORY MANAGEMENT WHEN USING DEVICES OF LARGE ADDRESSING CAPABILITY SUCH THAT THE ADDRESSED MEMORY SPACE WILL FIT WITHIN THE CONSTRAINTS OF A DEVICE WITH SMALLER AVAILABLE MEMORY ADDRESSING CAPABILITY. 1.4.1.2.3 dbo-db7--dATA bUS tHE PROCESSOR DATA BUS IS EXACTLY THE SAME FOR THE PROCESSORS CURRENTLY AVAILABLE AND FOR THE SOFTWARE-COMPATIBLE PROCESSORS WHICH WILL BE INTRODUCED IN THE NEAR FUTURE. aLL INSTRUCTIONS AND DATA TRANSFERS BE- TWEEN THE PROCESSOR AND MEMORY TAKE PLACE ON THESE LINES. tHE BUFFERS DRIV- ING THE DATA BUS LINES HAVE FULL "THREE-STATE" CAPABILITY. tHIS IS NECES- SITATED BY THE FACT THAT THE LINES ARE BI-DIRECTIONAL. eACH DATA BUS PIN IS CONNECTED TO AN INPUT AND AN OUTPUT BUFFER, WITH THE OUTPUT BUFFER REMAINING IN THE "FLOATING" CONDITION EXCEPT WHEN THE PROCESSOR IS TRANSFERRING DATA INTO OR OUT OF ONE OF THE SUPPORT CHIPS. aLL INTER-CHIP DATA TRANSFERS TAKE PLACE DURING THE pHASE tWO CLOCK PULSE. dURING pHASE oNE THE ENTIRE DATA BUS IS "FLOATING." -34- ============================================================================ pERSONAL NOTE: VERY VAGUE TIMING DIAGRAM. bETTER CHECK A GOOD DATASHEET. mcs650x sYSTEM tIMONG dIAGRAM figure 1.13 -35- ============================================================================ tHE DATA BUS BUFFER IS A PUSH/PULL DRIVER CAPABLE OF DRIVING 130 PF AND 1 STANDARD ttl LOAD AT THE RATED SPEED. aT A 1 mhZ CLOCK RATE, THE DATA ON THE DATA BUS MUST BE STABLE 100 NS BEFORE THE END OF pHASE tWO. tHIS IS TRUE FOR TRANSFERS IN EITHER DIRECTION. fIGURE 1.13 DETAILS THE RELATIONSHIP OF THE DATA BUS TO OTHER SIGNAL& 1.4.1.2.4 r/w--rEAD/wRITE tHE rEAD/wRITE LINE ALLOWS THE PROCESSOR TO CONTROL THE DIREC- TION OF DATA TRANSFERS BETWEEN THE PROCESSOR AND THE SUPPORT CHIPS. tHIS LINE IS HIGH EXCEPT WHEN THE PROCESSOR IS WRITING TO MEMORY OR TO A PERI- PHERAL INTERFACE DEVICE. aLL TRANSITIONS ON THIS LINE OCCUR DURING THE pHASE oNE CLOCK PULSE (CONCURRENT WITH THE ADDRESS LINES). tHIS ALLOWS COMPLETE CONTROL OF THE DATA TRANSITION WHICH TAKES PLACE DURING THE pHASE tWO CLOCK PULSE. tHE r/w BUFFER IS SIMILAR TO THE ADDRESS BUFFERS. tHEY ARE CAPABLE OF DRIVING 130 PF AND ONE STANDARD ttl LOAD AT THE RATED SPEED. aGAIN, fIGURE 1.13 DETAILS THE RELATIVE TIMING OF THE r/w LINE. 1.4.1.2.5 dbe--dATA bUS eNABLE oN THE mcs6501, A DATA BUS ENABLE SIGNAL IS PROVIDED TO ALLOW EXTERNAL ENABLING OF THE DATA BUS. tHIS LINE IS CONNECTED DIRECTLY TO THE pHASE tWO INPUT CLOCK SIGNAL FOR ANY NORMALLY OPERATING SYSTEM AND IS DE- TAILED IN fIGURE 1.13. tHE dbe SIGNAL AFFECTS ONLY THE DATA BUS BUFFERS. iT DOES NOT AFFECT PROCESSOR TIMING AND HAS NO EFFECT ON THE ADDRESS OR THE r/w LINES. tHIS INPUT IS PROVIDED PRIMARILY FOR USE IN SYSTEMS WHICH USE NON-FAMILY DEVICES FOR EITHER THE MEMORY OR THE PERIPHERAL INTERFACE FUNC- TIONS. iN PARTICULAR, IT ALLOWS THE DATA BUS TO BE ENABLED FOR A PERIOD LONGER THAN THE pHASE tWO CLOCK PULSE FOR SYSTEMS REQUIRING GREATER PROCES- SOR HOLD TIME ON THE DATA BUS. tHIS APPLICATION IS COVERED IN GREATER DE- TAIL IN cHAPTER 2. 1.4.1.2.6 vma--vALID mEMORY aDDRESS aS MENTIONED ABOVE, THE mcs650x FAMILY OF MICROPROCESSORS ALWAYS PUTS KNOWN ADDRESSES ON THE ADDRESS BUS AND, AS A RESULT, DOES NOT REQUIRE A vma SIGNAL. hOWEVER, TO REMAIN PIN-COMPATIBLE WITH THE mc6800, THE vma PIN -36- ============================================================================ IS CONNECTED INTERNALLY TO THE vCC POWER SUPPLY. tHIS ASSURES OPERATION IN SYSTEMS IN WHICH vma IS PART OF THE CHIP-SELECT FUNCTION. tHIS PIN IS NOT AVAILABLE ON THE 28-PIN PROCESSORS. 1.4.1.2.7 ba--bUS aVAILABLE tHE BUS AVAILABLE SIGNAL IS PROVIDED ON THE mcs65o1 TO SIGNAL TO A dma CONTROLLER, ETC. THAT THE PROCESSOR IS STOPPED AND THAT THE DATA AND ADDRESS BUSSES CAN BE USED FOR OTHER THAN PROCESSOR PROGRAM EXECUTION. tHIS OPERATION IS SIMILAR TO THAT OF THE mc6800 BUS AVAILABLE SIGNAL EXCEPT THAT MUCH LESS TIME IS REQUIRED TO STOP THE mcs6501 SINCE THE mg6800 REQUIRES COMPLETION OF THE CURRENT INSTRUCTION BEFORE STOPPING. iF NO WRITE OPERATION TAKES PLACE DURING THE CYCLE IN WHICH THE rdy SIGNAL GOES LOW, THE ba WILL GO HIGH (> 2.4V) DURING pHASE tWO OF THE SAME CYCLE. iN GENERAL, ba WILL GO HIGH DURING THE FIRST pHASE tWO PULSE DURING WHICH THE r/w LINE IS HIGH. fOR THE CURRENT PROCESSORS, THE MAXIMUM TIME IS 3-1/2 CYCLES. 1.4.1.2.8 rdy--rEADV tHE rdy INPUT DELAYS EXECUTION OF ANY CYCLE DURING WHICH THE rdy LINE IS PULLED LOW. tHIS LINE SHOULD CHANGE DURING THE pHASE oNE CLOCK PULSE. tHIS CHANGE IS THEN RECOGNIZED DURING THE NEXT pHASE tWO PULSE TO ENABLE OR DISABLE THE EXECUTION OF THE CURRENT INTERNAL MACHINE CYCLE. tHIS EXECUTION NORMALLY OCCURS DURING THE NEXT pHASE oNE CLOCK; TIMING IS SHOWN IN fIGURE 1.13. tHE PRIMARY PURPOSE OF THE rdy LINE IS TO DELAY EXECUTION OF A PROGRAM FETCH CYCLE UNTIL DATA IS AVAILABLE FROM MEMORY. tHIS HAS DIRECT APPLICATION IN PROTOTYPE SYSTEMS EMPLOYING LIGHT-ERASABLE promS OR epromS. bOTH OF THESE DEVICES HAVE RELATIVELY SLOW ACCESS TIMES AND REQUIRE IMPLE- MENTATION OF THE rdy FUNCTION IF THE PROCESSOR IS TO OPERATE AT FULL SPEED. wITHOUT THE rdy FUNCTION A REDUCTION IN THE FREQUENCY OF THE SYSTEM CLOCK WOULD BE NECESSARY. tHE rdy FUNCTION WILL NOT STOP THE PROCESSOR IN A CYCLE IN WHICH A write OPERATION IS BEING PERFORMED. iF THE roy LINE GOES FROM HIGH TO LOW DURING A write CYCLE THE PROCESSOR WILL EXECUTE THAT CYCLE AND WILL THEN STOP IN THE NEXT read CYCLE (r/w = 1). -37- ============================================================================ ___ 1.4.1.2.9 nmi--nON-mASKABLE iNTERRUPT tHE nmi INPUT, WHEN IN THE INTERRUPTED STATE, ALWAYS INTERRUPTS THE PROCESSOR AFTER IT COMPLETES THE INSTRUCTION CURRENTLY BEING EXECUTED. tHIS INTERRUPT IS NOT "MASKABLE," I.E., THERE IS NO WAY FOR THE PROCESSOR TO PREVENT RECOGNITION OF THE INTERRUPT. tHE nmi INPUT RESPONDS TO A NEGATIVE TRANSITION. tO INTERRUPT THE PROCESSOR, THE nmi INPUT MUST GO FROM HIGH (> +2.4v) TO LOW (< +0.4V). iT CAN THEN STAY LOW FOR AN INDEFINITE PERIOD WITHOUT AFFECTING THE PROCESSOR OPERATION AND WITHOUT ANOTHER INTERRUPT. tHE PROCESSOR WILL NOT DETECT ANOTHER INTERRUPT UNTIL THIS LINE GOES HIGH AND THEN BACK TO LOW. tHE nni SIGNAL MUST BE LOW FOR AT LEAST TWO CLOCK CYCLES FOR THE INTERRUPT TO BE RECOGNIZED, WHEREUPON NEW PROGRAM COUNT VECTORS ARE FETCHED. 1.4.1.2.10 irq--iNTERRUPT rEQUEST tHE INTERRUPT REQUEST (irq) RESPONDS IN MUCH THE SAME MANNER AS nmi. hOWEVER, THIS FUNCTION CAN BE ENABLED OR DISABLED BY THE INTERRUPT INHIBIT BIT IN THE PROCESSOR STATUS REGISTER. aS LONG AS THE i FLAG (INTER- RUPT INHIBIT FLAG) IS A LOGIC 1, THE SIGNAL ON THE irq PIN WILL NOT AFFECT THE PROCESSOR. tHE irq PIN IS NOT EDGE-SENSITIVE. iNSTEAD, THE PROCESSOR WILL BE INTERRUPTED AS LONG AS THE i FLAG IS A LOGIC "o" AND THE SIGNAL ON THE irq INPUT IS AT gnd. bECAUSE OF THIS, THE irq SIGNAL MUST BE HELD LOW UN- TIL IT IS RECOGNIZED, I.E., UNTIL THE PROCESSOR COMPLETES THE INSTRUCTION CURRENTLY BEING EXECUTED. iF i IS SET WHEN irq GOES LOW, THE INTERRUPT WILL NOT BE RECOGNIZED UNTIL i IS CLEARED THROUGH SOFTWARE CONTROL. tO ASSURE THAT THE PROCESSOR WILL NOT RECOGNIZE THE INTERRUPT MORE THAN ONCE, THE i FLAG IS SET AUTOMATICALLY DURING THE LAST CYCLE BEFORE THE PROCESSOR BEGINS EXECUTING THE INTERRUPT SOFTWARE, BEGINNING WITH THE FETCH OF PROGRAM COUNT. tHE FINAL REQUIREMENT IS THAT THE INTERRUPT INPUT MUST BE CLEARED BEFORE THE i FLAG IS RESET. iF THERE IS MORE THAN ONE ACTIVE INTERRUPT DRIVING THESE TWO LINES (or'ED TOGETHER), THE RECOMMENDED PRO- CEDURE IS TO SERVICE AND CLEAR BOTH INTERRUPTS BEFORE CLEARING THE i FLAG. hOWEVER, IF THE INTERRUPTS ARE CLEARED ONE AT A TIME AND THE i FLAG IS RE- SET AFTER EACH, THE PROCESSOR WILL SIMPLY RECOGNIZE ANY INTERRUPTS STILL ACTIVE AND WILL PROCESS THEM PROPERLY BUT MORE SLOWLY BECAUSE OF THE TIME REQUIRED TO RETURN FROM ONE INTERRUPT BEFORE RECOGNIZING THE NEXT. iF THE -38- ============================================================================ PROCEDURE RECOMMENDED ABOVE IS FOLLOWED, EACH INTERRUPT WILL BE RECOGNIZED AND PROCESSED ONLY ONCE. fIGURE 1.14 PROVIDES SEVERAL EXAMPLES OF INTER- RUPTS, MICROPROCESSOR RECOGNITION OF EACH INTERRUPT (irq AND nmi), AND PRO- CESSOR SELECTION OF INTERRUPTS DURING OVERLAPPED REQUESTS. -- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- O2 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} --- -{$7e}- --- --- --- -{$7e}- --- --- --- --- -{$7e}- -{$7e}- --- -{$7e}- --- --- -- ___---- ------------------------------- -------- irq 1{$7c} {$7c}3 {$7c}9 {$7c} ------------- --------------- ___---------------------- ------- --------- nmi 5{$7c} {$7c} {$7c}7 {$7c} 12{$7c} --------------- --------- ---------- ------------- ---------- --------- --------- interrupt 2{$7c} 4{$7c} {$7c} {$7c} 8{$7c} 10{$7c} 11{$7c} 13{$7c} mask bit -------- --------- -------- ----- ---- eXAMPLES OFLNTERRUPT rECOGNITION BY mcs650x figure 1.14 eACH MAJOR EVENT AFFECTING THE MICROPROCESSOR IS NUMBERED IN THE FIGURE WITH THE CORRESPONDING EXPLANATIONS BELOW. eVENT nUMBER sYSTEM aCTIVITY ------ --------------- ___ 1. pROCESSOR IS EXECUTING FROM MAIN PROGRAM AND irq GOES TO LOW STATE. 2. uPON COMPLETION OF CURRENT INSTRUCTION, THE PROCESSOR RECOGNIZES THE INTERRUPT, STORES THE CONTENTS OF pc AND p ONTO THE STACK AND THEN SETS i DURING THE FETCH OF THE INTERRUPT VECTOR. ___ 3. aFTER SERVICING THE INTERRUPT, irq SHOULD BE RESET BEFORE RESETTING THE INTERRUPT MASK BIT TO AVOID DOUBLE INTERRUPTING. 4. bEFORE THE PROCESSOR RESUMES NORMAL MAIN PROGRAM EXE- CUTION THE INTERRUPT MASK BIT WILL BE RESET LOW. ___ 5. nmi NOW GOES LOW, SIGNALLING A NON-MASKABLE INTERRUPT REQUEST. -39- ============================================================================ eVENT nUMBER sYSTEM aCTIVITY ------ ___ --------------- 6. tHE nmi INTERRUPT IS RECOGNIZED AND SERVICED IN THE SAME MANNER AS irq. ___ 7. tHE PROCESSOR HAS RESUMED NORMAL OPERATION WHEN nmi AGAIN GOES LOW REQUESTING AN INTERRUPT. 8. tHE INTERRUPT MASK BIT IS SET HIGH IN RESPONSE TO THE nmi REQUEST. ___ 9. hERE irq HAS GONE LOW TO SIGNAL AN INTERRUPT REQUEST. tHIS REQUEST IS IGNORED SINCE THE nmi INTERRUPT IS BEING SERVICED AND THE INTERRUPT MASK IS SET. ___ 10. tHE INTERRUPT MASK BIT IS RESET AFTER SERVICING THE nmi INTERRUPT. ___ 11. tHE PROCESSOR IS NOW ABLE TO RECOGNIZE THE irq SIGNAL, WHICH IS STILL LOW, AND DOES SO BY SETTUIG THE INTER- RUPT MASK BIT. ___ ___ 12. dURING THE SERVICING OF irq, nmi GOES FROM HIGH TO LOW. tHE PROCESSOR THEN COMPLETES THE CURRENT INSTRUCTION AND ABANDONS THE irq INTERRUPT TO SERVICE nmi. nmi IS SERVICED REGARDLESS OF THE STATE OF THE INTERRUPT MASK BIT. ___ 13. aFTER COMPLETING THE nmi INTERRUPT ROUTINE, THE PRO- CESSOR WILL RESUME EXECUTION OF THE irq ROUTINE, EVEN THOUGH irq HAS SUBSEQUENTLY GONE HIGH. ___ 1.4.1.2.11 res--rESET tHE res LINE IS USED TO INITIALIZE THE MICROPROCESSOR FROM A POWER-DOWN CONDITION. dURING THE POWER-UP TIME THIS LINE IS HELD LOW, AND WRITING FROM THE MICROPROCESSOR IS INHIBITED. wHEN THE LINE GOES HIGH, THE MICROPROCESSOR WILL DELAY 6 CYCLES AND THEN FETCH THE NEW PROGRAM COUNT VEC- TORS FROM SPECIFIC LOCATIONS IN MEMORY (pcl FROM LOCATION fffc AND pch FROM LOCATION fffd). tHIS IS THE START OF THE USER'S CODE. iT SHOULD BE ASSUMED THAT ANY TIME THE RESET LINE HAS BEEN PULLED LOW AND THEN HIGH, THE INTERNAL STATES OF THE MACHINE ARE UNKNOWN AND ALL REGISTERS MUST BE RE-INITIALIZED DURING THE RESTART SEQUENCE. tIMING FOR THE RESET SEQUENCE IS SHOWN IN fIGURE 1.13. -40- ============================================================================ 1.4.2 tHE mcs6502 1.4.2.1 pRODUCT cHARACTERISTICS tHE mcs6502 IS VERY SIMILAR TO THE mcs6501 DESCRIBED IN DETAIL IN THE PREVIOUS SECTION. iT PROVIDES A FULL 16-PIN ADDRESS BUS AND THEREFORE ADDRESSES A FULL 65,536 WORDS (*) IN MEMORY. iT ALSO HAS THE SAME DATA BUS, r/w AND rdy AVAILABLE ON THE mcs 6501. fIGURE 1.15 ILLUSTRATES THE PIN CONFIGURATION OF THE mcs6502. tHE DIFFERENCES BETWEEN THE TWO DEVICES ARE AS FOLLOWS: 1. tHE mcs6502 HAS THE OSCILLATOR AND CLOCK DRIVER ON-CHIP, THUS ELIMINATING THE NEED FOR AN EXTERNAL HIGH-LEVEL TWO-PHASE CLOCK GENERATOR. 2. tHE mcs6502 GENERATES A sync SIGNAL INSTEAD OF THE BUS AVAIL- ABLE (ba) SIGNAL. tHE sync SIGNAL IS DESCRIBED IN DETAIL BE- LOW. 3. pIN 5, CORRESPONDING TO THE mc6800 vma SIGNAL, IS NOT CONNEC- TED. 4. tHE INTERNAL DATA BUS ENABLE FUNCTION IS CONNECTED DIRECTLY TO THE PHASE TWO CLOCK ON THE CHIP. tHEREFORE PIN 36 ON THE mcs6502 IS NOT CONNECTED. 1.4.2.2 dEVICE tIMING--rEQUIREMENTS AND gENERATION tHE mcs6501, IN MAINTAINING TOTAL BUS COMPATIBILITY WITH THE mc6800 PRODUCT FAMILY, REQUIRES A 5-VOLT TWO-PHASE CLOCK. tHE mcs6502, HOWEVER, CAN BE USED WITH AN EXTERNALLY GENERATED TIME BASE CONSISTING OF EITHER A ttl LEVEL SINGLE-PHASE CLOCK, CRYSTAL OSCILLATOR OR rc NETWORK. fIGURES 1.16 AND 1.17 SHOW THE CONFIGURATION FOR SETTING THE FRE- QUENCY OF OSCILLATIONS WITH A CRYSTAL OR WITH AN rc NETWORK. fIGURE 1.16 DISPLAYS THE CRYSTAL MODE OF OPERATION IN WHICH THE FREQUENCY OF OSCILLATION IS SET BY THE CRYSTAL OPERATING IN CONJUNCTION WITH THE rc NETWORK. fIGURE 1.17 DISPLAYS THE SAME INTERCONNECTS AS IN THE CRYSTAL MODE OF TIME BASE GENERATION, WITH THE CRYSTAL REMOVED FROM THE -41- ============================================================================ --------------------------- ___ vss ---+ 1 40+---<------ res ---+ +--- rdy ------>---+ 2 39+---------> p2 (out) ---+ +--- p1 (out) <---------+ 3 38+---<------ s.o. ___ ---+ +--- irq ------>---+ 4 37+---<------ p0 (in) ---+ +--- n.c. ---+ 5 36+--- n.c. ___ ---+ +--- nmi ------>---+ 6 35+--- n.c. ---+ +--- sync <---------+ 7 34+---------> r/w ---+ +--- vcc ---+ 8 33+---\ db0 ---+ +--- {$7c} ab0 /---+ 9 32+--- {$7c} db1 {$7c} ---+ +--- {$7c} ab1 {$7c} ---+10 31+--- {$7c} db2 {$7c} ---+ mcs6502 +--- {$7c} ab2 {$7c} ---+11 30+--- {$7c} db3 {$7c} ---+ +--- >---> ab3 {$7c} ---+12 29+--- {$7c} db4 {$7c} ---+ +--- {$7c} ab4 {$7c} ---+13 28+--- {$7c} db5 {$7c} ---+ +--- {$7c} ab5 {$7c} ---+14 27+--- {$7c} db6 <---< ---+ +--- {$7c} ab6 {$7c} ---+15 26+--- {$7c} db7 {$7c} ---+ +---/ ab7 {$7c} ---+16 25+---\ ab15 {$7c} ---+ +--- {$7c} ab8 {$7c} ---+17 24+--- {$7c} ab14 {$7c} ---+ +--- >---> ab9 {$7c} ---+18 23+--- {$7c} ab13 {$7c} ---+ +--- {$7c} ab10 {$7c} ---+19 22+--- {$7c} ab12 {$7c} ---+ +---/ ab11 {$7c} ---+20 21+--- vss \---+ +--- --------------------------- n.c. = no connection mcs6502 pINOUT dESIGNATIONS figure 1.15 -42- ============================================================================ ---------- {$7c}\ 7404 {$7c}\ {$7c} {$7c} {$7c} \ {$7c} \ {$7c} 39 +------------------O----+ >o---O---o{$7c} >------> systen p2 {$7c} {$7c} {$7c} {$7c} / {$7c} {$7c} / {$7c} {$7c} -+- {$7c}/ {$7c} {$7c}/ {$7c} {$7c} cF -+- rF {$7c} {$7c} {$7c} {$7c} ------ {$7c} {$7c} 37 +---O-----O--------O---+ +---- {$7c} {$7c} {$7c} {$7c} {$7c} ------ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -+- -+- -+- {$7c} {$7c} \ / / \ ----- crystal {$7c} {$7c} -+- -+- ----- {$7c} {$7c} {$7c} {$7c} -+- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ---------O ---------- {$7c} {$7c} {$7c} -+- o vCC //// mcs6502 pARALLEL mODE cRYSTAL cONTROLlED oSCILLATOR figure 1.16A ---------- {$7c}\ 7404 {$7c}\ {$7c} {$7c} {$7c} \ {$7c} \ {$7c} 39 +------------------O----+ >o---O---o{$7c} >------> systen p2 {$7c} {$7c} {$7c} {$7c} / {$7c} {$7c} / {$7c} {$7c} -+- {$7c}/ {$7c} {$7c}/ {$7c} {$7c} cF -+- rF {$7c} {$7c} {$7c} {$7c} ------ {$7c} {$7c} 37 +---O-----O--------O---+ +---O {$7c} {$7c} {$7c} {$7c} {$7c} ------ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -+- -+- {$7c} {$7c} {$7c} {$7c} \ / / \ {$7c} --- {$7c} {$7c} {$7c} -+- -+- {$7c} {$7c}{$7c} {$7c}{$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -----+{$7c} {$7c}+---- {$7c} {$7c} {$7c} {$7c} {$7c}{$7c} {$7c}{$7c} {$7c} {$7c} {$7c} {$7c} --- {$7c} {$7c} {$7c} {$7c} crystal ---------- {$7c} {$7c} {$7c} -+- vcc o //// mcs6502 sERIES mODE cRYSTAL cONTROLLED oSCILLATOR figure 1.16B mcs6502 tIME bASE gENERATION - cRYSTAL cONTROLLED figure 1.16 ---------- {$7c}\ 7404 {$7c}\ {$7c} {$7c} {$7c} \ {$7c} \ {$7c} 39 +------------------O----+ >o---O---o{$7c} >------> systen p2 {$7c} {$7c} {$7c} {$7c} / {$7c} {$7c} / {$7c} {$7c} -+- {$7c}/ {$7c} {$7c}/ {$7c} {$7c} cF -+- rF {$7c} {$7c} {$7c} {$7c} ------ {$7c} {$7c} 37 +------------------O---+ +---- {$7c} {$7c} ------ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ---------- mcs6502 tIME bASE gENERATOR - rc nETWORK figure 1.17 -43- ============================================================================ CIRCUIT. vALUES OF THE FEEDBACK RESISTOR, rf, AND FEEDBACK CAPACITOR, cf, WILL BE DIFFERENT FOR THE CRYSTAL MODE VERSUS THE rc MODE. WHILE THE DE- TAIL SPECIFICATIONS FOR VALUES OF rf AND cf ARE FOUND IN THE DATA SHEET FOR THE mcs6502, CLOCK TIMING CAN BE GENERATED BY USE OF COMBINATIONS OF rf IN THE RANGE OF 0 TO 500k OHMS AND cf IN THE RANGE OF 2 TO 12 PF. tHE READER IS REFERRED TO THE mcs6502 DATA SHEET FOR A DETAILED DESCRIPTION OF THE APPLICATION OF rc NETWORKS AND CRYSTAL OSCILLATORS FOR GENERATION OF THE TIME BASE IN THESE MODES OF OPERATION. tHE mcs6500 BUS DISCIPLINE DESCRIBED IN sECTION 1.3.1 IS APPLI- CABLE WHEREVER THE OSCILLATOR IS LOCATED. fOR DATA TRANSFERS TO BE PROPERLY CARRIED OUT BETWEEN THE PROCESSOR AND THE VARIOUS SUPPORT CHIPS IN THE SYS- TEMS, THE TIMING OF THE CLOCKS CONTROLLING THE INTERNAL PROCESSOR OPERA- TIONS MUST BE VERY CLOSE TO THAT OF THE PHASE TWO CLOCK OUT OF PIN 39 OF THE PROCESSOR WITH NO MORE THAN TWO ttl DELAYS FOR CLOCK BUFFERING. iT IS IMPORTANT IN SYSTEMS WHICH DRIVE THE CLOCK GENERATORS WITH A ttl SQUARE WAVE THAT THIS INPUT WAVEFORM NOT BE USED TO CONTROL THE PERIPHERAL CHIPS UNLESS CARE IS TAKEN TO ASSURE PROPER TIMING OF THE PHASE TWO CLOCK BEING USED IN THESE SUPPORT CHIPS. 1.4.2.3 sync sIGNAL iN THE mcs6502, A sync SIGNAL IS PROVIDED TO IDENTIFY THOSE CYCLES IN WHICH THE PROCESSOR IS DOING AN op code FETCH. tHE sync LINE GOES HIGH DURING PHASE ONE OF AN op code FETCH AND STAYS HIGH FOR THE REMAINDER OF THAT CYCLE. iF THE rdy LINE IS PULLED LOW DURING THE PHASE ONE CLOCK PULSE IN WHICH THE sync LINE WENT HIGH, THE PROCESSOR WILL STOP IN ITS CURRENT STATE. iT REMAINS IN THAT STATE UNTIL THE rdy LINE GOES HIGH. iN THIS MANNER, THE sync SIGNAL CAN BE USED TO CONTROL rdy TO CAUSE SINGLE-INSTRUC- TION EXECUTION. tHIS APPLICATION IS DISCUSSED IN DETAIL IN cHAPTER 2. fIGURE 1.18 CONTAINS A TIMING DIAGRAM FOR THIS SIGNAL. 1.4.2.4 s.o.--sET oVERFLOW tHIS PIN SETS THE OVERFLOW FLAG ON A NEGATIVE TRANSITION FROM ttl ONE TO ttl ZERO. tHIS IS DESIGNED TO WORK WITH A FUTURE i/o PART AND SHOULD NOT BE USED IN NORMAL APPLICATIONS UNLESS THE USER HAS PROGRAMMED FOR THE FACT THE ARITHMETIC OPERATIONS ALSO AFFECT THE OVERFLOW FLAG. -44- ============================================================================ -- --- --- --- --- --- --- --- --- --- --- --- --- --- -- O2 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} --- --- --- --- --- --- --- --- --- --- --- --- --- --- -- -------------------------------- r/w {$7c}1 2{$7c} ------------------------- ----- ----- ----- sync 3{$7c} {$7c} 4{$7c} {$7c} {$7c} {$7c} -------------------------- --------- --------- ---- 1. dURING A MICROPROCESSOR WRITE CYCLE, r/w SIGNAL LOW, THE sync PULSE DOES NOT OCCUR. 2. tHE r/w SIGNAL GOES HIGH TO SIGNAL THE BEGINNING OF A MICROPROCESSOR READ CYCLE. 3. aT THE BEGINNING OF THE READ CYCLE A sync PULSE WILL BE BE GENERATED. tHIS PULSE WILL LAST FOR ONE CYCLE TIME. tHE sync PULSE INDICATES THAT THE MICROPROCESSOR IS READING AN op code FROM THE MEMORY FIELD. iN THIS CASE THE sync PULSE IS HIGH FOR ONE CYCLE AS THE PROCESSOR READS THE op code. 4. tHE PROCESSOR OUTPUTS ANOTHER sync PULSE INDICATING IT HAS COMPLETED THE PREVIOUS INSTRUCTION AND IS FETCHING ANOTHER op code. iN THIS CASE THREE MORE CYCLES ARE NEEDED TO COMPLETE THIS INSTRUCTION BEFORE THE NEXT sync PULSE IS GENERATED. tHE sync PULSE IS APERIODIC IN THAT ITS GENERATION IS A FUNCTION OF THE PROGRAM AND THE RESULTANT LENGTHS OF THE INSTRUCTIONS AND ADDRESSING MODES. mcs6502 sync sIGNAL figure 1.18 -45- ============================================================================ tHE OPERATION OF EACH FUNCTION IS EXACTLY THE SAME AS ON THE mcs6502. ------------------+-------------------+-------------------+-------------------- {$7c} fEATURES {$7c} mcs6503 {$7c} mcs6504 {$7c} mcs6505 {$7c} +=================+===================+===================+===================+ {$7c} aDDRESSING {$7c} 4096 bYTES {$7c} 8192 bYTES {$7c} 4096 bYTES {$7c} {$7c} cAPABILITY {$7c} (ab00 - ab11) {$7c} (ab00 - ab12) {$7c} (ab00 - ab11) {$7c} +-----------------+-------------------+-------------------+-------------------+ {$7c} iNTERRUPT {$7c} ___ ___ {$7c} ___ {$7c} ___ {$7c} {$7c} rEQUEST {$7c} irq, nmi {$7c} irq {$7c} irq {$7c} {$7c} cAPABILITY {$7c} {$7c} {$7c} {$7c} +-----------------+-------------------+-------------------+-------------------+ {$7c} "rEADY" sIGNAL {$7c} -- {$7c} -- {$7c} rdy {$7c} +-----------------+-------------------+-------------------+-------------------+ {$7c} tIMING {$7c} sINGLE pHASE {$7c} sINGLE pHASE {$7c} sINGLE pHASE {$7c} {$7c} sIGNALS {$7c} ttl lEVEL O0(in), {$7c} ttl lEVEL O0(in), {$7c} ttl lEVEL O0(in), {$7c} {$7c} rEQUIRED {$7c} OR cRYSTAL OR rc {$7c} OR cRYSTAL OR rc {$7c} OR cRYSTAL OR rc {$7c} +-----------------+-------------------+-------------------+-------------------+ {$7c} oTHER cONTROL {$7c} ___ {$7c} ___ {$7c} ___ {$7c} {$7c} sIGNALS {$7c} res, r/w {$7c} res, r/w {$7c} res, r/w {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ------------------+-------------------+-------------------+-------------------- fUNCTIONAL fEATURES OF mcs6503, mcs6504, mcs6505 figure 1.19 -46- ============================================================================ fIGURE 1.20 ILLUSTRATES THE PIN DESIGNATION FOR THE THREE PROCES- SORS, INDICATING THE TRADEOFFS THAT EXIST BETWEEN CONTROL SIGNALS AND AD- DRESSING CAPABILITY DUE TO PINOUT CONSTRAINTS. lIKE THE mcs6502, THE 28- PIN MICROPROCESSORS ALSO HAVE THE ON-THE-CHIP-OSCILLATOR AND CLOCK DRIVERS. fIGURE 1.21 AND 1.22 DISPLAY THE CIRCUITRY NECESSARY TO GENERATE THE TIME BASE IN THE CRYSTAL MODE AND rc NETWORK MODE RESPECTIVELY. sPECIFIC DE- TAILS ON THE VALUE OF FEEDBACK RESISTANCE, rf, AND FEEDBACK CAPACITANCE, cf, CAN BE FOUND IN THE APPROPRIATE DATA SHEET. -47- ============================================================================ ___ ---------- ___ ---------- ___ ---------- res -+ 1 40+- p2(out) res -+ 1 40+- p2(out) res -+ 1 40+- p2(out) -+ +- -+ +- -+ +- vSS -+ 2 39+- p0(in) vSS -+ 2 39+- p0(in) vSS -+ 2 39+- p0(in) ___ -+ +- ___ -+ +- ___ -+ +- irq -+ 3 38+- r/w irq -+ 3 38+- r/w irq -+ 3 38+- r/w ___ -+ +- ___ -+ +- ___ -+ +- nmi -+ 4 37+- db0 nmi -+ 4 37+- db0 nmi -+ 4 37+- db0 -+ +- -+ +- -+ +- vCC -+ 5 36+- db1 vCC -+ 5 36+- db1 vCC -+ 5 36+- db1 -+ +- -+ +- -+ +- ab0 -+ 6 35+- db2 ab0 -+ 6 35+- db2 ab0 -+ 6 35+- db2 -+ +- -+ +- -+ +- ab1 -+ 7 34+- db3 ab1 -+ 7 34+- db3 ab1 -+ 7 34+- db3 -+ +- -+ +- -+ +- ab2 -+ 8 33+- db4 ab2 -+ 8 33+- db4 ab2 -+ 8 33+- db4 -+ +- -+ +- -+ +- ab3 -+ 9 32+- db5 ab3 -+ 9 32+- db5 ab3 -+ 9 32+- db5 -+ +- -+ +- -+ +- ab4 -+10 31+- db6 ab4 -+10 31+- db6 ab4 -+10 31+- db6 -+ +- -+ +- -+ +- ab5 -+11 30+- db7 ab5 -+11 30+- db7 ab5 -+11 30+- db7 -+ +- -+ +- -+ +- ab6 -+12 29+- ab11 ab6 -+12 29+- ab11 ab6 -+12 29+- ab11 -+ +- -+ +- -+ +- ab7 -+13 28+- ab10 ab7 -+13 28+- ab10 ab7 -+13 28+- ab10 -+ +- -+ +- -+ +- ab8 -+14 27+- ab9 ab8 -+14 27+- ab9 ab8 -+14 27+- ab9 -+ +- -+ +- -+ +- ---------- ---------- ---------- mcs6503 mcs6504 mcs6505 mcs6503, mcs6504, mcs6505 pINOUT dESIGNATIONS figure 1.20 -48- ============================================================================ ---------- {$7c}\ 7404 {$7c}\ {$7c} {$7c} {$7c} \ {$7c} \ {$7c} 28 +------------------O----+ >o---O---o{$7c} >------> systen p2 {$7c} {$7c} {$7c} {$7c} / {$7c} {$7c} / {$7c} {$7c} -+- {$7c}/ {$7c} {$7c}/ {$7c} {$7c} cF -+- rF {$7c} {$7c} {$7c} {$7c} ------ {$7c} {$7c} 27 +---O-----O--------O---+ +---- {$7c} {$7c} {$7c} {$7c} {$7c} ------ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -+- -+- -+- {$7c} {$7c} \ / / \ ----- crystal {$7c} {$7c} -+- -+- ----- {$7c} {$7c} {$7c} {$7c} -+- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ---------O ---------- {$7c} {$7c} {$7c} -+- o vCC //// mcs6503,4,5 pARALLEL mODE cRYSTAL cONTROLlED oSCILLATOR ---------- {$7c}\ 7404 {$7c}\ {$7c} {$7c} {$7c} \ {$7c} \ {$7c} 28 +------------------O----+ >o---O---o{$7c} >------> systen p2 {$7c} {$7c} {$7c} {$7c} / {$7c} {$7c} / {$7c} {$7c} -+- {$7c}/ {$7c} {$7c}/ {$7c} {$7c} cF -+- rF {$7c} {$7c} {$7c} {$7c} ------ {$7c} {$7c} 27 +---O-----O--------O---+ +---O {$7c} {$7c} {$7c} {$7c} {$7c} ------ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -+- -+- {$7c} {$7c} {$7c} {$7c} \ / / \ {$7c} --- {$7c} {$7c} {$7c} -+- -+- {$7c} {$7c}{$7c} {$7c}{$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -----+{$7c} {$7c}+---- {$7c} {$7c} {$7c} {$7c} {$7c}{$7c} {$7c}{$7c} {$7c} {$7c} {$7c} {$7c} --- {$7c} {$7c} {$7c} {$7c} crystal ---------- {$7c} {$7c} {$7c} -+- vcc o //// mcs6503,4,5 sERIES mODE cRYSTAL cONTROLLED oSCILLATOR mcs6503, mcs6504, mcs6505 tIME bASE gENERATION cRYSTAL cONTROLLED figure 1.16 ---------- {$7c}\ 7404 {$7c}\ {$7c} {$7c} {$7c} \ {$7c} \ {$7c} 39 +------------------O----+ >o---O---o{$7c} >------> systen p2 {$7c} {$7c} {$7c} {$7c} / {$7c} {$7c} / {$7c} {$7c} -+- {$7c}/ {$7c} {$7c}/ {$7c} {$7c} cF -+- rF {$7c} {$7c} {$7c} {$7c} ------ {$7c} {$7c} 37 +------------------O---+ +---- {$7c} {$7c} ------ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ---------- mcs6503, mcs6504, mcs6505 tIME bASE gENERATOR rc nETWORK figure 1.17 -49- ============================================================================ 1.5 periphera1 interface device - mcs6520 1.5.1 iNTRODUCTION tHE mcs6520 IS A DIRECT PIN FOR PIN REPLACEMENT FOR THE mOTOROLA mc6820 pERIPHERAL iNTERFACE aDAPTER, THE "pia". aS SUCH, IT MEETS ALL OF THE "pia" ELECTRICAL SPECIFICATIONS AND IS TOTALLY HARDWARE COMPATIBLE WITH THE mc6820. tHE mcs6520 IS AN i/o DEVICE WHICH ACTS AS AN INTERFACE BETWEEN THE MICROPROCESSOR AND PERIPHERALS SUCH AS PRINTERS, DISPLAYS, KEYBOARDS, ETC. tHE PRIME FUNCTION OF THE ng56520 IS TO RESPOND TO STIMULUS FROM EACH OF THE TWO WORLDS IT IS SERVING. oN THE ONE SIDE, THE mcs6520 IS INTERFACING WITH PERIPHERALS VIA TWO EIGHT-BIT BI-DIRECTIONAL PERIPHERAL DATA PORTS. oN THE OTHER SIDE, THE DEVICE INTERFACES WITH THE MICROPRO- CESSOR THROUGH AN EIGHT-BIT DATA BUS; THIS IS THE SAME DATA BUS DISCUSSED AT LENGTH IN sECTION 1.3.1. iT IS, THEREFORE, SIMPLEST TO VIEW THE BASIC FUNCTION OF THE mcs6520 AS IN THE BLOCK DIAGRAM OF fIGURE 1.23. / ----------- \ {$7c} {$7c} {$7c}<====> control {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} 8 bit {$7c} {$7c} 8 bit {$7c} {$7c} data bus <====>{$7c} {$7c}<====> data port {$7c} peripheral microprocessors {$7c} {$7c} {$7c} {$7c} devices - mc05ox < {$7c} mcs6520 {$7c} > printers, {$7c} {$7c} {$7c} {$7c} displays, etc. {$7c} {$7c} {$7c} 8 bit {$7c} {$7c} {$7c} {$7c}<====> data port {$7c} {$7c} control <====>{$7c} {$7c} {$7c} {$7c} {$7c} {$7c}<====> control {$7c} \ ----------- / bASIC mcs6520 iNTERFACE dIAGRAM figure 1.23 -50- ============================================================================ iN ADDITION TO THE LINES DESCRIBED ABOVE, THE mcs6520 PROVIDES FOUR INTERRUPT INPUT/PERIPHERAL CONTROL LINES AND THE LOGIC NECESSARY FOR SIMPLE, EFFECTIVE CONTROL OF PERIPHERAL INTERRUPTS. nO EXTERNAL LOGIC IS REQUIRED FOR INTERFACING THE mcs650x MICROPROCESSOR TO MOST PERIPHERAL DEVICES. tHE FUNCTIONAL CONFIGURATION OF THE mcs6520 IS PROGRAMMED BY THE MICROPROCESSOR DURING SYSTEMS INITIALIZATION. eACH OF THE PERIPHERAL DATA LINES IS PROGRAMMED TO ACT AS AN INPUT OR OUTPUT AND EACH OF THE FOUR CONTROL/INTERRUPT LINES MAY BE PROGRAMMED FOR ONE OF FOUR POSSIBLE CONTROL MODES. tHIS ALLOWS A HIGH DEGREE OF FLEXIBILITY IN THE OVERALL OPERATION OF THE INTERFACE. sOME OF THE MORE IMPORTANT FEATURES OF THE mcs6520 ARE THE FOLLOWING. * cOMPATIBILITY WITH THE mcs650x MICROPROCESSORS. * eIGHT-BIT BI-DIRECTIONAL DATA BUS FOR COMMUNICATION WITH THE MICROPROCESSOR. * tWO EIGHT-BIT BI-DIRECTIONAL PORTS FOR INTERFACE TO PERIPHERALS. * tWO PROGRAMMABLE CONTROL REGISTERS. * tWO PROGRAMMABLE dATA dIRECTION rEGISTERS. * fOUR INDIVIDUALLY CONTROLLED INTERRUPT INPUT LINES - TWO USABLE AS PERIPHERAL CONTROL OUTPUTS. * hANDSHAKE CONTROL LOGIC FOR INPUT AND OUTPUT PERIPHERAL OPERATION. * hIGH IMPEDANCE THREE-STATE AND DIRECT TRANSISTOR DRIVE PERIPHERAL LINES. * pROGRAM CONTROLLED INTERRUPT AND INTERRUPT MASK CAPABILITY. 1.5.2 oRGANIZATION OF THE mcs6520 fIGURE 1.25 CONTAINS A BLOCK DIAGRAM OF THE mcs6520 SHOWING THE INTERNAL REGISTERS AND DATA PATHS AND THE VARIOUS INPUTS AND OUTPUTS ON THE DEVICE. tHIS SECTION CONTAINS A GENERAL DESCRIPTION OF THE INTERNAL ORGANIZATION OF THE DEVICE ALONG WITH A DISCUSSION OF HOW THE VARIOUS REGISTERS AFFECT ONE ANOTHER. tHE FOLLOWING SECTIONS DISCUSS THE DETAILS -51- ============================================================================ --------------------------- vss ---+ 1 40+---<------ ca1 ---+ +--- pa0 /---+ 2 39+---<-----> ca2 {$7c} ---+ +--- ____ pa1 {$7c} ---+ 3 38+---------> irqa {$7c} ---+ +--- ____ pa2 {$7c} ---+ 4 37+---------> irqb {$7c} ---+ +--- pa3 {$7c} ---+ 5 36+---<------ rs0 {$7c} ---+ +--- pa4 {$7c} ---+ 6 35+---<------ rs1 {$7c} ---+ +--- ___ pa5 {$7c} ---+ 7 34+---<------ res {$7c} ---+ +--- pa6 {$7c} ---+ 8 33+---\ d0 {$7c} ---+ +--- {$7c} pa7 {$7c} ---+ 9 32+--- {$7c} d1 <-->< ---+ +--- {$7c} pb0 {$7c} ---+10 31+--- {$7c} d2 {$7c} ---+ mcs6520 +--- {$7c} pb1 {$7c} ---+11 30+--- {$7c} d3 {$7c} ---+ +--- ><--> pb2 {$7c} ---+12 29+--- {$7c} d4 {$7c} ---+ +--- {$7c} pb3 {$7c} ---+13 28+--- {$7c} d5 {$7c} ---+ +--- {$7c} pb4 {$7c} ---+14 27+--- {$7c} d6 {$7c} ---+ +--- {$7c} pb5 {$7c} ---+15 26+--- {$7c} d7 {$7c} ---+ +---/ pb6 {$7c} ---+16 25+---<------ enable {$7c} ---+ +--- pb7 {$7c} ---+17 24+---<------ cs2 \---+ +--- ___ cb1 ------>---+18 23+---<------ cs3 ---+ +--- cb2 <----->---+19 22+---<------ cs1 ---+ +--- vcc ---+20 21+---<------ r/w ---+ +--- --------------------------- mcs6520 pINOUT dESIGNATIONS pERIPHERAL iNTERFACE aDAPTER figure 1.24 -52- ============================================================================ mcs6520 iNTERNAL aRCHITECTURE figure 1.25 -53- ============================================================================ OF THE INPUTS AND OUTPUTS ON THE CHIP, ALONG WITH A DETAILED DISCUSSION OF THE OPERATION OF EACH REGISTER. tHE FINAL SECTION DISCUSSES THE mcs6520 FROM AN OPERATIONAL VIEWPOINT, DESCRIBING THE INTERACTION OF THE REGISTER BITS, INPUT/OUTPUT LINES, ETC. tHE mcs6520 IS ORGANIZED INTO TWO INDEPENDENT SECTIONS REFERRED TO AS THE "a sIDE" AND THE "b sIDE." eACH SECTION CONSISTS OF A cONTROL rEGIS- TER (cra, crb), dATA dIRECTION rEGISTER (ddra, ddrb), oUTPUT rEGISTER (ora, orb), iNTERRUPT sTATUS cONTROL AND THE BUFFER NECESSARY TO DRIVE THE pERIPH- ERAL iNTERFACE BUSSES. 1.5.2.1 dATA iNPUT rEGISTER wHEN THE MICROPROCESSOR WRITES DATA INTO THE mcs6520, THE DATA WHICH APPEARS ON THE DATA BUS DURING THE pHASE tWO CLOCK PULSE IS LATCHED INTO THE dATA iNPUT rEGISTER. iT IS THEN TRANSFERRED INTO ONE OF SIX IN- TERNAL REGISTERS OF THE mcs6520 AFTER THE TRAILING EDGE OF pHASE tWO. tHIS ASSURES THAT THE DATA ON THE PERIPHERAL OUTPUT LINES WILL NOT "GLITCH," I.E., THE OUTPUT LINES WILL MAKE SMOOTH TRANSITIONS FROM HIGH TO LOW OR FROM LOW TO HIGH AND THE VOLTAGE WILL REMAIN STABLE EXCEPT WHEN IT IS GOING TO THE OPPOSITE POLARITY. 1.5.2.2 cONTROL rEGISTERS (cra AND crb) fIGURE 1.29 ILLUSTRATES THE BIT DESIGNATION AND FUNCTIONS IN THE cONTROL rEGISTERS. tHE cONTROL rEGISTERS ALLOW THE MICROPROCESSOR TO CON- TROL THE OPERATION OF THE INTERRUPT LINES (ca1, ca2, cb1, cb2), AND PERIPH- ERAL CONTROL LINES (ca2, cb2). a SINGLE BIT IN EACH REGISTER CONTROLS THE ADDRESSING OF THE dATA dIRECTION rEGISTERS (ddra, ddrb) AND THE oUTPUT rEG- ISTERS (ora, orb) DISCUSSED BELOW. iN ADDITION, TWO BITS (BIT 6 AND 7) ARE PROVIDED IN EACH CONTROL REGISTER TO INDICATE THE STATUS OF THE INTERRUPT INPUT LINES (ca1, ca2, cbL, cb2). tHESE INTERRUPT STATUS BITS (irqa, irqb) ARE NORMALLY INTERROGATED BY THE MICROPROCESSOR DURING THE INTERRUPT SERV- ICE PROGRAM TO DETERMINE THE SOURCE OF AN ACTIVE INTERRUPT. tHESE ARE THE INTERRUPT LINES WHICH DRIVE THE INTERRUPT INPUT (irq, nmi) OF THE MICRO- PROCESSOR. tHE OTHER BITS IN cra AND crb ARE DESCRIBED IN THE DISCUSSION OF THE INTERFACE TO THE PERIPHERAL DEVICE (sECTION 1.5.4). tHE VARIOUS BITS IN THE CONTROL REGISTERS WILL BE ACCESSED MANY TIMES DURING A PROGRAM TO ALLOW THE PROCESSOR TO ENABLE OR DISABLE INTER- RUPTS) CHANGE OPERATING MODES, ETC. AS REQUIRED BY THE PERIPHERAL DEVICE BEING CONTROLLED. -54- ============================================================================ 1.5.2.3 dATA dIRECTION rEGISTERS (ddra, ddrb) tHE dATA dIRECTION rEGISTERS ALLOW THE PROCESSOR TO PROGRAM EACH LINE IN THE 8-BIT pERIPHERAL i/o PORT TO ACT AS EITHER AN INPUT OR AN OUT- PUT. eACH BIT IN ddra CONTROLS THE CORRESPONDING LINE IN THE pERIPHERAL a PORT AND EACH BIT IN ddrb CONTROLS THE CORRESPONDING LINE IN THE pERIPHERAL b PORT. pLACING A "0" IN THE dATA dIRECTION rEGISTER CAUSES THE CORRESPOND- ING pERIPHERAL i/o LINE TO ACT AS AN INPUT. a "1" CAUSES IT TO ACT AS AN OUTPUT. tHE dATA dIRECTION rEGISTERS ARE NORMALLY PROGRAMMED ONLY DURING THE SYSTEM INITIALIZATION ROUTINE WHICH IS PERFORMED IN RESPONSE TO A rESET SIGNAL. hOWEVER, THE CONTENTS OF THESE REGISTERS CAN BE ALTERED DURING SYSTEM OPERATION. tHIS ALLOWS VERY CONVENIENT CONTROL OF SOME PERIPHERAL DEVICES SUCH AS KEYBOARDS. 1.5.2.4 pERIPHERAL oUTPUT rEGISTERS (ora, orb) tHE pERIPHERAL oUTPUT rEGISTERS STORE THE OUTPUT DATA WHICH AP- PEARS ON THE pERIPHERAL i/o PORT. wRITING AN "0" INTO A BIT IN ora CAUSES THE CORRESPONDING LINE ON THE pERIPHERAL a PORT TO GO LOW (< 0.4V) IF THAT LINE IS PROGRAMMED TO ACT AS AN OUTPUT. a "1" CAUSES THE CORRESPONDING OUTPUT TO GO HIGH. tHE LINES OF THE pERIPHERAL b PORT ARE CONTROLLED BY orb IN THE SAME MANNER. aDDRESSING OF THESE REGISTERS IS DISCUSSED IN sECTION 1.5.3.4. 1.5.2.5 iNTERRUPT sTATUS cONTROL tHE FOUR INTERRUPT/PERIPHERAL CONTROL LINES (ca1, ca2, cb1, cb2) ARE CONTROLLED BY THE iNTERRUPT sTATUS cONTROL (a, b). tHIS LOGIC INTER- PRETS THE CONTENTS OF THE CORRESPONDING cONTROL rEGISTER, DETECTS ACTIVE TRANSITIONS ON THE INTERRUPT INPUTS AND PERFORMS THOSE OPERATIONS NECESSARY TO ASSURE PROPER OPERATION OF THESE FOUR PERIPHERAL INTERFACE LINES. tHE OPERATION OF THESE LINES IS DESCRIBED IN DETAIL IN sECTION 1.5.4.2. 1.5.2.6 pERIPHERAL iNTERFACE bUFFERS (a, b) AND dATA bUS bUFFERS (dbb) tHE bUFFERS WHICH DRIVE THE PERIPHERAL i/o PORTS AND THE DATA BUS PROVIDE THE CURRENT AND VOLTAGE DRIVE NECESSARY TO ASSURE PROPER SYSTEM OPERATION AND TO MEET THE DEVICE SPECIFICATIONS. -55- ============================================================================ 1.5.3 iNTERFACE bETWEEN mcs6520 AND THE mcs650x fAMILY OF mICROPROCESSORS tHE mcs6520 INTERFACES TO THE MICROPROCESSOR WITH AN 8-BIT BI-DIREC- TIONAL DATA BUS, 3 CHIP-SELECT LINES, 2 REGISTER-SELECT LINES, 2 INTERRUPT REQUEST LINES, READ/WRITE LINE, ENABLE LINE AND RESET LINE. 1.5.3.1 dATA bUS (d0-d7) tHE 8-BIT, BI-DIRECTIONAL DATA BUS ALLOWS THE TRANSFER OF DATA BE- TWEEN THE MICROPROCESSOR AND THE mcs6520. tHE DATA BUS OUTPUT DRIVERS ARE 3-STATE DEVICES THAT REMAIN IN THE HIGH IMPEDANCE STATE EXCEPT WHEN THE MICROPROCESSOR READS DATA FROM THE PERIPHERAL ADAPTER. tHIS DATA BUS IS THE SAME AS DISCUSSED IN sECTION 1.3.1, "bUS sTRUCTURE." 1.5.3.2 eNABLE (e) tHE eNABLE INPUT IS THE ONLY MICROPROCESSOR INTERFACE TIMING INPUT ON THE PERIPHERAL INTERFACE DEVICE. aLL DATA TRANSFERS INTO AND OUT OF THE mcs6520 ARE CONTROLLED BY THIS SIGNAL. iN NORMAL OPERATION, THIS INPUT SHOULD BE CONNECTED TO THE PHASE TWO CLOCK SIGNAL. iN THE CASE OF THE mcs6501, THIS IS THE 02 CLOCK GENERATED EXTERNAL TO THE MICROPROCESSOR CHIP. fOR ON-CHIP OSCILLATOR PRODUCTS (mcs6502, mcs6503, mcs6504 AND mcs6505), THE ENABLE PULSE BECOMES 02(out). 1.5.3.3 rEAD/wRITE (r/w) tHIS SIGNAL IS GENERATED BY THE MICROPROCESSOR TO CONTROL THE DI- RECTION OF DATA TRANSFERS ON THE DATA BUS. a LOW (< 0.4V) ON THIS LINE ENABLES THE INPUT BUFFERS (MICROPROCESSOR wRITE) AND DATA IS TRANSFERRED FROM THE MICROPROCESSOR TO THE mcs6520 UNDER CONTROL OF eNABLE INPUT IF THE DEVICE HAS BEEN CHIP-SELECTED. a HIGH ON THE r/w LINE ALLOWS THE mcs6520 TO TRANSFER DATA TO THE DATA BUS BUFFERS. tHE DATA BUS BUFFERS ARE ENABLED WHEN THE PROPER CHIP-SELECT AND eNABLE SIGNALS ARE PRESENT. fIGURE 1.26 ILLUSTRATES THE rEAD/wRITE TIMING. 1.5.3.4 cHIP sELECT lINES (cs1, cs2, cs3) tHESE THREE INPUTS ALLOW THE MICROPROCESSOR TO SELECT THE PROPER PERIPHERAL INTERFACE DEVICE. cs1 AND cs2 MUST BE HIGH AND cs3 MUST BE LOW FOR SELECTION OF THE DEVICE. dATA TRANSFERS ARE THEN PERFORMED UNDER CON- TROL OF THE eNABLE AND r/w SIGNALS. tHESE LINES ARE NORMALLY CONNECTED TO THE ADDRESS LINES ON THE MICROPROCESSOR, EITHER DIRECTLY OR THROUGH ADDRESS DECODERS. -56- ============================================================================ ->{$7c} 180 {$7c}<- {$7c} {$7c} {$7c} {$7c}-------------- -------- 2.4v nable {$7c} /{$7c} \ / -------{$7c}---- {$7c} {$7c}-------------- 0.4v {$7c} {$7c} {$7c} {$7c} ->{$7c} 300 {$7c}<- {$7c} {$7c} {$7c} {$7c} {$7c} ------ {$7c}-----{$7c}-------{$7c}-------{$7c}----------------------- 2.4v address x{$7c} {$7c} {$7c} {$7c} ------ {$7c}-----{$7c}-------{$7c}-------{$7c}----------------------- 0.4v {$7c} {$7c} {$7c} ->{$7c} {$7c}<- 20 {$7c} {$7c} {$7c} -------------------- {$7c}-------{$7c}\{$7c} 2.4v data bus x{$7c} {$7c} > -------------------- -------------------- {$7c}-------{$7c}/{$7c} 0.4v {$7c} {$7c} ---- {$7c}-----------------------{$7c}----------------------- 2.4v peripheral x{$7c} {$7c} data (a or b) ---- {$7c}-----------------------{$7c}----------------------- 0.4v {$7c} {$7c} {$7c}<------- 700 ------->{$7c} mICROPROCESSOR iNTERFACE tIMING rEAD figure 1.26A {$7c}<- 470 ->{$7c} {$7c} {$7c} {$7c}-------------{$7c} -------- 2.4v nable /{$7c} \ / ------------ {$7c} {$7c}-------------- 0.4v {$7c} {$7c} ->{$7c} 180 {$7c}<- ->{$7c} 100 {$7c}<- {$7c} {$7c} {$7c} {$7c} ------ {$7c}-----{$7c}-------{$7c}-------{$7c}----------------------- 2.4v address x{$7c} {$7c} {$7c} {$7c} ------ {$7c}-----{$7c}-------{$7c}-------{$7c}----------------------- 0.4v {$7c} {$7c} {$7c} ->{$7c} 130 {$7c}<- {$7c} {$7c} {$7c} {$7c} {$7c} -- {$7c} {$7c} {$7c} --------------------- 2.4v read/write \{$7c} {$7c} {$7c} / {$7c}-----------------{$7c}-------{$7c}- 0.4v {$7c} {$7c} {$7c} ->{$7c} {$7c}<- 20 {$7c} {$7c} {$7c} -------------------- {$7c}-------{$7c}\{$7c} 2.4v data bus x{$7c} {$7c} > -------------------- -------------------- {$7c}-------{$7c}/{$7c} 0.4v {$7c} {$7c} ---- {$7c}-----------------------{$7c}----------------------- 2.4v peripheral x{$7c} {$7c} data (a or b) ---- {$7c}-----------------------{$7c}----------------------- 0.4v {$7c} {$7c} {$7c}<------- 700 ------->{$7c} *note: all times specified are in Nsec for 1mhz operation. mICROPROCESSOR iNTERFACE tIMING - wRITE figure 1.26B -57- ============================================================================ aS DESCRIBED IN sECTION 1.5.5.2, A SINGLE BIT IN EACH cONTROL rEG- ISTER (cra AND crb) CONTROLS ACCESS TO THE dATA dIRECTION rEGISTER OR THE pERIPHERAL INTERFACE. iF BIT 2 IN THE cONTROL rEGISTER IS A "1," A pERIPH- ERAL oUTPUT REGISTER (ora, orb) IS SELECTED, AND IF BIT 2 IS A "0," THE dATA dIRECTION rEGISTER IS SELECTED. iNTERNAL REGISTERS ARE SELECTED BY THE rEGISTER sELECT LINES (rs0, rs1) AND THE dATA dIRECTION rEGISTER aCCESS cONTROL BIT AS FOLLOWS: dATA dIRECTION rEGISTER aCCESS cONTROL bIT rs1 rs0 cra-2 crb-2 rEGISTER sELECTED 0 0 1 - pERIPHERAL iNTERFACE a (sEE sECTION 1.5.3.5.1) 0 0 0 - dATA dIRECTION rEGISTER a 0 1 - - cONTROL rEGISTER a 1 0 - 1 pERIPHERAL iNTERFACE b (sEE sECTION 1.5.3.5.2) 1 0 - 0 dATA dIRECTION rEGISTER b 1 1 - - cONTROL rEGISTER b iF THE PROGRAMMER WISHES TO WRITE THE DATA INTO ddra, ora, ddrb, OR orb, HE MUST FIRST SET BIT 2 IN THE PROPER cONTROL rEGISTER. tHE DE- SIRED REGISTER CAN THEN BE ACCESSED WITH THE ADDRESS DETERMINED BY THE ADDRESS INTERCONNECT TECHNIQUE USED. (sEE cHAPTER 2, sECTION 2.3.1 FOR A DISCUSSION OF ADDRESSING IN mcs650x SYSTEMS.) 1.5.3.5 rEGISTER sELECT lINES (rs0), (rs1) tHESE TWO REGISTER SELECT LINES ARE USED TO SELECT THE VARIOUS REG- ISTERS INSIDE THE mcs6520. tHESE INPUT LINES ARE USED IN CONJUNCTION WITH INTERNAL CONTROL REGISTERS TO SELECT A PARTICULAR REGISTER THAT IS TO BE ACCESSED BY THE MICROPROCESSOR. tHESE LINES ARE NORMALLY CONNECTED TO MICROPROCESSOR ADDRESS OUTPUT LINES. tHESE LINES OPERATE IN CONJUNCTION WITH THE CHIP-SELECT INPUTS TO ALLOW THE MICROPROCESSOR TO ADDRESS A SINGLE 8-BIT REGISTER. WITHIN THE MICROPROCESSOR ADDRESS SPACE. tHIS REGISTER MAY BE AN INTERNAL REGISTER (cra, ora, ETC.) OR IT MAY BE A pERIPHERAL i/o PORT. tHE PROCESSOR CAN WRITE DIRECTLY INTO THE cONTROL rEGISTERS (cra, crb), THE dATA dIRECTION rEGISTERS (ddra, ddrb) AND THE pERIPHERAL oUTPUT rEGISTERS (ora, orb). iN ADDITION, THE PROCESSOR CAN DIRECTLY READ THE -58- ============================================================================ CONTENTS OF THE cONTROL rEGISTERS AND THE dATA dIRECTION rEGISTERS. aCCESS- ING THE pERIPHERAL oUTPUT rEGISTER FOR THE PURPOSE OF READING DATA BACK INTO THE PROCESSOR OPERATES DIFFERENTLY ON THE ora AND THE orb REGISTERS AND THEREFORE ARE DISCUSSED SEPARATELY BELOW. 1.5.3.5.1 rEADING THE pERIPHERAL a i/o pORT tHE pERIPHERAL a i/o PORT CONSISTS OF 8 LINES WHICH CAN BE PRO- GRAMMED TO ACT AS INPUTS OR OUTPUTS. wHEN PROGRAMMED TO ACT AS OUTPUTS, EACH LINE REFLECTS THE CONTENTS OF THE CORRESPONDING BIT IN THE pERIPHERAL oUTPUT rEGISTER. wHEN PROGRAMMED TO ACT AS AN INPUT, THESE LINES WILL GO HIGH OR LOW DEPENDING ON THE INPUT DATA. tHE pERIPHERAL oUTPUT rEGISTER (ora) HAS NO EFFECT ON THOSE LINES PROGRAMMED TO ACT AS INPUTS. tHE 8 LINES OF THE pERIPHERAL a i/o PORT THEREFORE CONTAIN EITHER INPUT OR OUTPUT DATA DEPENDING ON WHETHER THE LINE IS PROGRAMMED TO ACT AS AN INPUT OR AN OUTPUT. fIGURE 1.27A ILLUSTRATES THE INTERFACE TIMING. pERFORMING A rEAD OPERATION WITH rs1 = 0, rs0 = 0 AND THE dATA dIRECTION rEGISTER aCCESS cONTROL BIT (cra-2) = 1, DIRECTLY TRANSFERS THE DATA ON THE pERIPHERAL a i/o LINES INTO THE PROCESSOR (VIA THE DATA BUS). tHIS WILL CONTAIN BOTH THE INPUT AND OUTPUT DATA. tHE PROCESSOR MUST BE PROGRAMMED TO RECOGNIZE AND INTERPRET ONLY THOSE BITS WHICH ARE IMPORTANT TO THE PARTICULAR PERIPHERAL OPERATION BEING PERFORMED. sINCE THE PROCESSOR ALWAYS READS THE pERIPHERAL a i/o PORT PINS INSTEAD OF THE ACTUAL pERIPHERAL oUTPUT rEGISTER (ora), IT IS POSSIBLE FOR THE DATA READ INTO THE PROCESSOR TO DIFFER FROM THE CONTENTS OF THE pERIPH- ERAL oUTPUT rEGISTER FOR AN OUTPUT LINE. tHIS IS TRUE WHEN THE i/o PIN IS NOT ALLOWED TO GO TO A FULL +2.4V dc WHEN THE pERIPHERAL oUTPUT REGISTER CONTAINS A LOGIC 1. iN THIS CASE, THE PROCESSOR WILL READ A 0 FROM THE pERIPHERAL a PIN, EVEN THOUGH THE CORRESPONDING BIT IN THE pERIPHERAL oUT- PUT REGISTER IS A 1. 1.5.3.5.2 rEADING THE pERIPHERAL b i/o pORT rEADING THE pERIPHERAL b i/o PORT YIELDS A COMBINATION OF INPUT AND OUTPUT DATA IN A MANNER SIMILAR TO THE pERIPHERAL a PORT. hOWEVER, DATA IS READ DIRECTLY FROM THE pERIPHERAL b oUTPUT rEGISTER (orb) FOR THOSE LINES PROGRAMMED TO ACT AS OUTPUTS. iT IS THEREFORE POSSIBLE TO LOAD DOWN THE pERIPHERAL b oUTPUT LINES WITHOUT CAUSING INCORRECT DATA TO BE TRANS- FERRED BACK INTO THE PROCESSOR ON A rEAD OPERATION. fIGURE L.27B ILLUS- TRATES THE TIMING. -59- ============================================================================ -------- -------- {$7c}------- -------- enable / \ / \ /{$7c} \ / \ - ---/ /--- --------- {$7c} {$7c} {$7c}------- -- {$7c} {$7c} {$7c} ->{$7c}180{$7c}<- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} --------------/ /------------------ {$7c}---{$7c}----{$7c}---{$7c}------------------- address x{$7c} {$7c} {$7c} {$7c} --------------/ /------------------ {$7c}---{$7c}----{$7c}---{$7c}------------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -----{$7c}----{$7c}---{$7c}------------------- read/write / {$7c} {$7c} {$7c} --------------/ /----------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ->{$7c}100{$7c}<- {$7c} {$7c} {$7c} {$7c} /{$7c}---{$7c}\{$7c} data bus --------------/ /-----------------------{$7c}--< {$7c} {$7c} >----------------- {$7c} \{$7c}---{$7c}/{$7c} {$7c} ->{$7c} {$7c}<-20 - ------------------------------------------------------------------- peripheral x data - ------------------------------------------------------------------- 1.0Us ->{$7c} {$7c}<- ------------------------------------------------- {$7c} {$7c}-- ca2 (ac5 = ac3 = 1, ac4 = 0) \ {$7c}/{$7c} pulse output mode --------------{$7c} {$7c} ->{$7c} {$7c}<- 1.0Us --{$7c} {$7c}---------------------------------------------------------------- ca1 {$7c}x{$7c} --{$7c} {$7c}---------------------------------------------------------------- {$7c} ->{$7c} {$7c}<- 2.0Us {$7c} {$7c} {$7c} {$7c}----------------------------------------- ca2 /{$7c} \ ------ ------------------- (ac = 1, ac3 = ac$ = 0) handshake mode note: all times specified are in Nsec for 1mhz operation pERIPHERAL a iNTERFACE tIMING figure 1.27A -60- ============================================================================ {$7c}------- {$7c}------- {$7c}------- --- enable /{$7c} \ /{$7c} \ /{$7c} \ / ------- {$7c} {$7c}------- {$7c} -------- {$7c} -------- {$7c} {$7c} {$7c} {$7c} ->{$7c}180{$7c}<- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} --- {$7c}---{$7c}-----------------{$7c}-----------------{$7c}-------------------- address x{$7c} {$7c} {$7c} x {$7c} {$7c} --- {$7c}---{$7c}---------- ------{$7c}-----------------{$7c}-------------------- {$7c} {$7c} {$7c} {$7c} ->{$7c} 130 {$7c}<- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} - {$7c} {$7c} ------{$7c}-----------------{$7c}-------------------- read/write \{$7c} {$7c} / {$7c} {$7c} {$7c}--------------{$7c}- {$7c} {$7c} {$7c} {$7c} {$7c} ->{$7c}100{$7c}<- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ------------ {$7c}---{$7c}-{$7c} -----{$7c}-----------------{$7c}-------------------- data bus x{$7c} {$7c} x {$7c} {$7c} ------------ {$7c}---{$7c}-{$7c} -----{$7c}-----------------{$7c}-------------------- {$7c} {$7c} {$7c} {$7c} 20 ->{$7c} {$7c}<- {$7c} {$7c} {$7c} {$7c} {$7c} -----------------{$7c}--- {$7c}---{$7c}-----------------{$7c}-------------------- peripheral data and {$7c} x{$7c} {$7c} {$7c} cb2 -----------------{$7c}--- {$7c}---{$7c}-----------------{$7c}-------------------- (normal output mode) {$7c} {$7c} {$7c} {$7c} 1.0Us ->{$7c} {$7c}<- {$7c} ->{$7c} {$7c}<- 1.0 Us {$7c} {$7c} {$7c} --------------------------{$7c}- {$7c} {$7c} -{$7c}---------------- cb2 (bc5 = bc3 = 1, bc4 = 0) {$7c} \ {$7c} {$7c} / {$7c} (pulse output mode) {$7c} -{$7c}-------------{$7c}- {$7c} 1.0 Us {$7c} {$7c} {$7c} {$7c} ->{$7c} {$7c}<- ->{$7c} {$7c}<- 1.0Us {$7c} {$7c} ------------------------------{$7c}------------------------{$7c} {$7c}------- cb1 {$7c} {$7c}x{$7c} ------------------------------{$7c}------------------------{$7c} {$7c}------- {$7c} {$7c} {$7c} {$7c} {$7c} ---------------------------- {$7c} {$7c} -{$7c}--- cb2 (bc5 = 1, bc3 = bc4 = 0) \ {$7c} {$7c} / {$7c} (handshake mode) -{$7c}--------------------------{$7c}- {$7c} {$7c} {$7c} 2.0Us ->{$7c} {$7c}<- pERIPHERAL a iNTERFACE tIMING figure 1.27B -61- ============================================================================ -------------------- ----------------------- {$7c} {$7c} +5v {$7c} {$7c} +5v +5v {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -+- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ----+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}{$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}+---- -+- {$7c} {$7c} -+- {$7c}{$7c} {$7c} {$7c} {$7c} output {$7c} {$7c} {$7c} ----+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +-----+---> {$7c} {$7c} {$7c} {$7c} {$7c} to {$7c} {$7c} {$7c} -+- +--------+-----> chip {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}--- {$7c} {$7c} {$7c} {$7c} {$7c}{$7c} {$7c} {$7c} {$7c} {$7c}--- from-->--+{$7c} {$7c} {$7c} {$7c} {$7c}{$7c} chip {$7c}{$7c} {$7c} --->--{$7c}----+---+{$7c} {$7c}--- {$7c} {$7c} {$7c}{$7c} {$7c} {$7c} input {$7c} {$7c}--- {$7c} {$7c} {$7c} {$7c} -+- {$7c} {$7c} {$7c} - {$7c} {$7c} -+- {$7c} {$7c} - {$7c} {$7c} mcs6520 {$7c} {$7c} mcs6520 {$7c} {$7c} -------------------- ----------------------- pERIPHERAL i/o fORT a bUFFER figure 1.28a -------------------- ----------------------- {$7c} {$7c} +5v {$7c} {$7c} +5v {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}--- {$7c} {$7c} {$7c} {$7c}{$7c} {$7c} {$7c} ----+ -->--+{$7c} {$7c} {$7c} {$7c}{$7c} {$7c}{$7c} {$7c} {$7c} {$7c}+---- {$7c}--- {$7c} {$7c} {$7c}{$7c} {$7c} {$7c} {$7c} output {$7c} ----+ {$7c} from {$7c} {$7c} {$7c} {$7c} {$7c} chip +-----+---> {$7c} {$7c} {$7c} to {$7c} {$7c} {$7c} +--------+-----> chip {$7c} {$7c} {$7c} {$7c} {$7c}--- {$7c} {$7c} {$7c} {$7c}{$7c} {$7c} {$7c} {$7c}--- -->--+{$7c} {$7c} {$7c} {$7c}{$7c} {$7c}{$7c} {$7c} --->--{$7c}--------+{$7c} {$7c}--- {$7c} {$7c} {$7c}{$7c} {$7c} {$7c} input {$7c} {$7c}--- {$7c} {$7c} {$7c} {$7c} -+- {$7c} {$7c} {$7c} - {$7c} {$7c} -+- - {$7c} {$7c} -+- {$7c} {$7c} - {$7c} {$7c} mcs6520 {$7c} {$7c} mcs6520 {$7c} {$7c} -------------------- ----------------------- pERIPHERAL i/o pORT b bUFFER figure 1.28b -62- ============================================================================ tHE DETAILS OF THE pERIPHERAL a AND pERIPHERAL b PORTS WILL BE DISCUSSED IN THE NEXT SECTION UNDER THE DISCUSSION OF THE INTERFACE BETWEEN THE mcs6520 AND THE pERIPHERAL dEVICES. ___ 1.5.3.6 rESET (res) tHE ACTIVE LOW rESET LINE RESETS THE CONTENTS OF ALL mcs6520 REG- ISTERS TO A LOGIC ZERO. tHIS LINE CAN BE USED AS A POWER-ON RESET OR AS A MASTER RESET DURING SYSTEM OPERATION. ____ ____ 1.5.3.7 iNTERRUPT rEQUEST lINE (irqa, irqb) ____ ____ tHE ACTIVE LOW iNTERRUPT rEQUEST LINES (irqa AND irqb) ACT TO INTERRUPT THE MICROPROCESSOR EITHER DIRECTLY OR THROUGH EXTERNAL INTERRUPT PRIORITY CIRCUITRY. tHESE LINES ARE "OPEN SOURCE" (NO LOAD DEVICE ON THE CHIP) AND ARE CAPABLE OF SINKING 1.6 MILLIAMPS FROM AN EXTERNAL SOURCE. tHIS PERMITS ALL INTERRUPT REQUEST LINES TO BE TIED TOGETHER IN A "WIRED-or" CONFIGURATION. tHE "a" AND "b" IN THE TITLES OF THESE LINES CORRESPOND TO THE "a" PERIPHERAL PORT AND THE "b" PERIPHERAL PORT. hENCE EACH INTERRUPT REQUEST LINE SERVICES ONE PERIPHERAL DATA PORT. eACH iNTERRUPT rEQUEST LINE HAS TWO INTERRUPT FLAG BITS WHICH CAN CAUSE THE iNTERRUPT rEQUEST LINE TO GO LOW. tHESE FLAGS ARE BITS 6 AND 7 IN THE TWO cONTROL rEGISTERS. tHESE FLAGS ACT AS THE LINK BETWEEN THE PERIPHERAL INTERRUPT SIGNALS AND THE MICROPROCESSOR INTERRUPT INPUTS. eACH FLAG HAS A CORRESPONDING INTERRUPT DISABLE BIT WHICH ALLOWS THE PROCESSOR TO ENABLE OR DISABLE THE INTERRUPT FROM EACH OF THE FOUR INTERRUPT INPUTS (ca1, ca2, cb1, cb2). tHE FOUR INTERRUPT FLAGS ARE SET BY ACTIVE TRANSITIONS OF THE SIG- NAL ON THE INTERRUPT INPUT (ca1, ca2, cb1, cb2). cONTROLLING THIS ACTIVE TRANSITION IS DISCUSSED IN THE NEXT SECTION UNDER THE DISCUSSION OF THE INTERFACE BETWEEN THE mcs6520 AND THE PERIPHERAL DEVICE. ____ 1.5.3.7.1 cONTROL OF irqa cONTROL rEGISTER a BIT 7 IS ALWAYS SET BY AN ACTIVE TRANSITION OF THE ca1 INTERRUPT INPUT SIGNAL. iNTERRUPTING FROM THIS FLAG CAN BE DIS- ABLED BY SETTING BIT 0 IN THE cONTROL rEGISTER a (cra) TO A LOGIC 0. lIKE- WISE, cONTROL rEGISTER a BIT 6 CAN BE SET BY AN ACTIVE TRANSITION OF THE ca2 INTERRUPT INPUT SIGNAL. iNTERRUPTING FROM THIS FLAG CAN BE DISABLED BY SETTING BIT 3 IN THE cONTROL rEGISTER TO A LOGIC 0. -63- ============================================================================ bOTH BIT 6 AND BIT 7 IN cra ARE RESET BY A "rEAD pERIPHERAL oUT- PUT rEGISTER a" OPERATION. tHIS IS DEFINED AS AN OPERATION IN WHICH THE PROPER CHIP-SELECT AND REGISTER-SELECT SIGNALS ARE PROVIDED TO ALLOW THE PROCESSOR TO READ THE pERIPHERAL a i/o PORT. ____ 1.5.3.7.2 cONTROL OF irqb cONTROL OF irqb IS PERFORMED IN EXACTLY THE SAME MANNER AS THAT DESCRIBED ABOVE FOR irqa. bIT 7 IN crb IS SET BY AN ACTIVE TRANSITION ON cb1; JNTERRUPTING FROM THIS FLAG IS CONTROLLED BY crb BIT 0. lIKEWISE, BIT 6 IN crb IS SET BY AN ACTIVE TRANSITION ON cb2; INTERRUPTING FROM THIS FLAG IS CONTROLLED BY crb BIT 3. aLSO, BOTH BIT 6 AND BIT 7 ARE RESET BY A "rEAD pERIPHERAL b oUTPUT rEGISTERT" OPERATION. summary: irqa GOES LOW WHEN cra-7 = 1 AND cra-0 = 1 OR WHEN cra-6 = 1 AND cra-3 = 1. irqb GOES LOW WHEN crb-7 = 1 AND crb-0 = 1 OR WHEN crb-6 = 1 AND crb-3 = 1. tHE USE OF THESE INTERRUPT FLAGS AND INTERRUPT DISABLE BITS IS DISCUSSED IN MORE DETAIL IN sECTION 1.5.4. iT SHOULD BE STRESSED AT THIS POINT THAT THE FLAGS ACT AS THE LINK BETWEEN THE PERIPHERAL INTERRUPT SIGNALS AND THE PROCESSOR INTERRUPT INPUTS. tHE INTERRUPT DISABLE BITS ALLOW THE PROCESSOR TO CONTROL THE INTERRUPT FUNCTION. 1.5.4 iNTERFACE bETWEEN mcs6520 AND pERIPHERAL dEVICES tHE mcs6520 PROVIDES 2 8-BIT BI-DIRECTIONAL PORTS AND 4 INTERRUPT/ CONTROL LINES FOR INTERFACING TO PERIPHERAL DEVICES. tHESE PORTS AND THE ASSOCIATED INTERRUPT/CONTROL LINES ARE REFERRED TO AS THE "a" SIDE AND THE AND THE "b" SIDE. eACH SIDE HAS ITS OWN UNIQUE CHARACTERISTICS AND WILL THEREFORE BE DISCUSSED SEPARATELY BELOW. 1.5.4.1 pERIPHERAL i/o pORTS tHE PERIPHERAL a AND pERIPHERAL b i/o PORTS ALLOW THE MICROPROCES- SOR TO INTERFACE TO THE INPUT LINES ON THE PERIPHERAL DEVICE BY LOADING DATA INTO THE pERIPHERAL oUTPUT rEGISTER. tHEY ALSO ALLOW THE PROCESSOR TO INTERFACE WITH THE PERIPHERAL DEVICE OUTPUT LINES BY READING THE DATA ON -64- ============================================================================ THE pERIPHERAL pORT INPUT LINES DIRECTLY ONTO THE DATA BUS AND INTO THE INTERNAL REGISTERS OF THE PROCESSOR. 1.5.1.1.1 pERIPHERAL a i/o pORT (pa0-pa7) aS DISCUSSED IN sECTION 1.5.2.3. EACH OF THE pERIPHERAL i/o LINES CAN BE PROGRAMMED TO ACT AS AN INPUT OR AN OUTPUT. tHIS IS ACCOMPLISHED BY SETTING A "1" IN THE CORRESPONDING BIT IN THE dATA dIRECTION rEGISTER FOR THOSE LINES WHICH ARE TO ACT AS OUTPUTS. a "0" IN A BIT OF THE dATA dIREC- TION rEGISTER CAUSES THE CORRESPONDING pERIPHERAL i/o LINES TO ACT AS AN INPUT. tHE BUFFERS WHICH DRIVE THE pERIPHERAL a i/o LINES CONTAIN "PASSIVE" PULL-UPS AS SHOWN IN fIGURE 1.28A. tHESE PULL-UP DEVICES ARE RESISTIVE IN NATURE AND THEREFORE ALLOW THE OUTPUT VOLTAGE TO GO TO vDD FOR A LOGIC 1. tHE SWITCHES CAN SINK A FULL 1.6 MA, MAKING THESE BUFFERS CAP- ABLE OF DRIVING ONE STANDARD ttl LOAD. iN THE INPUT MODE, THE PULL-UP DEVICES SHOWN IN fIGURE 1.28A ARE STILL CONNECTED TO THE i/o PIN AND STILL SUPPLY CURRENT TO THIS PIN. fOR THIS REASON, THESE LINES REPRESENT ONE STANDARD ttl LOAD IN THE INPUT MODE. 1.5.4.1.2 pERIPHERAL b i/o pORT (pb0-pb7) tHE pERIPHERAL b i/o PORT DUPLICATES MANY OF THE FUNCTIONS OF THE pERIPHERAL a PORT. tHE PROCESS OF PROGRAMMING THESE LINES TO ACT AS AN INPUT OR AN OUTPUT HAS BEEN DISCUSSED PREVIOUSLY. lIKEWISE, THE EFFECT OF READING OR WRITING THIS PORT HAS BEEN DISCUSSED. hOWEVER, THERE ARE SEV- ERAL CHARACTERISTICS OF THE BUFFERS DRIVING THESE LINES WHICH AFFECT THEIR USE IN PERIPHERAL INTERFACING. tHESE WILL BE DISCUSSED BELOW. tHE pERIPHERAL b i/o PORT BUFFERS ARE PUSH-PULL DEVICES AS SHOWN IN fIGURE 1.28B. tHE PULL-UP DEVICES ARE SWITCHED "off" IN THE "0" STATE AND "on" FOR A LOGIC 1. sINCE THESE PULL-UPS ARE ACTIVE DEVICES, THE LOGIC "1" VOLTAGE IS NOT GUARANTEED TO GO HIGHER THAN +2.4v. tHEY ARE ttl COM- PATIBLE BUT ARE NOT cmos COMPATIBLE. hOWEVER, THE ACTIVE PULL-UP DEVICES CAN SINK UP TO 1 MA AT 1.5v. tHIS CURRENT DRIVE CAPABILITY IS PROVIDED TO ALLOW DIRECT CONNECTION TO dARLINGTON TRANSISTOR SWITCHES. tHIS ALLOWS VERY SIMPLE CONTROL OF RELAYS, LAMPS, ETC. bECAUSE THESE OUTPUTS ARE DESIGNED TO DRIVE TRANSISTORS DIRECTLY, THE OUTPUT DATA IS READ DIRECTLY FROM THE pERIPHERAL oUTPUT rEGISTER FOR THOSE LINES PROGRAMMED TO ACT AS INPUTS. -65- ============================================================================ tHE FINAL CHARACTERISTIC WHICH IS A FUNCTION OF THE pERIPHERAL b PUSH-PULL BUFFERS IS THE HIGH-IMPEDANCE INPUT STATE. wHEN THE pERIPHERAL b i/o LINES ARE PROGRAMMED TO ACT AS INPUTS, THE OUTPUT BUFFER ENTERS THE HIGH IMPEDANCE STATE. tHESE INPUTS WILL THEN HAVE AN IMPEDANCE OF GREATER THAN 1 MEGOHM. 1.5.4.2 iNTERRUPT iNPUT/pERIPHERAL cONTROL lINES (ca1, ca2, cb1, cb2) tHE FOUR INTERRUPT INPUT/PERIPHERAL CONTROL LINES PROVIDE A NUMBER OF SPECIAL PERIPHERAL CONTROL FUNCTIONS. tHESE LINES GREATLY ENHANCE THE POWER OF THE TWO GENERAL PURPOSE INTERFACE PORTS (pa0-pa7, pb0-pb7). 1.5.4.2.1 pERIPHERAL a iNTERRUPT iNPUT/pERIPHERAL cONTROL lINES (ca1, ca2) ca1 IS AN INTERRUPT INPUT ONLY. aN ACTIVE TRANSITION OF THE SIGNAL ON THIS INPUT WILL SET BIT 7 OF THE cONTROL rEGISTER a TO A LOGIC 1. tHE ACTIVE TRANSITION CAN BE PROGRAMMED BY THE MICROPROCESSOR BY SETTING A "0" IN BIT 1 OF THE cra IF THE INTERRUPT FLAG (BIT 7 OF cra) IS TO BE SET ON A NEGATIVE TRANSITION OF THE ca1 SIGNAL OR A "1" IF IT IS TO BE SET ON A POSITIVE TRANSITION. nOTE: a NEGATIVE TRANSITION IS DEFINED AS A TRANS- ITION FROM A HIGH (> 2.4V) TO A LOW (< 0.4v), AND A POSITIVE TRANSITION IS DEFINED AS A TRANSITION FROM A LOW TO A HIGH VOLTAGE. sETTING THE INTERRUPT FLAG WILL INTERRUPT THE PROCESSOR THROUGH irqa IF BIT 0 OF cra IS A 1 AS DESCRIBED PREVIOUSLY. ca2 CAN ACT AS A TOTALLY INDEPENDENT INTERRUPT INPUT OR AS A PERIPHERAL CONTROL OUTPUT. aS AN INPUT (cra, BIT 5 = 0) IT ACTS TO SET THE INTERRUPT FLAG, BIT 6 OF cra, TO A LOGIC 1 ON THE ACTIVE TRANSITION SELEC- TED BY BIT 4 OF cra. tHESE CONTROL REGISTER BITS AND INTERRUPT INPUTS SERVE THE SAME BASIC FUNCTION AS THAT DESCRIBED ABOVE FOR ca1. tHE INPUT SIGNAL SETS THE INTERRUPT FLAG WHICH SERVES AS THE LINK BETWEEN THE PERIPHERAL DEVICE AND THE PROCESSOR INTERRUPT STRUCTURE. tHE INTERRUPT DISABLE BIT ALLOWS THE PROCESSOR TO EXERCISE CONTROL OVER THE SYSTEM INTERRUPTS. iN THE oUTPUT MODE (cra, BIT 5 = 1), ca2 CAN OPERATE INDEPEN- DENTLY TO GENERATE A SIMPLE PULSE EACH TIME THE MICROPROCESSOR READS THE DATA ON THE pERIPHERAL a i/o PORT. tHIS MODE IS SELECTED BY SETTING cra, BIT 4 TO A 0 AND cra, BIT 3 TO A "1." tHIS PULSE OUTPUT CAN BE USED TO CONTROL THE COUNTERS, SHIFT REGISTERS, ETC. WHICH MAKE SEQUENTIAL DATA AVAILABLE ON THE pERIPHERAL INPUT LINES. -66- ============================================================================ a SECOND OUTPUT MODE ALLOWS ca2 TO BE USED IN CONJUNCTION WITH ca1 TO "HANDSHAKE" BETWEEN THE PROCESSOR AND THE PERIPHERAL DEVICE. oN THE a SIDE, THIS TECHNIQUE ALLOWS POSITIVE CONTROL OF DATA TRANSFERS FROM THE PERIPHERAL DEVICE INTO THE MICROPROCESSOR. tHE ca1 INPUT SIGNALS THE PRO- CESSOR THAT DATA IS AVAILABLE BY INTERRUPTING THE PROCESSOR. tHE PROCESSOR READS THE DATA AND SETS ca2 LOW. tHIS SIGNALS THE PERIPHERAL DEVICE THAT IT CAN MAKE NEW DATA AVAILABLE. tHIS TECHNIQUE IS DISCUSSED IN DETAIL IN cHAPTER 2. tHE FINAL OUTPUT MODE CAN BE SELECTED BY SETTING BIT 4 OF cra TO A 1. iN THIS MODE, ca2 IS A SIMPLE PERIPHERAL CONTROL OUTPUT WHICH CAN BE SET HIGH OR LOW BY SETTING BIT 3 OF cra TO A 1 OR A 0 RESPECTIVELY. tHE OPERATION OF ca1 AND ca2 IS SUMMARIZED IN THE NEXT SECTION. 1.5.4.2.2 pERIPHERAL b iNTERRUPT iNPUT/pERIPHERAL cONTROL lINES (cb1, cb2) cb1 OPERATES AS AN INTERRUPT INPUT ONLY IN THE SAME MANNER AS ca1. bIT 7 OF crb IS SET BY THE ACTIVE TRANSITION SELECTED BY BIT 0 OF crb. lIKEWISE, THE cb2 INPUT MODE OPERATES EXACTLY THE SAME AS THE ca2 INPUT MODES. tHE cb2 OUTPUT MODES, crb, BIT 5 = 1, DIFFER SOMEWHAT FROM THOSE OF ca2. tHE PULSE OUTPUT OCCURS WHEN THE PROCESSOR WRITES DATA INTO THE pERIPH- ERAL b oUTPUT rEGISTER. aLSO, THE "HANDSHAKING" OPERATES ON DATA TRANSFERS FROM THE PROCESSOR INTO THE PERIPHERAL DEVICE. tHE OPERATION OF cb1 AND cb2 IS SUMMARIZED IN THE NEXT SECTION. a MORE DETAILED DISCUSSION OF HANDSHAKING ON THE pERIPHERAL b i/o PORT IS CONTAINED IN cHAPTER 2 OF THIS MANUAL. 1.5.5 sUMMARY OF mcs6520 oPERATION 1.5.5.1 cONTROL rEGISTER oPERATION --------+--------+-----------------+--------+-------------- {$7c} 7 {$7c} 6 {$7c} 5 4 3 {$7c} 2 {$7c} 1 0 {$7c} +-------+--------+-----------------+--------+-------------+ cra {$7c} irqa1 {$7c} irqa2 {$7c} ca2 cONTROL {$7c} ddra {$7c} ca1 cONTROL {$7c} {$7c} {$7c} {$7c} ______^________ {$7c} aCCESS {$7c} _____^_____ {$7c} {$7c} {$7c} {$7c}/ \{$7c} {$7c}/ \{$7c} --------+--------+-----------------+--------+-------------- --------+--------+-----------------+--------+-------------- {$7c} 7 {$7c} 6 {$7c} 5 4 3 {$7c} 2 {$7c} 1 0 {$7c} +-------+--------+-----------------+--------+-------------+ crb {$7c} irqb1 {$7c} irqb2 {$7c} cb2 cONTROL {$7c} ddrb {$7c} cb1 cONTROL {$7c} {$7c} {$7c} {$7c} ______^________ {$7c} aCCESS {$7c} _____^_____ {$7c} {$7c} {$7c} {$7c}/ \{$7c} {$7c}/ \{$7c} --------+--------+-----------------+--------+-------------- cONTROL rEGISTER bIT dESIGNATIONS figure 1.29 -69- ============================================================================ ------------------+--------------------+------------------------------------- {$7c} cra (crb) {$7c} {$7c} {$7c} {$7c} {$7c} aCTIVE tRANSITION {$7c} irqa (irqb) {$7c} {$7c} bIT 1 bIT 0 {$7c} OF iNPUT sIGNAL* {$7c} iNTERRUPT oUTPUTS {$7c} {$7c} {$7c} {$7c} {$7c} +-----------------+--------------------+------------------------------------+ {$7c} {$7c} {$7c} {$7c} {$7c} 0 0 {$7c} NEGATIVE {$7c} dISABLE--REMAIN HIGH {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} eNABLED--GOES LOW WHEN BIT 7 {$7c} {$7c} {$7c} {$7c} IN cra (crb) IS SET BY ACTIVE {$7c} {$7c} 0 1 {$7c} NEGATIVE {$7c} TRANSITION OF SIGNAL ON ca0 {$7c} {$7c} {$7c} {$7c} (cbi) {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} 1 0 {$7c} POSITIVE {$7c} dISABLE--REMAIN HIGH {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} 1 1 {$7c} POSITIVE {$7c} eNABLE--AS EXPLAINED ABOVE {$7c} {$7c} {$7c} {$7c} {$7c} +-----------------+--------------------+------------------------------------+ {$7c} {$7c} {$7c} *nOTE 1: bIT 7 OF cra (crb) WILL HE SET TO A LOGIC 1 BY AN ACTIVE {$7c} {$7c} TRANSITION OF THE ca1 (cb1) SIGNAL. tHIS IS INDEPENDENT {$7c} {$7c} OF THE STATE OF bIT 0 IN cra (crb) {$7c} {$7c} {$7c} ----------------------------------------------------------------------------- cONTROL OFINTERRUPT iNPUTS ca1, cb1 figure 1.30 ------------------------+-------------------+-------------------------------- {$7c} cra (cre) {$7c} {$7c} {$7c} {$7c} {$7c} aCTIVE tRANSITION {$7c} irqa (irqb) {$7c} {$7c} bIT 5 bIT 4 bIT 3 {$7c} OF iNPUT sIGNAL* {$7c} iNTERRUPT oUTPUT {$7c} {$7c} {$7c} {$7c} {$7c} +-----------------------+-------------------+-------------------------------+ {$7c} {$7c} {$7c} {$7c} {$7c} 0 0 0 {$7c} NEGATIVE {$7c} dISABLE--REMAINS HIGH {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} eNABLED--GOES LOW WHEN BIT 6 {$7c} {$7c} {$7c} {$7c} IN cra (crb) IS SET BY ACTIVE {$7c} {$7c} 0 0 1 {$7c} NEGATIVE {$7c} TRANSITION OF SIGNAL ON ca2 {$7c} {$7c} {$7c} {$7c} (cb2) {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} 0 1 0 {$7c} POSITIVE {$7c} dISABLE--REMAINS HIGH {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} 0 1 1 {$7c} POSITIVE {$7c} eNABLE--AS EXPLAINED ABOVE {$7c} {$7c} {$7c} {$7c} {$7c} +-----------------------+-------------------+-------------------------------+ {$7c} {$7c} {$7c} *nOTE: bIT 6 OF cra (crb) WILL BE SET TO A LOGIC 1 BY AN ACTIVE {$7c} {$7c} TRANSITION OF THE ca2 (cb2) SIGNAL. tHIS IS INDEPENDENT {$7c} {$7c} OF THE STATE OF bIT 3 IN cra (crb). {$7c} {$7c} {$7c} ----------------------------------------------------------------------------- cONTROL OF ca2 (cb2) AS iNTERRUPT iNPUTS (bIT 5 "0") figure 1.31A -68- ============================================================================ ------------------------+-----------------+---------------------------------- {$7c} cra {$7c} {$7c} {$7c} {$7c} bIT 5 bIT 4 bIT 3 {$7c} mODE {$7c} dESCRIPTION {$7c} {$7c} {$7c} {$7c} {$7c} +-----------------------+-----------------+---------------------------------+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ca2 IS SET HIGH ON AN ACTIVE {$7c} {$7c} {$7c} {$7c} TRANSITION OF THE ca1 INTERRUPT {$7c} {$7c} {$7c} {$7c} INPUT SIGNAL AND SET LOW BY A {$7c} {$7c} 1 0 0 {$7c} "hANDSHAKE" {$7c} MICROPROCESSOR "rEAD a dATA" {$7c} {$7c} {$7c} ON rEAD {$7c} OPERATION. tHIS ALLOWS POSI- {$7c} {$7c} {$7c} {$7c} TIVE CONTROL OF DATA TRANSFERS {$7c} {$7c} {$7c} {$7c} FROM THE PERIPHERAL DEVICE TO {$7c} {$7c} {$7c} {$7c} THE MICROPROCESSOR. {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ca2 GOES LOW FOR ONE CYCLE {$7c} {$7c} {$7c} {$7c} AFTER A "rEAD a dATA" OPERA- {$7c} {$7c} 1 0 1 {$7c} pULSE oUTPUT {$7c} TION. tHIS PULSE CAN BE USED {$7c} {$7c} {$7c} {$7c} TO SIGNAL THE PERIPHERAL DE {$7c} {$7c} {$7c} {$7c} VICE THAT DATA WAS TAKEN. {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} 1 1 0 {$7c} mANUAL oUTPUT {$7c} ca2 SET LOW {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} 1 1 1 {$7c} mANUAL oUTPUT {$7c} ca2 SET HIGH {$7c} ------------------------+-----------------+---------------------------------- cONTROL OF ca2 oUTPUT mODES figure 1.31B ------------------------+-----------------+---------------------------------- {$7c} crb {$7c} {$7c} {$7c} {$7c} bIT 5 bIT 4 bIT 3 {$7c} mODE {$7c} dESCRIPTION {$7c} {$7c} {$7c} {$7c} {$7c} +-----------------------+-----------------+---------------------------------+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} cb2 IS SET LOW ON MICROPROCES {$7c} {$7c} {$7c} {$7c} SOR "wRITE b dATA" OPERATION {$7c} {$7c} {$7c} {$7c} AND IS SET HIGH BY AN ACTIVE {$7c} {$7c} 1 0 0 {$7c} "hANDSHAKE" {$7c} TRANSITION OF THE cb1 INTERRUPT {$7c} {$7c} {$7c} ON wRITE {$7c} INPUT SIGNAL. tHIS ALLOWS POSI-{$7c} {$7c} {$7c} {$7c} TIVE CONTROL OF DATA TRANSFERS {$7c} {$7c} {$7c} {$7c} FROM THE MICROPROCESSOR TO THE {$7c} {$7c} {$7c} {$7c} PERIPHERAL DEVICE. {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} cb2 GOES LOW FOR ONE CYCLE AFTER{$7c} {$7c} {$7c} {$7c} A MICROPROCESSOR "wRITE b dATA" {$7c} {$7c} 1 0 1 {$7c} pULSE oUTPUT {$7c} OPERATION. tHIS CAN BE USED TO {$7c} {$7c} {$7c} {$7c} SIGNAL THE PERIPHERAL DEVICE {$7c} {$7c} {$7c} {$7c} THAT DATA IS AVAILABLE. {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} 1 1 0 {$7c} mANUAL oUTPUT {$7c} cb2 SET LOW {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} 1 1 1 {$7c} mANUAL oUTPUT {$7c} cb2 SET HIGH {$7c} ------------------------+-----------------+---------------------------------- cONTROL OF cb2 oUTPUT mODES figure 1.31C -69- ============================================================================ 1.5.5.2 mcs6520 oPERATION IN mc6500 sYSTEMS a BRIEF REVIEW OF THE OVERALL OPERATION OF THE mcs6520 SHOULD SERVE TO TIE TOGETHER MANY OF THE DETAILS DISCUSSED PREVIOUSLY. dURING THE SYSTEM INITIALIZATION ROUTINE WHICH IS EXECUTED IN RESPONSE TO THE PROCESSOR reset SIGNAL, THE MICROPROCESSOR WILL WRITE A PATTERN OF 1'S AND 0'S INTO THE dATA dIRECTION rEGISTERS. tHIS WILL DETERMINE THOSE LINES WHICH ARE TO ACT AS INPUTS AND THOSE WHICH ARE TO ACT AS OUTPUTS. tHIS PATTERN WILL USUALLY BE FIXED FOR THE SYSTEM OPERATION. tHEREFORE, THE NEXT STEP WOULD BE TO SET THE VARIOUS OPERATING MODES, ACTIVE TRANSITIONS, ETC. WHICH ARE CONTROLLED BY THE cONTROL rEGISTERS. aT THE SAME TIME THE dATA dIRECTION rEGISTER aCCESS cONTROL bIT CAN BE SET TO A 1 TO ALLOW THE PROCESSOR TO CONTROL THE pERIPHERAL pORTS DURING SYSTEM OPERATION. tHE INTERRUPTS WILL NORMALLY REMAIN DISABLED UNTIL THE ENTIRE SYSTEM IS INITIALIZED. aT THIS TIME, THE INTERRUPTS ARE ENABLED AND FULL SYSTEM OPERATION BEGINS. dURING SYSTEM OPERATION, THE MICROPROCESSOR WILL INTERROGATE THE SWITCHES, SENSORS, ETC. IN THE PERIPHERAL DEVICE BY READING THE DATA ON THE pERIPHERAL iNPUT LINES. bINARY OR DECIMAL DATA MAY HE TRANSFERRED INTO THE MICROPROCESSOR IN THE SAME WAY. aT THE SAME TIME THE VARIOUS LIGHTS, MOTORS, SOLENOIDS, ETC. ON THE PERIPHERAL DEVICE ARE CONTROLLED BY WRITING DATA INTO THE APPROPRIATE BITS OF THE pERIPHERAL oUTPUT rEGISTERS. tHE ENTIRE SEQUENCE OF OPERATIONS IS DETERMINED BY THE PROGRAMMER TO CONTROL A PARTICULAR PERIPH- ERAL DEVICE IN A DEFINED MANNER. tHE VARIOUS REGISTERS, GATES, ETC. IN THE iNTERFACE dEVICE ACT PRIMARILY AS A LINK BETWEEN THE INTERNAL PROCESSOR OPER- ATIONS AND THE VARIOUS INPUTS AND OUTPUTS ON THE PERIPHERAL DEVICES BEING CONTROLLED. -70- ============================================================================ 1.6 peripheral interface/memory device - mcs6530 1.6.1 iNTRODUCTION tHE mcs6530 IS DESIGNED TO OPERATE IN CONJUNCTION WITH THE mcs650x mICROPROCESSOR. iT IS COMPRISED OF A MASK PROGRAMMABLE 1024 X 8 rom, A 64 X 8 ram, TWO 8 BIT BI-DIRECTIONAL PORTS CAPABLE OF DIRECTLY INTER- FACING THE mICROPROCESSOR UNIT AND PERIPHERAL DEVICES AND A PROGRAMMABLE INTERVAL TIMER WITH INTERRUPT, CAPABLE OF TIMING IN VARIOUS INTERVALS FROM 1 TO 262,144 CLOCK PERIODS. tHE i/o CONFIGURATION, THE INTERVAL TIMER AND INTERRUPT CAPABILITY ARE UNDER SOFTWARE CONTROL. * 8 BIT BI-DIRECTIONAL dATA bUS FOR COMMUNICATION WITH THE MICROPROCESSOR UNIT. * tWO 8 BIT BI-DIRECTIONAL PORTS FOR DIRECT INTERFACE TO PERIPHERALS. * tWO i/o pERIPHERAL dATA dIRECTION rEGISTERS * pROGRAMMABLE iNTERVAL tIMER FROM 1 TO 256 X 1024 CLOCK PERIODS. * pROGRAMMABLE iNTERVAL tIMER iNTERRUPT * c mos cOMPATIBLE pERIPHERAL lINES * pERIPHERAL pINS WITH dIRECT tRANSISTOR dRIVE cAPABILITY * tHREE-sTATE dATA pINS * uP TO 7k CONTIGUOUS rom WITH NO EXTERNAL DECODING * 1024 X 8 rom * 64 X 8 sTATIC ram 1.6.2 pINOUT dESCRIPTION fIGURE 1.33 IS THE PINOUT DIAGRAM OF THE mcs6530. ___ 1.6.2.1 rESET (res) ___ dURING SYSTEM INITIALIZATION A lOGIC "o" ON THE res INPUT WILL CAUSE A ZEROING OF ALL i/o REGISTERS. tHIS IN TURN WILL CAUSE ALL i/o BUSES TO ACT AS INPUTS THUS PROTECTING EXTERNAL COMPONENTS FROM POSSIBLE DAMAGE AND ERRONEOUS DATA WHILE THE SYSTEM IS BEING CONFIGURED UNDER SOFTWARE CONTROL. tHE dATA bUS bUFFERS ARE PUT INTO AN off-state DURING rESET. iNTERRUPT IS DISABLED WHEN RESET. tHE res SIGNAL MUST BE HELD LOW FOR AT LEAST ONE CLOCK PERIOD WHEN RESET IS REQUIRED. -71- ============================================================================ --------------------------- vss ---+ 1 40+---\ pa1 ---+ +--- {$7c} pa0 <----->---+ 2 39+--- {$7c} pa2 ---+ +--- {$7c} O2 ------>---+ 3 38+--- {$7c} pa3 ---+ +--- {$7c} rs0 ------>---+ 4 37+--- ><--> pa4 ---+ +--- {$7c} a9 ---+ 5 36+--- {$7c} pa5 ---+ +--- {$7c} a8 ---+ 6 35+--- {$7c} pa6 ---+ +--- {$7c} a7 ---+ 7 34+--- {$7c} pa7 ---+ +---/ a6 ---+ 8 33+---\ db0 ---+ +--- {$7c} r/w ---+ 9 32+--- {$7c} db1 ---+ +--- {$7c} a5 ---+10 31+--- {$7c} db2 ---+ mcs6530 +--- {$7c} a4 ---+11 30+--- {$7c} db3 ---+ +--- ><--> a3 ---+12 29+--- {$7c} db4 ---+ +--- {$7c} a2 ---+13 28+--- {$7c} db5 ---+ +--- {$7c} a1 ---+14 27+--- {$7c} db6 ---+ +--- {$7c} a0 ---+15 26+--- {$7c} db7 ___ ---+ +---/ res ------>---+16 25+---\ pb0 ___ ---+ +--- {$7c} irq/pb7 <----->---+17 24+--- {$7c} pb1 ---+ +--- {$7c} cs1/pb6 <----->---+18 23+--- ><--> pb2 ---+ +--- {$7c} cs2/pb5 <----->---+19 22+--- {$7c} pb3 ---+ +--- {$7c} vcc ---+20 21+--- {$7c} pb4 ---+ +---/ --------------------------- mcs6530 pINOUT dESIGNATION figure 1.32 -72- ============================================================================ 1.6.2.2 iNPUT cLOCK tHE INPUT CLOCK IS A SYSTEM pHASE tWO CLOCK WHICH CAN BE EITHER A LOW LEVEL CLOCK (vil < 0.4, vih > 2.4) OR HIGH LEVEL CLOCK (vil < 0.2, +.3 vih = vCC-.2) 1.6.2.3 rEAD/wRITE (r/w) tHE r/w SIGNAL IS SUPPLIED BY THE MICROPROCESSING UNIT AND IS USED TO CONTROL THE TRANSFER OF DATA TO AND FROM THE MICRAPROCESSING UNIT AND THE mcs6530. a HIGH ON THE r/w PIN ALLOWS THE PROCESSOR TO READ (WITH PRO- PER ADDRESSING) THE DATA SUPPLIED BY THE mcs6530. a LOW ON THE r/w PIN ALLOWS A WRITE (WITH PROPER ADDRESSING) TO THE mcs6530. ___ 1.6.2.4 iNTERRUPT rEQUEST (irq) tHE irq PIN IS AN INTERRUPT PIN FROM THE INTERVAL TIMER. tHIS SAME PIN, IF NOT USED AS AN INTERRUPT, CAN BE USED AS A PERIPHERAL i/o PIN (pb7). wHEN USED AS AN INTERRUPT, THE PIN SHOULD BE SET UP AS AN INPUT BY THE DATA DIRECTION REGISTER. tHE PIN WILL BE NORMALLY HIGH WITH A LOW INDI- CATING AN INTERRUPT FROM THE mcs6530. aN EXTERNAL PULL-UP DEVICE IS NOT REQUIRED; HOWEVER, IF COLLECTOR-or'D WITH OTHER DEVICES, THE INTERNAL PULL- UP MAY BE OMITTED WITH A MASK OPTION. 1.6.2.5 dATA bUS (d0-d7) tHE mcs6530 HAS EIGHT BI-DIRECTIONAL DATA PINS (d0-d7). tHESE PINS CONNECT TO THE SYSTEM'S DATA LINES AND ALLOW TRANSFER OF DATA TO AND FROM THE MICROPROCESSOR UNIT. tHE OUTPUT BUFFERS REMAIN IN THE OFF STATE EXCEPT WHEN A rEAD OPERATION OCCURS. 1.6.2.6 pERIPHERAL dATA pORTS tHE mcs6530 HAS 16 PINS AVAILABLE FOR PERIPHERAL i/o OPERATIONS. eACH PIN IS INDIVIDUALLY SOFTWARE PROGRAMMABLE TO ACT AS EITHER AN INPUT OR AN OUTPUT. tHE 16 PINS ARE DIVIDED INTO 2 8-BIT PORTS, pa0-pa7 AND pb0-pb7 pb5, pb6 AND pb7 ALSO HAVE OTHER USES WHICH WILL BE DISCUSSED IN sECTION 1.6.4. tHE PINS ARE SET UP AS AN INPUT BY WRITING A "0" INTO THE CORRE- SPONDING BIT IN THE DATA DIRECTION REGISTER. a "1" INTO THE DATA DIRECTION REGISTER WILL CAUSE ITS CORRESPONDING BIT TO BE AN OUTPUT. wHEN IN THE INPUT MODE, THE PERIPHERAL OUTPUT BUFFERS ARE IN THE "1" STATE AND A PULL-UP DEVICE ACTS AS LESS THAN ONE ttl LOAD TO THE PERIPHERAL DATA LINES. oN A rEAD OPERATION, THE MICROPROCESSOR UNIT READS THE PERIPHERAL PIN. wHEN THE -73- ============================================================================ PERIPHERAL DEVICE GETS INFORMATION FROM THE mcs6530 IT RECEIVES DATA STORED IN THE DATA REGISTER. tHE MICROPROCESSOR WILL READ CORRECT INFORMATION IF THE PERIPHERAL LINES ARE GREATER THAN 2.0 VOLTS FOR A "1" AND LESS THAN 0.8 VOLTS FOR A "0" AS THE PERIPHERAL PINS ARE ALL ttl COMPATIBLE. pINS pa0 AND pb0 ARE ALSO CAPABLE OF SOURCING 3 Ma AT 1.5v, THUS MAKING THEM CAPABLE OF dARLINGTON DRIVE. 1.6.2.7 aDDRESS lINES (a0-a9) tHERE ARE 10 ADDRESS PINS. iN ADDITION TO THESE 10, THERE IS THE rom select PIN. tHE ABOVE PINS, a0-a9 AND rom select, ARE ALWAYS USED AS ADDRESSING PINS. tHERE ARE 2 ADDITIONAL PINS WHICH ARE MASK PROGRAMMABLE AND CAN BE USED EITHER INDIVIDUALLY OR TOGETHER AS chip selects. tHEY ARE PINS pb5 AND pb6. wHEN USED AS PERIPHERAL DATA PINS THEY CANNOT BE USED AS CHIP SELECTS. 1.6.3 iNTERNAL oRGANIZATION a BLOCK DIAGRAM OF THE INTERNAL ARCHITECTURE IS SHOWN IN fIGURE 1.33. tHE mcs6530 IS DIVIDED INTO FOUR BASIC SECTIONS, ram, rom, i/o AND timer. tHE ram AND rom INTERFACE DIRECTLY WITH THE MICROPROCESSOR THROUGH THE SYS- TEM DATA BUS AND ADDRESS LINES. tHE i/o SECTION CONSISTS OF 2 8-BIT HALVES. eACH HALF CONTAINS A dATA dIRECTION rEGISTER (ddr) AND AN i/o rEGISTER. tHE ddr CONTROLS THE PERIPHERAL OUTPUT BUFFERS. a "1" WRITTEN INTO THE ddr SETS UP THE CORRESPONDING PERIPHERAL BUFFER AS AN OUTPUT BUFFER. bY THIS, IT IS MEANT THAT ANYTHING THEN WRITTEN INTO THE i/o rEGISTER WILL APPEAR ON THAT CORRESPONDING PERIPHERAL PIN. a "0" WRITTEN INTO THE ddr INHIBITS THE OUTPUT BUFFER FROM TRANSMITTING DATA FROM THE i/o rEGISTER. tHE OUTPUT BUFFER REMAINS IN THE HIGH STATE MAKING IT READY TO RECEIVE DATA ON THE PERIPHERAL LINES. iT SHOULD BE NOTED THAT THE MICROPROCESSOR, WHEN READING THE i/o rEGISTER, IS IN FACT READING THE pERIPHERAL pIN AND NOT THE i/o rEGISTER. tHE ONLY WAY THE i/o rEGISTER DATA CAN BE CHANGED IS BY A MICROPROCESSOR wRITE OPERATION. tHE rEGISTER IS NOT AFFECTED BY THE DATA ON THE pERIPH- ERAL pIN. 1.6.3.1 rom--1k bYTE (8k bITS) tHE 8k rom IS IN A 1024 X 8 CONFIGURATION. aDDRESS LINES a0-a9, AS WELL AS rs0 ARE NEEDED TO ADDRESS THE ENTIRE rom. wITH THE ADDITION OF -74- ============================================================================ mcs6530 iNTERNAL aRCHITECTURE figure 1.33 -75- ============================================================================ cs1 AND cs2, UP TO SEVEN mcs6530S MAY BE ADDRESSED, GIVING 7168 X 8 BITS OF CONTIGUOUS rom. 1.6.3.2 ram--64 bYTES (512 bITS) a 64 X 8 STATIC ram IS CONTAINED ON THE mcs6530. iT IS ADDRESSED BY a0-a5 (bYTE sELECT), rs0, a6, a7, a8, a9 AND, DEPENDING ON THE NUMBER OF CHIPS IN THE SYSTEM, cs1 AND cs2. 1.6.3.3 iNTERNAL pERIPHERAL rEGISTERS tHERE ARE FOUR INTERNAL REGISTERS, TWO DATA DIRECTION REGISTERS AND TWO PERIPHERAL i/o DATA REGISTERS. tHE TWO DATA DIRECTION REGISTERS (a SIDE AND b SIDE) CONTROL THE DIRECTION OF DATA INTO AND OUT OF THE PERIPH- ERAL PINS. fOR EXAMPLE, A "1" LOADED INTO DATA DIRECTION REGISTER a, POSI- TION 3 SETS UP PERIPHERAL PIN pa3 AS AN OUTPUT. iF A "0" HAD BEEN LOADED INSTEAD, pa3 WOULD BE CONFIGURED AS AN INPUT. tHE TWO DATA i/o REGISTERS ARE USED TO LATCH DATA FROM THE DATA BUS DURING A wRITE OPERATION UNTIL THE PERIPHERAL DEVICE CAN READ THE DATA SUPPLIED BY THE MICROPROCESSOR UNIT. aLTHOUGH DURING A rEAD OPERATION THE MICROPROCESSOR UNIT READS THE PERIPH- ERAL PIN, THE ADDRESS IS THE SAME AS THE REGISTER. fOR THOSE PINS PRO- GRAMMED AS OUTPUTS BY THE DATA DIRECTION REGISTERS, THE DATA ON THE PINS WILL BE THE SAME AS THAT IN THE i/o REGISTER. 1.6.3.4 iNTERVAL tIMER tHE tIMER SECTION OF THE mcs6530 CONTAINS THREE BASIC PARTS: PRE- LIMINARY DIVIDE DOWN REGISTER, PROGRAMMABLE 8-BIT REGISTER AND INTERRUPT LOGIC. tHESE ARE ILLUSTRATED IN fIGURE 1.34. tHE INTERVAL TIMER CAN BE PROGRAMMED TO COUNT UP TO 256 TIME INTERVALS. eACH TIME INTERVAL CAN BE EITHER 1t, 8t, 64t OR 1024t INCRE- MENTS, WHERE t IS THE SYSTEM CLOCK PERIOD. wHEN A FULL COUNT IS REACHED, AN INTERRUPT FLAG IS SET TO A LOGIC "1." aFTER THE INTERRUPT FLAG IS SET THE INTERNAL CLOCK BEGINS COUNTING DOWN TO A MAXIMUM OF -255t. tHUS, AFTER THE INTERRUPT FLAG IS SET, A rEAD OF THE TIMER WILL TELL HOW LONG SINCE THE FLAG WAS SET UP TO A MAXIMUM OF 255t. wHEN WRITING TO THE TIMER, THE HIGH ORDER 8 BITS OF THE TIMER ARE WRITTEN BY THE SYSTEM DATA BUS. iF A COUNT OF 52 TIME INTERVALS WERE TO BE COUNTED, 0 0 1 1 0 1 0 0 WOULD BE WRITTEN INTO THE TIMER SECTION. tHE TIME INTERVALS OF 1, 8, 64 OR 1024t ARE DECODED FROM ADDRESS LINES a0 AND a1 AT THIS SAME TIME. aDDRESS LINE a3, IF HIGH DURING THIS WRITE OPERATION, -76- ============================================================================ 256 iNTERVALS ___________^___________ / \ d7 d6 d5 d4 d3 d2 d1 d0 r/w a1 a0 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} V V V V V V V V {$7c} V V ------------------------- {$7c} ---------------- {$7c} {$7c}<-----+----->{$7c} {$7c} -----+ programmable {$7c} {$7c} dividedown {$7c}<---O2 {$7c} {$7c} register {$7c}<------------+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -+--+--+--+--+--+--+--+-- ---------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} 1t, 8t, 64t, OR 1024t iNTERVALS {$7c} {$7c} V V V V V V V {$7c} {$7c} d6 d5 d4 d3 d2 d1 d0 {$7c} {$7c} {$7c} {$7c} V {$7c} -------- {$7c} a3 -->{$7c} {$7c} {$7c} {$7c} +--+-->d7 r/w-->{$7c} {$7c} ----+--- {$7c} V ___ irq bASIC eLEMENTS OF iNTERVAL tIMER fig ure 1.34 -77- ============================================================================ ENABLES THE INTERRUPT FLAG ONTO PIN pb7. pb7 SHOULD BE PROGRAMMED AS AN INPUT IF IT IS TO BE USED AS AN INTERRUPT PIN. pb7 GOES LOW WHEN AN INTER- RUPT OCCURS. wHEN THE TIMER IS READ PRIOR TO THE INTERRUPT FLAG BEING SET, THE NUMBER OF TIME INTERVALS REMAINING WILL BE READ, I.E., 51, 50, 49, ETC. sHOULD THE TIMER BE READ WHEN INTERRUPT OCCURS, THE VALUE READ WOULD BE 1 1 1 1 1 1 1 1. aFTER INTERRUPT, THE TIMER REGISTER DECREMENTS AT A DIVIDE BY "1" RATE OF THE SYSTEM CLOCK. iF AFTER INTERRUPT, THE TIMER IS READ AND A VALUE OF 1 1 1 0 0 1 0 0 IS READ, THE TIME SINCE INTERRUPT IS 28t. tHE VALUE READ IS IN TWO'S COMPLEMENT. vALUE READ = 1 1 1 0 0 1 0 0 cOMPLEMENT = 0 0 0 1 1 0 1 1 add 1 = 0 0 0 1 1 1 0 0 = 28. tHUS, TO ARRIVE AT THE TOTAL ELAPSED TIME, MERELY DO A TWO'S COMPLEMENT ADD TO THE ORIGINAL TIME WRITTEN INTO THE TIMER. aGAIN, ASSUME TIME WRITTEN AS 0 0 1 1 0 1 0 0 (= 52). wITH A DIVIDE BY 8, TOTAL TIME TO INTERRUPT IS (52 X 8) + 1 = 417t. tOTAL ELAPSED TIME WOULD BE 416t + 28t = 444t, ASSUM- ING THE VALUE READ AFTER INTERRUPT WAS 1 1 1 0 0 1 0 0. aFTER INTERRUPT, WHENEVER THE TIMER IS WRITTEN OR READ THE INTER- RUPT IS RESET. hOWEVER, THE READING OR WRITING OF THE TIMER AT THE SAME TIME INTERRUPT OCCURS WILL NOT RESET THE INTERRUPT FLAG. fIGURE 1.35 ILLUSTRATES AN EXAMPLE OF INTERRUPT. wHEN READING THE TIMER AFTER AN INTERRUPT, a3 SHOULD BE LOW SO AS TO DISABLE THE irq PIN. tHIS IS DONE SO AS TO AVOID FUTURE INTERRUPTS UNTIL AFTER ANOTHER wRITE TIMER OPERATION. 1.6.4 aDDRESSING aDDRESSING OF THE mcs6530 OFFERS MANY VARIATIONS TO THE USER FOR GREATER FLEXIBILITY. tHE USER MAY CONFIGURE HIS SYSTEM WITH ram IN LOWER MEMORY, rom IN HIGHER MEMORY, AND i/o REGISTERS WITH INTERVAL TIMERS BETWEEN THE EXTREMES. tHERE ARE 10 ADDRESS LINES (a0-a9). iN ADDITION, THERE IS THE POSSIBILITY OF 3 ADDITIONAL ADDRESS LINES TO BE USED AS CHIP-SELECTS AND TO DISTINGUISH BETWEEN rom, ram, i/o AND INTERVAL TIMER. tWO OF THE ADDI- TIONAL LINES ARE CHIP-SELECTS 1 AND 2 (cs1 AND cs2). tHE CHIP-SELECT PINS CAN ALSO BE pb5 AND pb6. wHETHER THE PINS ARE USED AS CHIP-SELECTS OR PERIPHERAL i/o PINS IS A MASK OPTION AND MUST BE SPECIFIED WHEN ORDERING THE PART. bOTH PINS ACT INDEPENDENTLY OF EACH OTHER IN THAT EITHER OR BOTH -78- ============================================================================ (1) (2) (3) (4) (5) ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -- ---- ---- ---- -//- ---- -//- ---- -//- ---- --- 0 1 2 3 213 214 415 416 500 501 ---- write t {$7c} {$7c} -- --------------------------------------------------------- ------------------------------------------- irq {$7c} ------------------- should the programmable timer register be read at the times noted on the diagram above, it would contain: (1) dATA WRITTEN INTO INTERVAL TIMER IS 001100100 = 52 a DIVIDE BY 8 PRE-SCALE IS USED (2) 00011001 = 25 52 - 213/8 - 1 = 52 - 26 - 1 = 25 (3) 00000000 = 0 52 - 415/8 - 1 = 52 - 51 - 1 = 0 (4) iNTERRUPT HAS OCCURRED AT O2 PULSE #416 (5) 10101100 tWO; COMPLEMENT = 01010100 = 84 84 + (52X8) = 500 eXAMPLE OF iNTERRUPT gENERATED BY iNTERVAL tIMER figure 1.35 -79- ============================================================================ PINS MAY BE DESIGNATED AS A CHIP-SELECT. tHE THIRD ADDITIONAL ADDRESS LINE IS rs0. tHE mcs6502 AND mcs6530 IN A 2-CHIP SYSTEM WOULD USE rs0 TO DIS- TINGUISH BETWEEN rom AND NON-rom SECTIONS OF THE mcs6530. wITH THE AD- DRESSING PINS AVAILABLE, A TOTAL OF 7k CONTIGUOUS rom MAY BE ADDRESSED WITH NO EXTERNAL DECODE. bELOW IS AN EXAMPLE OF A 1-CHIP AND A 7-CHIP mcs6530 aDDRESSING sCHEME. 1.6.4.1 oNE-cHIP aDDRESSING fIGURE 1.36 ILLUSTRATES A 1-CHIP SYSTEM DECODE FOR THE mcs6530. 1.6.4.2 sEVEN-cHIP aDDRESSING iN THE 7-CHIP SYSTEM THE OBJECTIVE WOULD BE TO HAVE 7k OF CONTIGU- OUS rom, WITH ram IN LOW ORDER MEMORY. tHE 7k OF rom COULD BE PLACED BE- TWEEN ADDRESSES 65,536 AND 1024. fOR THIS CASE, ASSUME a13, a14 AND a15 ARE ALL 1 WHEN ADDRESSING rom, AND 0 WHEN ADDRESSING ram OR i/o. tHIS WOULD PLACE THE 7k rom BETWEEN aDDRESSES 65,535 AND 57,367. tHE 2 PINS DESIGNATED AS CHIP-SELECT OR i/o WOULD BE MASKED PROGRAMMED AS CHIP-SELECT PINS. pIN rs0 WOULD BE CONNECTED TO ADDRESS LINE a10. pINS cs1 AND cs2 WOULD BE CONNECTED TO ADDRESS LINES a11 AND a12 RESPECTIVELY. sEE fIGURE 1.37. tHE TWO EXAMPLES SHOWN WOULD ALLOW ADDRESSING OF THE rom AND ram; HOWEVER, ONCE THE i/o TIMER HAS BEEN ADDRESSED, FURTHER DECODING IS NECS- SARY TO SELECT WHICH OF THE i/o REGISTERS ARE DESIRED, AS WELL AS THE COD- a MG OF THE INTERVAL TIMER. 1.6.4,3 i/o rEGISTER--tIMER aDDRESSING fIGURE 1.38 ILLUSTRATES THE ADDRESSING DECODING FOR THE INTERNAL ELEMENTS AND TIMER PROGRAMMING. aDDRESS LINE a2 DISTINGUISHES i/o REGIS- TERS FROM THE TIMER. wHEN a2 IS LOW AND i/o TIMER SELECT IS HIGH, THE i/o REGISTERS ARE ADDRESSED. oNCE THE i/o REGISTERS ARE ADDRESSED, ADDRESS LINES a1 AND a0 DECODE THE DESIRED REGISTER. wHEN THE TIMER IS SELECTED a1 AND a0 DECODE THE DIVIDE BY MATRIX. tHIS IS DISCUSSED FURTHER IN THE tIMER sECTION. iN ADDITION, aDDRESS a3 IS USED TO ENABLE THE INTERRUPT FLAG TO pb7. -80- ============================================================================ [ pICTURE OF 6530 HOW MASK CAN BE PROGRAMMED ] a. x INDICATES MASK PROGRAMMING I.E. rom SELECT = cs1 X rs0 ___ ___ __ ram SELECT = cs1 X rs0 X a9 X a7 X a6 ___ ___ i/o timer select = cs1 X rs0 X a9 X a8 X a7 X a6 b. nOTICE THAT a8 IS A DON'T CARE FOR ram SELECT c. cs2 CAN BE USED AS pb5 IN THIS EXAMPLE. mcs6530 oNE cHIP aDDRESS eNCODING dIAGRAM figure 1.36 -81- ============================================================================ tHE ADDRESSING OF THE rom SELECT, ram SELECT AND i/o tIMER SELECT LINES WOULD BE AS FOLLOWS: cs2 cs1 rs0 a12 a11 a1o a9 a8 a7 a6 mcs6530 #1, rom select 0 0 1 x x x x ram select 0 0 0 0 0 0 0 i/o timer 0 0 0 1 0 0 0 mcs6530 #2, rom select 0 1 0 x x x x ram select 0 0 0 0 0 0 1 i/o timer 0 0 0 1 0 0 1 mcs6530 #3, rom select 0 1 1 X X X X ram select 0 0 0 0 0 1 0 i/o timer 0 0 0 1 0 1 0 mcs6530 #4, rom select 1 0 0 x x x x ram select 0 0 0 0 0 1 1 i/o timer 0 0 0 1 0 1 1 mcs6530 #5, rom select 1 0 1 x x x x ram select 0 0 0 0 1 0 0 i/o timer 0 0 0 1 1 0 0 nc56530 #6, rom select 1 1 0 X X X X ram select 0 0 0 0 1 0 1 i/o timer 0 0 0 1 1 0 1 mcs6530 #7, rom select 1 1 1 X X X X ram select 0 0 0 0 1 1 0 i/o timer 0 0 0 1 1 1 0 * ram SELECT FOR mcs6530 #5 WOULD READ = a120a110a10.a9.a8.a7.a6 mcs6530 sEVEN cHIP aDDRESSING sCHEME figure 1.37 -82- ============================================================================ addressing decode rom select ram select i/o timer select r/w a3 a2 a1 a0 read rom 1 0 0 1 X X X X write ram 0 1 0 0 X X X X read ram 0 1 0 1 x x x x write ddra 0 0 1 0 x 0 0 1 read ddra 0 0 1 1 x 0 0 1 write ddrb 0 0 1 0 x 0 1 1 read ddrb 0 0 1 1 x 0 1 1 write per. reg. a 0 0 1 0 X 0 0 0 read per. reg. a 0 0 1 1 x 0 0 0 write per. reg. b 0 0 1 0 X 0 1 0 read per. reg. b 0 0 1 1 X 0 1 0 write timer 1t w/irq TO pb7 0 0 1 0 1 1 0 0 8t wo/irq TO pb7 0 0 1 0 0 1 0 1 64t wiirq TO pb7 0 0 1 0 1 1 1 0 1024t wo/irq TO pb7 0 0 1 0 0 1 1 1 read timer disab1e irq to pb7 0 0 1 1 0 1 X 0 read interrupt flag 0 0 1 1 x 1 X 1 aDDRESSING dECODE FOR i/o rEGISTER AND tIMER figure 1.38 -83- ============================================================================ blank -83- ============================================================================ chapter 2 configuring the microcomputer system 2.1 the system configuration task tHE FIRST PART OF ANY MICROPROCESSOR-BASED DESIGN EFFORT IS THE SYSTEM CON- FIGURATION TASK. iN FACT, THIS PROBABLY REQUIRES MORE CREATIVITY FROM THE DE- SIGNER THAN ANY OTHER PART OF THE DESIGN EFFORT. tHE GOAL OF THE SYSTEM CON- FIGURATION EFFORT IS THE GENERATION OF A LIST OF COMPONENTS WHICH WILL MAKE UP THE SYSTEM, A DETAILED INTERCONNECT DIAGRAM AND A DETAILED DESCRIPTION OF THE TOTAL SYSTEM OPERATION. tHIS INCLUDES A DEFINITION OF HOW THE PROCESSOR WILL CONTROL THE PERIPHERAL DEVICES AS WELL AS A DEFINITION OF THE INTERNAL OPERA- TIONS TO BE PERFORMED. tHIS DOES NOT INCLUDE DETAILED IMPLEMENTATION OF THE DESIGN SUCH AS LAYING OUT PRINTED CIRCUIT BOARDS AND WRITING PROGRAMS, BUT DOES INVOLVE ENOUGH ANALYSIS OF THE TOTAL OPERATION TO ASSURE THAT THE SYSTEM WILL OPERATE PROPERLY AFTER ALL THE HARDWARE AND SOFTWARE IS ASSEMBLED. tHE TECHNICALLY BASED SELECTION OF COMPONENTS AND THE DEFINITION OF THE GENERAL OPERATION OF THE SYSTEM MUST BE BASED ON CONSIDERATION OF TWO FACTORS. tHESE ARE: 1. sYSTEM SPEED REQUIREMENTS 2. sYSTEM INPUT/OUTPUT REQUIREMENTS bOTH OF THESE FACTORS ARE INTERRELATED. tHEREFORE, IT WILL USUALLY BE NECESSARY TO DEFINE AN i/o CONFIGURATION AND THEN VERIFY THAT THE PROCESSOR CAN OPERATE AT THE SPEED REQUIRED BY THE PERIPHERAL DEVICES. iF THERE APPEARS TO BE ANY DIFFI- CULTY WITH THE i/o OPERATION, THIS STRUCTURE MUST BE RE-DEFINED AND RE-ANALYZED. iN ADDITION TO THE SPEED REQUIREMENTS OF THE i/o DEVICES, THERE ARE ALSO GENERAL SPEED REQUIREMENTS FOR THE INTERNAL PROCESSOR OPERATIONS (ARITHMETIC OPERATIONS, DATA MANIPULATION, ETC.). tHIS SPEED REQUIREMENT IS USUALLY SOME- WHAT MORE FLEXIBLE THAN THAT ASSOCIATED WITH i/o BUT IT SHOULD BE DEFINED ALONG WITH ANY OTHER SYSTEM REQUIREMENTS. tHE ULTIMATE TEST OF SYSTEM SPEED MUST WAIT FOR THE GENERATION OF BOTH THE HARDWARE AND THE PROGRAM; HOWEVER, THE SYSTEM REQUIREMENTS AND CAPABILITY MUST BE ANALYZED VERY EARLY IN THE SYSTEM DEVELOP- MENT PROCESS TO ASSURE THAT NO PROBLEMS WILL ARISE DURING THE LAST STAGES OF THE DESIGN. -84- ============================================================================ 2.2 input/output techniques 2.2.1 tHE gENERAL pURPOSE iNPUT/oUTPUT (i/o) pORT aLTHOUGH THE CONCEPT OF THE i/o PORT WAS INTRODUCED BRIEFLY IN sEC- TION 1, AND THE OPERATION OF TWO mcs6500 FAMILY DEVICES WHICH PROVIDE GEN- ERAL PURPOSE i/o CAPABILITY HAS BEEN DISCUSSED IN sECTIONS 1.5 AND 1.6, LITTLE HAS BEEN SAID ABOUT WHAT FACTORS MUST BE CONSIDERED WHEN CONFIGUR- ING AN i/o STRUCTURE USING THESE DEVICES. tHE GENERAL PURPOSE i/o PORT CONSISTS OF EIGHT LINES, EACH OF WHICH CAN ACT AS EITHER AN INPUT OR AN OUTPUT. aS AN INPUT, EACH LINE CAN DETECT THE STATE OF ONE SWITCH OR CAN DETECT ONE BIT OF DATA. aS AN OUTPUT, EACH LINE CAN CONTROL ONE LIGHT, SOLENOID, ETC. OR CAN PROVIDE ONE BIT OF DATA TO A PERIPHERAL DEVICE. iF THIS TECHNIQUE IS USED IN PERIPHERAL CONTROL, THE OPERATION OF EACH LINE IS TOTALLY DEFINED IN THE SYSTEM PROGRAM. fOR MOST SYSTEMS, THE GENERAL PURPOSE INTERFACE DEVICE PROVIDES MORE THAN ADEQUATE SPEED AND FLEXIBILITY TO SOLVE THE ENTIRE PERIPHERAL INTER- FACE PROBLEM. uSUALLY, A COST SAVINGS CAN BE REALIZED BECAUSE OF THE RE- DUCED COMPONENT COST AND THE NECESSITY OF STOCKING ONLY ONE TYPE OF INTER- FACE DEVICE. iN ADDITION, USE OF THE GENERAL PURPOSE PERIPHERAL INTERFACE DEVICE ALLOWS THE DESIGNER TO TAILOR THE OPERATION OF THE INTERFACE DEVICE TO FIT THE PROBLEM AT HAND. tHE ULTIMATE COMPONENT SELECTION MUST BE PRECEDED BY A STUDY OF EACH SECTION OF THE SYSTEM INPUT/OUTPUT STRUCTURE AND A STUDY OF THE OVERALL SYS- TERN PERFORMANCE. uLTIMATELY, THE SET OF GENERAL PURPOSE AND SPECIAL PURPOSE PERIPHERAL INTERFACE DEVICES SELECTED FOR A SYSTEM MUST BE CHOSEN TO MINI- MIZE TOTAL COST WHILE ASSURING SATISFACTORY SYSTEM PERFORMANCE. -88- ============================================================================ pROCESSOR SPEED IS A FUNCTION OF TWO THINGS. tHE FIRST IS SIMPLY THE NUM- BER OF INSTRUCTIONS REQUIRED TO PERFORM THE DESIRED OPERATIONS. tHE SECOND IS THE PERCENTAGE OF PROCESSOR TIME REQUIRED TO SERVICE INTERRUPTS. tHE TYPICAL SYSTEM MAY EMPLOY SEVERAL INTERRUPT SIGNALS WHICH OCCUR AT FIXED INTERVALS. aT TIMES, THESE MAY BE COMBINED WITH OTHER INTERRUPTS BEING GENERATED BY A PERIPH- ERAL DEVICE. iT IS IMPORTANT THAT THE TOTAL SERVICE TIME FOR THESE INTERRUPTS DOES NOT EXCEED THAT ALLOWABLE AND THAT THE TIME AVAILABLE TO THE PROCESSOR FOR EXECUTING THE MAIN PROGRAM IS SUFFICIENT TO ALLOW THE SYSTEM TO OPERATE AT ITS REQUIRED SPEED. dURING THE SYSTEM CONFIGURATION PROCESS, DETAILED SYSTEM PROGRAMS NEED NOT BE GENERATED. hOWEVER, IT WILL BE NECESSARY TO WRITE SMALL PORTIONS OF THE SOFTWARE TO VERIFY THE SPEED OF EXECUTION AND TO ASSURE PROPER OPERATION OF THE TOTAL SYSTEM. tHIS CHAPTER WILL DISCUSS SPECIAL TECHNIQUES FOR THE CONTROL OF THE VARIOUS COMPONENTS WHICH MAY BE INCLUDED IN A MICROCOMPUTER SYSTEM, AS WELL AS TECHNIQUES FOR CONTROLLING PERIPHERAL DEVICES WHICH ARE ATTACHED TO THE SYSTEM. a DISCUS- SION OF PROGRAMMING TECHNIQUES WHICH CAN BE USED TO OPTIMIZE THE TOTAL SYSTEM PERFORMANCE IS CONTAINED IN THE pROGRAMMING mANUAL. 2.2.2 tHE sPECIAL pURPOSE pERIPHERAL iNTERFACE dEVICE tHE SPECIAL PURPOSE, DEDICATED i/o DEVICE MUST ALSO BE CONSIDERED IN ANY MICROCOMPUTER DESIGN. tHESE DEVICES ARE DESIGNED TO COMPLETELY HANDLE A SINGLE WELL-DEFINED PROBLEM; FOR EXAMPLE, DRIVING A PARTICULAR PRINTER, HANDLING A PARTICULAR TYPE OF COMMUNICATIONS LINE OR DRIVING A SCANNED DIS- PLAY. tHESE SPECIAL PURPOSE DEVICES ARE DESIGNED TO TOTALLY HANDLE THEIR PARTICULAR TASK WITH VERY LITTLE HELP FROM THE PROCESSOR. -86- ============================================================================ tHE PRIMARY ADVANTAGE OF THIS TYPE OF INTERFACE DEVICE IS THAT IT REQUIRES AN ABSOLUTE MINIMUM AMOUNT OF ATTENTION FROM THE PROCESSOR. tHE MAJOR DISADVANTAGE OF SPECIAL PURPOSE i/o IS INCREASED COMPONENT COST. tHE TOTAL PRODUCTION VOLUME FOR THESE DEVICES IS LESS THAN THAT OF THE MORE UNIVERSAL i/o CHIPS AND ALSO THE TOTAL CHIP SIZE IS USUALLY GREATER. tHE USE OF SPECIAL PURPOSE PERIPHERAL CONTROL DEVICES WILL NOT BE DISCUSSED IN THIS MANUAL. iNSTEAD, A DETAILED STUDY WILL BE MADE OF THE MORE GENERAL PROBLEM OF CONFIGURING THE 8-BIT BI-DIRECTIONAL PERIPHERAL PORT. iN ADDITION, THIS CHAPTER WILL COVER SOME SPECIAL TECHNIQUES WHICH CAN GREATLY ENHANCE THE POWER OF THIS TYPE OF INTERFACE DEVICE. 2.2.3 cONFIGURING THE gENERAL pURPOSE i/o pORT tHE 8-BIT PERIPHERAL CONTROL PORT INCLUDED ON THE mcs6520 AND THE mcs6530 ALLOWS EACH LINE TO BE PROGRAMMED TO ACT AS AN INPUT OR AN OUTPUT. tHIS IS ACCOMPLISHED WHEN THE PROCESSOR WRITES A PATTERN OF 1'S AND 0'S INTO THE DATA DIRECTION REGISTER. wRITING A 1 CAUSES THE PIN TO BECOME AN OUTPUT, AND WRITING A 0 CAUSES IT TO ACT AS AN INPUT. aLTHOUGH THIS OPERA- TION IS NORMALLY PERFORMED ONLY DURING SYSTEM INITIALIZATION, THE ABILITY TO DO SO UNDER PROGRAM CONTROL ALLOWS SOME VERY IMPORTANT PERIPHERAL CON- TROL TECHNIQUES. aN EXAMPLE OF THIS IS DESCRIBED BELOW. tHE PROCESS OF CONFIGURING THE GENERAL PURPOSE i/o PORT INVOLVES FIRST EXAMINING THE PERIPHERAL DEVICES TO ANALYZE THE VARIOUS CONTROL IN- PUTS, SWITCHES, SENSORS, DATA SIGNALS, ETC. WHICH MUST BE HANDLED BY THE MICROPROCESSOR TO PROPERLY CONTROL THE DEVICE. eACH FUNCTION MUST THEN BE ASSIGNED TO A LINE ON THE i/O PORT. tHE ULTIMATE GOAL OF THIS PROCESS IS THE CREATION OF A LIST OF i/o PINS, THE FUNCTION OF EACH PIN, AND AN INDI- CATION OF WHETHER EACH PIN IS TO BE AN INPUT OR AN OUTPUT. sINCE EACH LINE IS CAPABLE OF OPERATING AS AN INPUT OR AN OUTPUT, AND SINCE THERE IS VERY LITTLE TO DIFFERENTIATE ONE LINE FROM ANY OTHER, THE ACTUAL ASSIGNMENT CAN BE MADE FAIRLY LATE IN THE SYSTEM DEVELOPMENT CYCLE AFTER CONSIDERATION OF SOFTWARE TECHNIQUES AND PRINTED CIRCUIT BOARD LAYOUT. iN FACT, SOFTWARE CONSIDERATIONS MAY BE THE ONLY THING WHICH DIC- TATES THAT A SIGNAL BE CONNECTED TO ONE PIN OR ANOTHER. dEVELOPING A THOROUGH UNDERSTANDING OF THE SOFTWARE IN THE mcs6500 SYSTEMS WILL REQUIRE A DETAIL STUDY OF THE pROGRAMMING mANUAL. hOWEVER, SEVERAL OPERATIONS WHICH CAN BE PERFORMED BY THE PROCESSOR AND WHICH AFFECT THE ASSIGNMENT OF INPUTS AND OUTPUTS WILL BE DISCUSSED BRIEFLY HERE. -87- ============================================================================ 2.2.3.1 aSSIGNMENT OF oUTPUTS a MAJOR FACTOR IN THE ASSIGNMENT OF OUTPUT PINS CAN BE THE ABILITY OF THE mcs650x PROCESSOR TO INCREMENT AND DECREMENT MEMORY. sINCE THE i/o PORT IS TREATED AS A LOCATION IN MEMORY, THIS INCREMENTING AND DECREMENTING CAN BE USED TO RAPIDLY SET AND CLEAR THE LOW ORDER BIT IN THIS MEMORY LOCA- TION. tHIS IS ILLUSTRATED IN fIGURE 2.1. nOTE THAT THIS DOES NOT AFFECT ANYTHING BUT THE LOW ORDER BIT IF IT IS USED PROPERLY AS SHOWN. tHIS OPERATION CAN BE PERFORMED MORE RAPIDLY THAN SEVERAL OTHER SOFTWARE TECHNIQUES WHICH CAN BE USED TO AFFECT A SINGLE BIT. tHEREFORE, CONTROL OF A SINGLE INDICATOR, DATA LINE, ETC. CAN BE GREATLY ENHANCED BY PUTTING IT ON THE LOW ORDER BIT OF AN i/o PORT. tHIS IS THE REASON THE LOW ORDER BIT OF BOTH THE nc56530 PERIPHERAL PORTS (pa0 AND pbo) PROVIDE THE ABILITY TO DRIVE TRANSISTORS DIRECTLY. iN MANY APPLI- CATIONS, A SIMPLE TRANSISTOR ATTACHED TO ONE OF THOSE PINS WOULD PROVIDE VERY CONVENIENT CONTROL OF A MOTOR, LAMP, ETC. tHE ABILITY OF THE MICROPROCESSOR TO SHIFT DATA IN MEMORY CAN BE ANOTHER VERY IMPORTANT FACTOR IN THE ASSIGNMENT OF OUTPUTS. oPERATIONS WHICH REQUIRE SEQUENTIAL STROBE SIGNALS CAN BE CONTROLLED CONVENIENTLY BY SHIFTING A SINGLE HIGH (OR LOW) SIGNAL FROM PIN TO PIN UNDER SOFTWARE CON- TROL. tHE SPECIFIC CHOICE OF PINS CAN GREATLY ENHANCE THE EASE WITH WHICH THIS SIGNAL IS CONTROLLED. 2.2.3.2 aSSIGNMENT OF iNPUTS iN GENERAL, THE PROCESSOR DEALS WITH THE INPUT DATA FROM SWITCHES, KEYBOARDS, ETC. BY READING THE DATA ON THE i/o PORT INTO THE INTERNAL REGIS- TERS OF THE PROCESSOR (USUALLY THE ACCUMULATOR) AND USING THE RESULTING CON- DITION OF FLAGS IN THE pROCESSOR sTATUS rEGISTER TO CONTROL THE PROGRAM WHICH IS EXECUTED. dURING THIS TRANSFER PROCESS, THE n FLAG IN THE pROCES- SOR sTATUS rEGISTER IS SET EQUAL TO THE HIGH ORDER BIT (BIT 7) OF THE WORD READ FROM THE i/o PORT. tHIS n FLAG CAN THEN BE USED TO CAUSE THE PROCESSOR TO EXECUTE DIFFERENT SECTIONS OF THE PROGRAM (sEE THE pROGRAMMING mANUAL, cHAPTER 4, FOR A DETAILED DISCUSSION OF bRANCHING). lIKEWISE, BY PERFORM- ING CERTAIN INSTRUCTIONS, THE v FLAG IN THE pROCESSOR sTATUS rEGISTER CAN BE sET EQUAL TO BIT 6 ON THE i/o PORT. tHIS FLAG CAN THEN BE USED TO AFFECT THE PROGRAM WHICH IS EXECUTED. tHIS OPERATION OF SETTING THE INTERNAL FLAGS FROM BITS 6 AND 7 OF THE MEMORY WORD MEANS THAT MAKING THESE TWO LINES INPUTS ON AN i/o PORT -88- ============================================================================ mcs6s2o data register 1 loaded into ----+---+---+---+---+---+---+---- voltage on output mcs6520 {$7c} 0 {$7c} 1 {$7c} 0 {$7c} 0 {$7c} 1 {$7c} 0 {$7c} 0 {$7c} 1 {$7c} pins of mcs6520 microprocessor ----+---+---+---+---+-+-+-+-+-+-- {$7c} {$7c} ---------> high (>2.4v) {$7c} -------------> low (<0.4v) -----------------> low 2 after ----+---+---+---+---+---+---+---- decrement {$7c} 0 {$7c} 1 {$7c} 0 {$7c} 0 {$7c} 1 {$7c} 0 {$7c} 0 {$7c} 0 {$7c} operation ----+---+---+---+---+-+-+-+-+-+-- {$7c} {$7c} ---------> low {$7c} -------------> low -----------------> low 3 after ----+---+---+---+---+---+---+---- subsequent {$7c} 0 {$7c} 1 {$7c} 0 {$7c} 0 {$7c} 1 {$7c} 0 {$7c} 0 {$7c} 1 {$7c} increment ----+---+---+---+---+-+-+-+-+-+-- operation {$7c} {$7c} ---------> high {$7c} -------------> low -----------------> low cONTROL OF lOW oRDER bIT OF mcs6520 oUTPUT rEGISTER figure 2.1 -89- ============================================================================ WILL ALLOW VERY CONVENIENT TESTING OF THE CONDITION OF THE SWITCHES, SENSORS, ETC. ATTACHED TO THESE INPUTS. iF MORE THAN TWO INPUT SIGNALS ARE TO BE ATTACHED TO A PORT, THE ADDITIONAL INPUTS SHOULD BE PLACED ON BIT 5, THEN BIT 4 AND SO ON. tHE PROCESSOR CAN THEN PERFORM OPERATIONS WHICH SHIFT THE LOWER ORDER BITS INTO BIT 7 ONE AT A TIME AND SETS THE n FLAG EQUAL TO THIS BIT. aFTER EACH SHIFT THE n FLAG CAN BE USED TO DETERMINE THE ACTUAL PROGRAM WHICH IS TO BE EXECUTED. (sEE THE pROGRAMMING mANUAL FOR A DISCUSSION OF THE sHIFT INSTRUCTIONS.) fROM THE ABOVE EXAMPLE, ONE SHOULD CONCLUDE THAT THE ASSIGNMENTS WHICH THE DESIGNER MAKES WILL BE VERY MUCH A FUNCTION OF THE SOFTWARE TECH- NIQUES WHICH WILL BE EMPLOYED IN CONTROLLING EACH LINE. iT IS VERY IMPORT- ANT THAT THE DESIGNER BE FAMILIAR WITH THESE TECHNIQUES AND THAT HE DOCU- MENT THE TECHNIQUES WHICH HE HAS IN MIND WHEN MAKING THE ASSIGNMENTS. tHIS IS PARTICULARLY IMPORTANT WHEN THE SYSTEM PROGRAM IS TO BE WRITTEN BY SOME- ONE ELSE. aLSO, IT IS IMPORTANT THAT THOSE DOING THE SYSTEM DEVELOPMENT WORK CONSTANTLY REVIEW THE i/o STRUCTURE TO OPTIMIZE THE SOFTWARE IN- VOLVED AS THE SYSTEM PROGRAM IS WRITTEN. 2.2.4 pOWER-oN cONSIDERATIONS cHAPTER 1, sECTION 1.3.3 DISCUSSES THE OPERATION OF THE SYSTEM reset FUNCTION. rEFERENCE IS MADE TO THE FACT THAT THIS CAN BE USED TO ASSURE THAT ALL i/o LINES COME UP IN A KNOWN STATE WHEN POWER IS APPLIED TO THE CHIP. aLTHOUGH THIS IS A VERY IMPORTANT FUNCTION, THE DESIGNER MUST ASSURE HIMSELF THAT THIS reset STATE DOES NOT ADVERSELY AFFECT THE PERIPHERAL DEVICES. tHIS SECTION DESCRIBES SOME OF THE PROBLEMS WHICH CAN BE ENCOUN- TERED WHEN THE SYSTEM IS RESET AND DISCUSSES SEVERAL TECHNIQUES WHICH CAN BE USED TO ASSURE SMOOTH POWER-UP OPERATION. tHE i/o LINES OF THE mcs6530 AND mcs6520 ALL ENTER THE INPUT STATE WHEN THE RESET LINE GOES TO gnd (< 0.4v). fOR THE mcs6530 i/o LINES, AND FOR THE pERIPHERAL a PORT ON THE mcs6520, THESE PINS WILL GO TO +5v dc (vDD). tHIS IS DUE TO THE OUTPUT STRUCTURE ON THESE PINS. wHEN THESE LINES ARE IN THE INPUT STATE, THE OUTPUT SWITCH BECOMES AN OPEN CIRCUIT BUT THE PULL-UP DEVICE CONTINUES TO SUPPLY CURRENT TO THE PIN. fIGURE 2.2 SHOWS A PERIPHERAL PORT WHICH IS CONFIGURED TO DRIVE TWO SOLENOIDS. tHESE SOLENOIDS CAN BE CONTROLLED PROPERLY AFTER THE SYSTEM IS INITIALIZED; HOWEVER, WHEN THE MANUAL RESET SWITCH IS ACTIVATED, BOTH i/o -90- ============================================================================ +v +v -------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +---> {$7c} {$7c} {$7c} {$7c} {$7c} solenoid coils {$7c} {$7c} +---> {$7c} {$7c} {$7c} {$7c} 8 -+-+-+--- ---+-+-+- {$7c} +---> output {$7c} \ \ \ {$7c} {$7c} / / / {$7c} {$7c} peripheral {$7c} lines ---+-+-+- -+-+-+--- from ======>{$7c} interface +---> {$7c} {$7c} microprossor {$7c} device {$7c} {$7c} {$7c} {$7c} mcs6520 +---> {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +---> / {$7c} {$7c} {$7c} ------ {$7c}/ {$7c} {$7c} +--->-----+ +----+ {$7c} {$7c} {$7c} ------ {$7c}\ {$7c} {$7c} +--->--- - {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -+- {$7c} {$7c} - {$7c} {$7c} / {$7c} ------ {$7c}/ ---+ +------------+ ------ {$7c}\ - {$7c} {$7c} {$7c} -+- - mcs6520 cONTROL OF tRANSISTOR dRIVEN sOLENOIDS figure 2.2 -91- ============================================================================ LINES ENTER THE INPUT STATE, THE TRANSISTORS SATURATE (CLOSE) AND THE SOLE- NOIDS ARE ACTIVATED. tHIS CAN BE CATASTROPHIC IN MOST MECHANICAL SUBSYS- TEMS, SO IT IS IMPORTANT THAT THIS POTENTIAL CONDITION BE UNDERSTOOD AND PREVENTED. fIGURE 2.3 SHOWS TWO SATISFACTORY SOLUTIONS TO THIS PROBLEM. tHE FIRST, fIGURE 2.3A, REQUIRES THAT A "0" BE WRITTEN INTO THE OUTPUT LINE BY THE PROCESSOR TO ACTUATE THE SOLENOIDS. tHIS ASSURES THAT THE SOLENOIDS WILL NOT BE POWERED SIMULTANEOUSLY WHEN THE MANUAL RESET SWITCH IS PRESSED. hOWEVER, IT DOES INTRODUCE ANOTHER POTENTIAL PROBLEM. WHEN THE RESET LINE ON THE PERIPHERAL INTERFACE DEVICE GOES LOW (< 0.4v), THE CONTENTS OF BOTH THE pERIPHERAL dATA REGISTER AND THE dATA dIRECTION REGISTER ARE CLEARED TO ZEROS. iF THE dATA dIRECTION REGISTER IS SET TO 1'S, BOTH SOLENOIDS WILL IMMEDIATELY ACTUATE DUE TO THE 0 STORED IN THE pERIPHERAL dATA REGISTER. tHIS CAN BE AVOIDED COMPLETELY IF THE SYSTEM SOFTWARE FIRST SETS THE BITS IN THE pERIPHERAL dATA REGISTER TO A 1 AND THEN SETS THE dATA dIRECTION REGISTER TO A 1. tHE i/o PIN WILL GO HIGH WHEN THE RESET SWITCH IS ACTUATED AND WILL SIMPLY STAY HIGH THROUGH THE INITIALIZATION ROUTINE. fIGURE 2.3B ILLUSTRATES A SOLUTION WHICH MAY BE MORE APPLICABLE TO A LARGE SYSTEM OR A COMPLEX PERIPHERAL. iN THIS APPROACH, A SEPARATE OUTPUT LINE IS USED TO APPLY POWER TO THE PERIPHERAL DEVICE. tHE POWER TO THE ENTIRE PERIPHERAL OR TO JUST THE CRITICAL ELEMENTS IS KEPT OFF UNTIL THE ENTIRE SYSTEM IS INITIALIZED AND IS READY TO RUN THE SYSTEM PROGRAM. oN THE mcs6520 pERIPHERAL b PORT, THE i/o LINES ARE OPEN CIRCUIT (HIGH IMPEDANCE) IN THE INPUT STATE. aS A RESULT, THE CONFIGURATION IN fIGURE 2.2 WILL NOT CAUSE THE SAME PROBLEM ON THE mcs6520 pERIPHERAL b PORT AS WOULD BE EXPECTED ON THE mcs6530. iN THE INPUT STATE, THE i/o PIN IS INCAPABLE OF SCURCING ANY MORE THAN A FEW MICROAMPS. hOWEVER, IF ONE WERE TO USE A SOLENOID DRIVER AS SHOWN IN fIGURE 2.4, THE ttl INPUT STRUCTURE ON THE DRIVERS WOULD INTERPRET THE HIGH-IMPEDANCE STATE AS A LOGIC 1 AND WOULD ACTUATE THE SOLENOIDS. bOTH THE SOLUTIONS IN fIGURE 2.3 WOULD BE SATISFACTORY IN THIS CASE. hOWEVER, THE TRANSISTORS ARE CONNECTED TO THE ttl BUFFER. iN ADDITION, THE EXTRA OUTPUT SHOWN IN fIGURE 2.3B, CONTROLLING POWER TO THE PERIPHERAL DEVICE, COULD ACTUALLY BE USED TO ENABLE THE SOLENOID DRIVERS IF AN ENABLE INPUT IS AVAILABLE TO THESE DEVICES. tHIS CONFIGURATION IS ILLUSTRATED IN fIGURE 2.5. -92- ============================================================================ -------------- {$7c} {$7c} {$7c} +---> 8 output +v {$7c} {$7c} lines {$7c} {$7c} +---> {$7c} {$7c} {$7c} {$7c} {$7c} +---> / mcs6520 cONTROL OF {$7c} peripheral {$7c} ------ {$7c}- pnp tRANSISTOR DRIVING {$7c} interface +---> ---+ +---+ sOLENOID cOIL {$7c} device {$7c} {$7c} ------ {$7c}\ {$7c} mcs6520 +---> {$7c} \ figure 2.3a {$7c} {$7c} {$7c} {$7c} {$7c} +---> {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +--->--- -+-+-+--- {$7c} {$7c} {$7c} \ \ \ {$7c} {$7c} +--->--- ---+-+-+- +v {$7c} {$7c} {$7c} {$7c} {$7c} -------------- {$7c} -+- {$7c} {$7c} solenoid - {$7c} {$7c} coil {$7c} {$7c} / {$7c} ------ {$7c}- ---+ +---------------+ ------ {$7c}\ \ {$7c} {$7c} -+-+-+--- {$7c} \ \ \ {$7c} ---+-+-+- {$7c} {$7c} -+- - +v {$7c} {$7c} / 8 output ------ {$7c}- power control lines ---+ +---------+ transistor -------------- {$7c} ------ {$7c}\ {$7c} {$7c} {$7c} \ {$7c} +---> {$7c} {$7c} {$7c} {$7c} {$7c} +----------- {$7c} +---> {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ---+-+-+- ---+-+-+- {$7c} +---> {$7c} {$7c} / / / {$7c} {$7c} / / / {$7c} mcs6520 cONTROLLING {$7c} peripheral {$7c} {$7c} -+-+-+--- -+-+-+--- bOTH pOWER AND dRIVERS {$7c} interface +---> {$7c} {$7c} {$7c} OF sOLENOID cELL {$7c} device {$7c} {$7c} {$7c} {$7c} {$7c} mcs6520 +---> {$7c} {$7c} {$7c} figure 2.3b {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +--->--- / {$7c} {$7c} {$7c} ------ {$7c}/ {$7c} {$7c} +--->-----+ +---+ {$7c} {$7c} {$7c} ------ {$7c}\ {$7c} {$7c} +--->--- - {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------------- {$7c} {$7c} {$7c} {$7c} -+- {$7c} {$7c} - {$7c} {$7c} / {$7c} ------ {$7c}/ ---+ +--------------+ ------ {$7c}\ - {$7c} {$7c} -+- - -------------- {$7c} {$7c} {$7c} +---> {$7c} {$7c} +v {$7c} +---> {$7c} {$7c} {$7c} {$7c} {$7c} +---> ---+-+-+- mcs6520 cONTROLLING {$7c} peripheral {$7c} {$7c} / / / {$7c} bOTH pOWER AND dRIVERS {$7c} interface +---> -+-+-+--- OF sOLENOID cELL {$7c} device {$7c} {$7c} solenoid {$7c} mcs6520 +---> {$7c} coils figure 2.3b {$7c} {$7c} {$7c} {$7c} +---> {$7c}\ / +v {$7c} {$7c} {$7c} \ {$7c}/ {$7c} {$7c} +--->------+ >-----+ {$7c} {$7c} {$7c} {$7c} / {$7c}\ ---+-+-+- {$7c} +--->--- {$7c}/ - {$7c} / / / {$7c} {$7c} {$7c} {$7c} {$7c} -+-+-+--- -------------- {$7c} ttl {$7c} {$7c} {$7c} buffers -+- {$7c} {$7c} - {$7c} {$7c} {$7c}\ / {$7c} {$7c} \ {$7c}/ ----+ >-------------+ {$7c} / {$7c}\ {$7c}/ - {$7c} {$7c} -+- - -93- ============================================================================ -------------- +v +v {$7c} {$7c} {$7c} {$7c} {$7c} +---> {$7c} solenoid coils {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +---> -+-+-+--- ---+-+-+- {$7c} {$7c} 8 {$7c} \ \ \ {$7c} {$7c} / / / {$7c} {$7c} +---> output ---+-+-+- -+-+-+--- {$7c} peripheral {$7c} lines {$7c} {$7c} {$7c} interface +---> {$7c} {$7c} {$7c} device {$7c} {$7c} {$7c} {$7c} mcs6520 +---> {$7c} {$7c} {$7c} {$7c} ------ / {$7c} {$7c} +--->---------------------------+ \ {$7c}/ {$7c} {$7c} {$7c} {$7c} and )----+ {$7c} {$7c} +--->------------ ---+ / {$7c}\ {$7c} {$7c} {$7c} {$7c} {$7c}\ {$7c} ------ - {$7c} {$7c} +--->------ {$7c} {$7c} \ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -----+ >o---+ {$7c} {$7c} -------------- {$7c} {$7c} / {$7c} -+- {$7c} {$7c} {$7c}/ {$7c} - {$7c} {$7c} {$7c} ------ / {$7c} ---+ \ {$7c}/ {$7c} {$7c} and )------------+ ----------------------+ / {$7c}\ ------ - {$7c} ttl {$7c} gates -+- - mcs6520 cONTROLLING sOLENOIDS WITH eNABLE sIGNAL AND ttl iNTERFACE figure 2.2 2.2.5 hANDSHAKING tHE mcs6520 PROVIDES BOTH INTERRUPT CONTROL AND DATA TRANSFER CON- TROL CAPABILITY. tHE TECHNIQUE FOR CONTROLLING THE TRANSFER OF DATA BE- TWEEN THE PROCESSOR AND A PERIPHERAL DEVICE IS REFERRED TO AS HANDSHAKING. iN THIS PROCEDURE, EACH DEVICE (THE PROCESSOR OR PERIPHERAL) IS CAPABLE OF SIGNALLING THE OTHER THAT ITS OPERATION IS COMPLETE. tHE SEQUENCE DIFFERS SOMEWHAT FOR TRANSFERS INTO OR OUT OF THE PROCESSOR, SO THEY WILL BE DIS- CUSSED SEPARATELY BELOW. 2.2.5.1 hANDSHAKING ON dATA tRANSFERS FROM THE pROCESSOR tHE TRANSFER OF DATA OUT OF THE PROCESSOR INTO A PERIPHERAL DEVICE IS PERFORMED BY FIRST WRITING THE DATA INTO THE DATA REGISTER WITHIN THE mcs6520. tHIS DATA THEN APPEARS ON THE PERIPHERAL OUTPUT LINES WHERE IT CAN BE READ BY THE PERIPHERAL DEVICE FOR STORAGE, DISPLAY, ETC. -94- ============================================================================ cONTROL OF THIS DATA TRANSFER BY HANDSHAKING REQUIRES FIRST THAT THE PROCESSOR SIGNAL THE PERIPHERAL DEVICE THAT DATA IS AVAILABLE ON THE i/o PORT. tHE PERIPHERAL DEVICE THEN READS THIS DATA AND SIGNALS TO THE PROCESSOR THAT THE DATA HAS BEEN TAKEN AND THAT NEW DATA CAN BE MADE AVAIL- ABLE. tHE PROCESSOR THEN MAKES NEW DATA AVAILABLE AND THE CYCLE IS RE- PEATED. aS DESCRIBED IN cHAPTER 1, THE pERIPHERAL b iNTERFACE pORT ON THE mcs6520 IS DESIGNED TO PERFORM HANDSHAKING ON write OPERATIONS. tHE cb2 PERIPHERAL CONTROL LINE CAN BE PROGRAMMED TO ACT AS AN OUTPUT WHICH GOES LOW EACH TIME THE PROCESSOR WRITES DATA ONTO THE pERIPHERAL b i/o PORT. tHIS IS THE SIGNAL WHICH IS USED TO TELL THE PERIPHERAL DEVICE THAT DATA IS AVAILABLE ON THESE OUTPUT LINES. tHE cb2 OUTPUT LINE WILL STAY LOW UNTIL THE PERIPHERAL DEVICE SIG- NALS THE PROCESSOR THAT THE DATA IS TAKEN. tHIS IS ACCOMPLISHED BY INTER- RUPTING THE PROCESSOR THROUGH THE cb1 INTERRUPT INPUT. tHE SEQUENCE WHICH TAKES PLACE DURING THE "write" HANDSHAKING OPERATION DESCRIBED ABOVE IS SHOWN IN fIGURE 2.6. 2.2.5.2 hANDSHAKING ON dATA tRANSFERS INTO THE pROCESSOR tHE pERIPHERAL a i/o PORT ON THE mcs6520 IS DESIGNED TO HANDSHAKE ON DATA TRANSFERS FROM THE PERIPHERAL DEVICE INTO THE PROCESSOR. iN THIS SEQUENCE, THE PERIPHERAL DEVICE MUST SIGNAL THE PROCESSOR THAT DATA IS AVAILABLE AND THE PROCESSOR MUST SIGNAL BACK THAT DATA WAS TAKEN. tHIS IS BASICALLY THE SAME SEQUENCE AS THAT PERFORMED IN THE PREVIOUS OPERATION. tHE ca1 INTERRUPT INPUT IS USED TO INTERRUPT THE PROCESSOR TO INDICATE THAT THERE IS DATA AVAILABLE ON THE pERIPHERAL a i/o PORT. tHE PERIPHERAL DE- VICE MUST THEN HOLD THAT DATA THERE UNTIL THE PROCESSOR READS IT INTO ITS INTERNAL REGISTERS. WHEN THE PROCESSOR READS THE pERIPHERAL a i/O PORT, THE ca2 PERIPHERAL CONTROL LINE GOES LOW TO SIGNAL TO THE PERIPHERAL DEVICE THAT THE DATA HAS BEEN TAKEN AND NEW DATA CAN BE MADE AVAILABLE. tHIS EN- TIRE SEQUENCE IS SHOWN IN fIGURE 2.7. tHE HANDSHAKING OPERATIONS DESCRIBED ABOVE CAN BE AN EXTREMELY POWERFUL TECHNIQUE FOR INTERFACING DATA STORAGE DEVICES OR, IN GENERAL, ANY DEVICE WHICH MUST TRANSFER BLOCKS OF DATA AND WHICH HAS A VARIABLE RE- SPONSE TIME. iF THE PROCESSOR CANNOT PREDICT THE SPEED WITH WHICH THE PERIPHERAL TAKES DATA, FOR INSTANCE, IT MUST RELY ON THE PERIPHERAL TO SIGNAL THAT IT HAS DONE SO. -95- ============================================================================ iNITIATING THE DATA TRANSFER SEQUENCE IS USUALLY ACCOMPLISHED THROUGH A SET OF i/o LINES SEPARATE FROM THE PORT WHICH IS TRANSFERRING THE DATA. hOWEVER, ONCE THE SEQUENCE IS UNDER WAY, THE PROCESSOR MUST DEAL WITH THE PERIPHERAL DEVICE ONLY WHEN AN INTERRUPT HAS OCCURRED. tHIS ALLOWS THE PROCESSOR TO EXECUTE THE PRIMARY SYSTEM PROGRAM WHILE STILL SERVICING THESE PERIPHERAL DEVICES. -96- ============================================================================ -- ----- ----- ----- ----- ----- ----- ----- enable {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ----- ----- ----- --//- ----- ----- ----- -- 1 -- ------- ----------------//------------------------------ address x x -- ------- ----------------//------------------------------ --- ------------------//------------------------------ r/w 1{$7c} {$7c} -------- __ 2/ \ data bus -----< >----------------//------------------------------ \__/ --------- -----------------//------------------------------ peripheral 3 x data --------- -----------------//------------------------------ ---------------- -------- cb2 {$7c} 6{$7c} ------------//----------------------- ---------------------------//------------------- ---------- cb1 5 x ---------------------------//------------------- ---------- 1. pROCESSOR PUTS OUT ADDRESS OF PERIPHERAL DEVICE AND CHANGES r/w SIGNAL TO WRITE ENABLE (LOW). 2. dURING PHASE TWO PROCESSOR PUTS OUT DATA ON dATA bUS. 3. dATA FROM THE PROCESSOR IS ACCEPTED BY THE mcs6520 ON THE FALLING EDGE OF THE ENABLE CLOCK. 4. pERIPHERAL iNTERFACE DEVICE NOW BEGINS THE HANDSHAKE BY SIGNALING THE PERIPHERAL DEVICE THAT DATA IS AVAILABLE TO READ ON THE OUTPUT PORT. 5. wHEN THE EXTERNAL PERIPHERAL DEVICE READS THE DATA ON THE OUTPUT PORT IT WILL RESPOND BY A CHANGE IN cb1. 6. tHIS CHANGE IN cb1 IS FOLLOWED BY A POSITIVE TRANSITION OF cb2 SIGNALLING THE PROCESSOR THAT DATA WAS ACCEPTED. wRITE HANDSHAKE sEQUENCE figure 2.6 -97- ============================================================================ ------ ------ ------ ------ ------ ----- enable {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} --- ------ ------ ------ ------ ------ ----- --------------------------------------------------- peripheral 1 x data ----- --------------------------------------------------- --------- ----------------------------------------------- ca1 2 x --------- ----------------------------------------------- ---------------------------- ---------------------------- address 5 x ---------------------------- ---------------------------- ------------------------------ r/w {$7c} ---------------------------- __ 6 / \ data bus ---------------------------------< >------------------ \__/ --------------------------- ca2 3 / \ 7 --------- ------------------- 1. nEW dATA IS PUT OUT BY PERIPHERAL DEVICE. 2. tHE PERIPHERAL INTERFACE DEVICE IS SIGNALED BY ca1 THAT THE NEW DATA IS READY TO BE READ AT THE INPUT PORT. 3. ca2 IS PUT IN THE HIGH STATE. 4. tHE PROCESSOR IS SIGNALLED THAT NEW DATA IS READY TO BE READ BY A LOW LEVEL ON THE irq LINE. 5. tHE PROCESSOR BEGINS SERVICING THE iNTERRUPT REQUEST AND DURING THE ROUTINE THE PROCESSOR WILL PUT OUT THE READ SIGNAL AND THE aDDRESS OF THE pERIPHERAL iNTERFACE DEVICE. 6. tHE pERIPHERAL INTERFACE WILL TRANSFER THE NEW DATA FROM THE PERIPHERAL DEVICE TO THE MICROPROCESSOR THROUGH THE DATA BUS. 7. wHEN dATA HAS BEEN TRANSFERRED THE PERIPHERAL DEVICE WILL BE SIGNALED BY ca2 GOING LOW. rEAD hANDSHAKE sEQUENCE figure 2.7 -98- ============================================================================ 2.3 configumng the interface between the microprocessor and the support chips. tHE SYSTEM BLOCK DIAGRAM (fIGURE 2.8) SHOWS THE BASIC DATA PATHS WHICH AL- LOW THE mcs6500 SYSTEM TO OPERATE. dATA bUS, aDDRESS bUS, r/w SIGNAL, ETC. ARE SHOWN AS SIMPLE CONNECTIONS BETWEEN THE VARIOUS CHIPS IN THE SYSTEM. aLTHOUGH THESE DATA PATHS WILL EXIST IN ANY SYSTEM, NO MATTER HOW COMPLEX, EACH ELEMENT OF THE MICROPROCESSOR INTERFACE MUST BE EXAMINED TO ASSURE THAT EACH CHIP IS PROPERLY DRIVEN WITH SIGNALS WHICH MEET ALL SPECIFICATIONS FOR THE DEVICE, TO ASSURE THAT THE INTER-CHIP TIMING IS PROPER AND TO ASSURE THAT THE OVERALL SYS- TEM IS OPERATING AS REQUIRED. 2.3.1 aSSIGNMENT OF aDDRESSES IN THE nc56500 sYSTEM tHE ONLY METHOD WHICH THE MICROPROCESSOR HAS FOR SELECTING BETWEEN THE VARIOUS ramS, romS, ETC. IN A SYSTEM IS THROUGH THE ADDRESS OUTPUT LINES. fOR THIS REASON, THE DESIGNER MUST USE THESE LINES VERY CAREFULLY TO ACHIEVE MINIMUM SYSTEM COST AND TO ASSURE SATISFACTORY SYSTEM PERFOR- MANCE. bEFORE LOOKING AT HOW THE ADDRESS LINES CAN BE CONFIGURED TO MINIMIZE TOTAL SYSTEM COST OR PROGRAM EXECUTION TIME, THE DESIGNER SHOULD UNDERSTAND HOW THE BINARY VALUE ASSOCIATED WITH EACH ADDRESS LINE IS RELATED TO THE TOTAL ADDRESS SPACE AVAILABLE TO THE MICROPROCESSOR AND HOW THE and FUNC- TION OF VARIOUS ADDRESS LINES CAN BE USED TO SELECT LARGE BLOCKS OF AD- DRESSES. fIGURE 2.9 ILLUSTRATES THE STATE OF THE THREE HIGH-ORDER ADDRESS LINES FOR THE ENTIRE ADDRESS SPACE AVAILABLE TO THE mcs650x. nOTE THAT THE HIGHEST ORDER ADDRESS LINE IS A LOGIC 1 FOR EXACTLY HALF OF THE AVAILABLE ADDRESS. tHE and FUNCTION OF THE TWO HIGHEST ORDER ADDRESS LINES IS A LOGIC 1 FOR ONE-FOURTH OF THE AVAILABLE ADDRESSES, AND SO FORTH. fIGURE 2.9 ALSO ILLUSTRATES SEVERAL and FUNCTIONS DERIVED FROM THE THREE HIGHEST ORDER ADDRESS LINES. eACH IS TRUE FOR A DIFFERENT BLOCK OF THE AVAILABLE AD- DRESSES. gENERATION OF THE and FUNCTION OF VARIOUS HIGH ORDER ADDRESS LINES IS EXTREMELY IMPORTANT BECAUSE OF THE CHIP SELECT TECHNIQUES EMPLOYED ON THE PROCESSOR SUPPORT CHIPS. aS DESCRIBED IN cHAPTER 1, sECTION 1.5.2.4, THE mcs6520 HAS THREE CHIP-SELECT LINES. tHE ENTIRE CHIP IS SELECTED FOR READING OR WRITING DATA WHEN cs1 AND cs2 ARE HIGH (> 2.4V) AND cs3 IS LOW -99- ============================================================================ [ bLOCKDIAGRAM OF cpu, ram, rom, i/o AND dma ] oRGANIZATION OF mICROCOMPUTER sYSTEM figure 2.8 -100- ============================================================================ eXAMPLE OF 'and" fUNCTION uSING hIGH oRDER aDDRESS lINES figure 2.9 -101- ============================================================================ (< 0.4v). sELECTION OF THE ADDRESS LINES WHICH ENABLE THE VARIOUS CHIPS IN THE SYSTEM IS A VERY BASIC BUT VERY IMPORTANT PART OF THE SYSTEM CON- FIGURATION TASK. iT IS IMPORTANT TO NOTE HERE THAT VERY FEW MICROPROCESSOR-BASED SYS- TEMS ACTUALLY REQUIRE THAT THE PROCESSORS BE ABLE TO ACCESS A FULL 65,536 WORDS. iN FACT, MOST SYSTEMS CAN BE PROGRAMMED IN LESS THAN 2,000 WORDS FOR PROGRAM AND DATA MEMORY. tHE FULL ADDRESS SPACE IS MADE AVAILABLE PRI- MARILY BECAUSE IT ALLOWS THE CONFIGURATION OF SYSTEMS WITH AN ABSOLUTE MINIMUM OF SEPARATE DECODING CHIPS BETWEEN THE PROCESSOR AND THE SUPPORT CHIPS. iT IS POSSIBLE TO ASSIGN ANY BLOCK OF ADDRESS TO EACH TYPE OF CHIP (ram, rom, PERIPHERAL INTERFACE CHIPS, ETC.) IN THE SYSTEM. hOWEVER, EACH OF THE ASSIGNED ADDRESSES MUST BE MUTUALLY EXCLUSIVE. oNLY ONE OF THE SUP- PORT CHIPS SHOULD BE SELECTED FOR EVERY ADDRESS USED IN THE SYSTEM PROGRAM. 2.3.1.1 rom aDDRESS aSSIGNMENT tHE ASSIGNMENT OF rom ADDRESSES IS DICTATED BY THE FACT THAT THE INTERRUPT AND reset VECTORS MUST BE LOCATED IN THE 6 HIGH-ORDER WORDS IN MEMORY. tHESE ARE FIXED VECTORS AND MUST BE STORED PERMANENTLY IN THESE LOCATIONS. fOR THIS REASON, THE PROGRAM MEMORY (USUALLY rom) IS USUALLY ASSIGNED THE HIGH ORDER ADDRESSES. iN FACT, THE RECOMMENDED PROCEDURE IS TO USE a15 (a12 FOR mcs6504 AND a11 FOR mcs6503 AND mcs6505) TO SELECT PROGRAM rom. 2.3.1.2 ram aDDRESS aSSIGNMENT tHERE ARE SEVERAL FACTORS WHICH DETERMINE THE LOCATION OF THE ram IN AN mcs650x-BASED SYSTEM. dATA STORED IN MEMORY UNDER CONTROL OF THE IN- TERNAL PROCESSOR sTACK pOINTER WILL ALWAYS GO INTO pAGE oNE (adh = 01). aLSO, THE ENTIRE SET OF pAGE zERO ADDRESSING MODES RELIES ON THERE BEING DATA STORAGE ram IN pAGE zERO. fOR THIS REASON, THE ram IN A mcs650x-BASED SYSTEM SHOULD BE PLACED IN THE LOW ORDER ADDRESSES IN MEMORY. wITH THE ram IN LOW ORDER MEMORY AND THE rom IN HIGH ORDER MEMORY, THE PERIPHERAL INTERFACE DEVICES MUST GO SOMEWHERE IN BETWEEN. tHIS IS ___ ACCOMPLISHED IN fIGURE 2.10 BY USING a15 X a14 TO SELECT romS, a15 TO SELECT ram, ___ AND a15 . a14 TO SELECT ALL PERIPHERAL INTERFACE DEVICES. tHIS ALLOWS DIF- FERENTIATION BETWEEN THE TYPES OF SUPPORT CHIPS. tHE ADDRESSING STRUCTURE CAN BE COMPLETED BY ALLOWING FOR SELECTION OF EACH CHIP IN THE GROUPS. -102- ============================================================================ -------- --------------- ------+cs {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a15+-----------------------------------------O {$7c}rom {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a14+--------------------------------------O--+-----+cs {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} a13+------------------------------------ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a12+--------------------------------- {$7c} {$7c} {$7c} -------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a11+------------------------------ {$7c} {$7c} {$7c} {$7c} {$7c}ram {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}__ {$7c} {$7c} a10+--------------------------- {$7c} {$7c} {$7c} {$7c} O-----+cs {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a9 +------------------------ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} micro {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} O-----+cs1 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} processor {$7c} {$7c} {$7c} {$7c} {$7c} O--+--+-----+cs2 {$7c}mcs6520 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}___ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} O--+-----+cs3 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} a0 +--- {$7c} {$7c} {$7c} O--+--+--+-----+cs1 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} --------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} O-----+cs2 {$7c}mcs6520 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}___ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} O--+-----+cs3 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} O-----+cs1 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} O--+--+--+--+-----+cs2 {$7c}mcs6520 {$7c} a0 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}___ {$7c} {$7c} thru {$7c} {$7c} {$7c} {$7c} {$7c} O--+-----+cs3 {$7c} {$7c} a9 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c}<------------------>{$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} V V V V V V V V a0 a9 a15 \__________________________________________/ to additiona1 mcs6520'S and memory tYPICAL aDDRESS aSSIGNMENTS figure 2.10 -103- ============================================================================ tHE ADDRESSES WHICH SELECT THE VARIOUS REGISTERS, PERIPHERAL PORTS, ETC. WITHIN THE PERIPHERAL INTERFACE DEVICES NORMALLY USED WILL NOT BE SEQUENTIAL. fOR THIS REASON, IT IS NORMALLY RECOMMENDED THAT THE TECH- NIQUE SHOWN IN fIGURE 2.10 BE USED TO DIFFERENTIATE BETWEEN THE PERIPHERAL INTERFACE CHIPS. tHIS ALLOWS SELECTION OF 12 DEVICES WITH NO DECODING IN A mcs6501- OR mcs6502-BASED SYSTEM, UP TO NINE mcs6520 DEVICES IN A mcs6504- BASED SYSTEM, AND UP TO EIGHT DEVICES IN A mcs6503 AND mcs6505-BASED SYSTEM. 2.3.2 aDDITIONAL aDDRESS aSSIGNMENT tECHNIQUES iN MANY SYSTEMS, THE TECHNIQUES ILLUSTRATED ABOVE MAY NOT REPRESENT THE BEST SOLUTION TO THE SYSTEM PROBLEM. tHIS IS PARTICULARLY TRUE IF PRO- GRAM EXECUTION SPEED IS A PRIMARY CONSIDERATION. tHE TIME REQUIRED TO ACCESS THE PERIPHERAL DEVICES CAN BE REDUCED BY PUTTING THESE DEVICES IN pAGE zERO. tHE ENTIRE SET OF pAGE zERO ADDRESSING MODES CAN THEN BE USED TO ACCESS THESE DEVICES. iN ADDITION, THE POLLING OF THE mcs6520 CONTROL REGISTERS DURING INTERRUPT SERVICING CAN BE FACILITATED GREATLY BY PUTTING THE CONTROL REGISTERS IN SEQUENTIAL ADDRESSES. tHESE REGISTERS CAN THEN BE ACCESSED USING THE pAGE zERO, iNDEXED ADDRESSING MODE DESCRIBED IN THE pRO- GRAMMING mANUAL. tHE ADDRESS INTERCONNECT WHICH ALLOWS THIS IS SHOWN IN fIGURE 2.11. nOTE THAT THIS IMPLEMENTATION REQUIRES EXTERNAL ADDRESS DE- CODING CHIPS BUT FOR THE SYSTEM REQUIRING IT, THIS INCREMENTAL COST WILL RESULT IN HIGHER OPERATING SPEEDS. tHE SYSTEM DESIGNER MUST BECOME FAMILIAR WITH THE ADDRESSING LINES AND THEIR EFFECT ON THE ADDRESS SPACE AVAILABLE TO THE PROCESSOR. eVEN MORE IMPORTANT, THERE IS A SIGNIFICANT RELATIONSHIP BETWEEN SOFTWARE AND HARDWARE IN MICROPROCESSOR SYSTEMS AND A FULL UNDERSTANDING OF BOTH CAN ALLOW OPTIMIZATION OF THE TRADE-OFF BETWEEN SPEED AND COST FOR THE SYSTEM UNDER DESIGN. 2.3.3 iNTERRUPTS tHE BASIC CONCEPT OF INTERRUPTS IS INTRODUCED IN cHAPTER 1, sECTION 1.3.2 OF THIS MANUAL. hOWEVER, LITTLE IS SAID THERE ABOUT THE HARDWARE AND SOFTWARE TECHNIQUES WHICH ARE REQUIRED TO ASSURE PROPER IMPLEMENTATION OF -104- ============================================================================ -------- {$7c}rom {$7c} {$7c} {$7c} ----------------------O--+cs {$7c} {$7c} {$7c} -------- {$7c} {$7c} {$7c} {$7c} -------- {$7c} ------+--+rs1 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ----+--+rs0 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ------+-+---+--+cs1 {$7c}mcs6520 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} --------------- {$7c} {$7c} {$7c} {$7c} --+--+cs2 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}___ {$7c} {$7c} a15+----------------------- {$7c} {$7c} {$7c} {$7c} O--+cs3 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} a14+------> {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} a13+------> {$7c} O-+-+-+--+rs1 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a12+------> {$7c} {$7c} O-+-+--+rs0 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a11+------> {$7c} ----+-+-+-+--+cs1 {$7c}mcs6520 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a10+------> {$7c} {$7c} {$7c} {$7c} O-+--+cs2 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}___ {$7c} {$7c} a9 +------> {$7c} {$7c} {$7c} {$7c} {$7c} O--+cs3 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} a8 +------> {$7c} {$7c} --+-+-O {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} a7 +--------------------------------+-+-- O-+-+-+--+rs1 {$7c} {$7c} mcs650x {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a6 +------> {$7c} {$7c} {$7c} O-+-+--+rs0 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a5 +------> {$7c} {$7c} --+-+-+-+--+cs1 {$7c}mcs6520 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a4 +--------------------------------+-+-+-+-O O-+--+cs2 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}___ {$7c} {$7c} a3 +--------------------------------+-+-+-O {$7c} {$7c} O--+cs3 {$7c} {$7c} {$7c} ----------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} a2 +------>--------+ +------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} a1 +------>--------+ +--------- {$7c} O-+-+-+--+rs1 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a0 +------>--------+ +----------- {$7c} O-+-+--+rs0 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} 1 of 8 +------------+-+-+-+--+cs1 {$7c}mcs6520 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} decoder +--------- {$7c} {$7c} O-+--+cs2 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}___ {$7c} {$7c} {$7c} {$7c} +------- {$7c} {$7c} {$7c} {$7c} O--+cs3 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} {$7c} {$7c} +----- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- {$7c} {$7c} {$7c} +--- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}ram {$7c} {$7c} {$7c} ----------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}___ {$7c} --------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} O--+cs1 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}___ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} O-+--+cs2 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------- V V V V {$7c} {$7c} {$7c} {$7c} \_______/ {$7e} {$7e} {$7e} {$7e} to other 6520'S pAGE zERO cHIP sELECT aDDRESSING sCHEME figure 2.11 -105- ============================================================================ THE INTERRUPT SYSTEM. tHIS SECTION IS DESIGNED TO INTRODUCE THE DESIGNER TO THE DETAILS OF INTERRUPTS AND INTERRUPT SERVICING TECHNIQUES. 2.3.3.1 iNTERRUPT pRIORITIZING cHAPTER 1 MAKES REFERENCE TO VARIOUS TECHNIQUES FOR HARDWARE PRIORITIZING OF INTERRUPTS TO ALLOW MORE RAPID SERVICING OF INTERRUPTS. tHE GOAL OF THIS HARDWARE IS TO ALLOW THE PROCESSOR TO GO DIRECTLY TO THE PROGRAM WHICH SERVICES THE HIGHEST PRIORITY ACTIVE INTERRUPT WITHOUT TAKING THE TIME TO POLL EACH INTERRUPTING DEVICE. aLL HARDWARE PRIORITIZING TECHNIQUES ARE BASED ON THE "PRIORITY ENCODER" SHOWN IN fIGURE 2.12. tHIS DEVICE HAS EIGHT INPUTS WHICH ARE ASSIGNED A PRIORITY LEVEL FROM ONE TO EIGHT AND GENERATES A THREE-BIT BI- NARY CODE CORRESPONDING TO THE HIGHEST PRIORITY ACTIVE INPUT SIGNAL. tHE GENERATION OF THIS THREE-BIT CODE IS IN REALITY A TRIVIAL TASK FOR THE DESIGNER. hOWEVER, RELATING THIS CODE TO THE ADDRESS OF THE CORRE- SPONDING INTERRUPT SERVICE ROUTINE IS MUCH MORE DIFFICULT AND REPRESENTS AN OPPORTUNITY FOR CREATIVITY ON THE PART OF THE DESIGNER. sEVERAL SOLUTIONS WILL BE ILLUSTRATED HERE TODEMONSTRATEWHAT CAN BE DONE. tHESE ARE CER- TAINLY NOT ASSUMED TO BE THE ONLY SOLUTIONS. eACH SYSTEM MUST BE CONSIDERED SEPARATELY TO ASSURE THAT THE IMPLEMENTATION CHOSEN IS AS CLOSE TO OPTIMUM AS POSSIBLE. 2.3.3.2 eXAMPLE 1: sELECTING THE iNTERRUPT vECTOR tHE FINAL STEP OF INTERRUPT RESPONSE WITHIN THE PROCESSOR IS THE FETCHING OF AN INTERRUPT VECTOR FROM TWO FIXED ADDRESSES IN MEMORY. tHE INTERRUPT VECTOR LOCATED IN THESE FIXED ADDRESSES IDENTIFIES THE ADDRESS OF THE SOFTWARE WHICH THE PROCESSOR EXECUTES TO POLL THE INTERRUPTING DEVICES. iNSTEAD OF POINTING TO THE POLLING ROUTINE, IT WOULD BE MUCH FASTER TO GO DIRECTLY TO THE SOFTWARE WHICH ACTUALLY SERVICES THE INTERRUPT. tHIS RE- QUIRES A UNIQUE VECTOR FOR EACH INTERRUPT. tHE TECHNIQUE ILLUSTRATED IN fIGURE 2.12 ASSUMES THAT THE INTER- RUPT VECTORS ARE LOCATED IN rom AT ADDRESSES BELOW THAT NORMALLY ASSIGNED TO THE INTERRUPT VECTOR. tHE DECODER DETECTS THE FACT THAT THE PROCESSOR IS READING fffe OR ffff. aT THIS TIME THE ADDRESS INPUTS ad1, ad2 AND ad3 INTO THE rom ARE DRIVEN FROM THE PRIORITY ENCODER. iNSTEAD OF ACCESSING fffe OR ffff, THE INTERRUPT VECTOR WILL COME FROM TWO ADDRESSES SELECTED BY -106- ============================================================================ ------------------ ------------ {$7c} {$7c} {$7c} {$7c} {$7c} a15+-->-------------------------------------------O--+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a14+-->------------------------------------------ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a13+-->---------------------------------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a12+-->-------------------------------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a11+-->------------------------------------ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a10+-->---------------------------------O-+-+-+-+-+--+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a9 +-->-------------------------------O-+-+-+-+-+-+--+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a8 +-->-----------------------------O-+-+-+-+-+-+-+--+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a7 +-->---------------------------O-+-+-+-+-+-+-+-+--+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a6 +-->-------------------------O-+-+-+-+-+-+-+-+-+--+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a5 +-->-----------------------O-+-+-+-+-+-+-+-+-+-+--+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a4 +-->-----------O---------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} 2k x 8 {$7c} {$7c} a3 +-->---------O-+-------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} rom {$7c} {$7c} a2 +-->-------O-+-+------ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a1 +-->-----O-+-+-+---- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +-+-+-+-+-+-+-+-+++-+++-+-+-+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} and {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} \ / {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} - {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a0 +-->-----+-+-+-+----------------------+-----------+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------+--- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ----------------+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +->------+ {$7c} {$7c} {$7c} {$7c} {$7c} ------------------+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} quad +->------+ {$7c} {$7c} {$7c} {$7c} --------------------+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} 2 input +->------+ {$7c} {$7c} {$7c} ----------------------+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} data +->------+ {$7c} {$7c} {$7c} ---------------+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} select {$7c} ------------ {$7c} {$7c} -+- -------+ {$7c} {$7c} {$7c} - {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -----+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ---+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ----------- {$7c} {$7c} ^ ^ ^ {$7c} microprocessor {$7c} --------+-+-+------ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} priority {$7c} {$7c} {$7c} {$7c} encoder {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} --+-+-+-+-+-+-+-+-- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +---O {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +---+-O {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +---+-+-O {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -----+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ___{$7c} / /+---+-+-+-O {$7c} {$7c} {$7c} {$7c} {$7c} irq+-----o< ( {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} \ \+---+-+-+-+-O {$7c} {$7c} {$7c} ------------------ -----+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +---+-+-+-+-+-O {$7c} {$7c} nor {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +---+-+-+-+-+-+-O {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +---+-+-+-+-+-+-+-O {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ^ ^ ^ ^ ^ ^ ^ ^ interrupt inputs sELECTING THE iNTERRUPT vECTOR figure 2.12 -107- ============================================================================ THE PRIORITY ENCODER. tHE ACTUAL HARDWARE INVOLVED IS QUITE SIMPLE AND THE INTERRUPT RESPONSE TIME IS AN ABSOLUTE MINIMUM. 2.3.3.3 eXAMPLE 2: uSING THE pROCESSOR sOFTWARE pOWER tHESE SEVERAL SOLUTIONS TO THE VECTORED INTERRUPT PROBLEM TAKE AD- VANTAGE OF CERTAIN INSTRUCTIONS WHICH CAN BE PERFORMED BY THE PROCESSOR. tHE FIRST OF THESE USES AN INSTRUCTION CALLED THE jUMP iNDIRECT. tHIS IN- STRUCTION CAUSES THE PROCESSOR TO BEGIN EXECUTING THE PROGRAM LOCATED AT THAT ADDRESS CONTAINED IN TWO SEQUENTIAL MEMORY LOCATIONS. aS IN eXAMPLE 1, THE THREE-BIT OUTPUT FROM THE PRIORITY ENCODER BECOMES PART OF THE ADDRESS OF THE INTERRUPT SOFTWARE. iF THE OUTPUT OF THE PRICRITY ENCODER IS CONNECTED TO THE INPUTS OF A PERIPHERAL INTERFACE DEVICE, THE PROCESSOR CAN THEN PERFORM A jUMP iNDIRECT OPERATION USING THE ADDRESS ON THE TWO PERIPHERAL i/o PORTS. tHIS IS SHOWN IN fIGURE 2.13. aNOTHER SOLUTION WHICH TAKES ADVANTAGE OF THE PROCESSOR SOFTWARE IS SHOWN iN fIGURE 2.14. oNCE AGAIN THE OUTPUT OF THE PRIORITY ENCODER IS CONNECTED TO THE INPUTS OF A PERIPHERAL i/o PORT. hOWEVER, IN THIS AP- PROACH, THE PRIORITY ENCODER IS CONNECTED TO THE LOW ORDER BITS AND THE OTHER BITS CAN BE USED AS CONTROL OR INPUT LINES FOR OTHER FUNCTIONS. iN THIS METHOD, THE THREE BITS FROM THE PRIORITY ENCODER WILL BE- COME PART OF AN ADDRESS ESTABLISHED IN MEMORY. tHIS ADDRESS WILL THEN BE USED IN A jUMP iNDIRECT INSTRUCTION AS BEFORE. tHIS OPERATION IS DETAILED IN fIGURE 2.15. 2.3.4 tHE aPPLICATION OF rdy TO cONTROLLING THE mEMORY iNTERFACE tHE ABILITY TO STOP THE MICROPROCESSOR CAN BE EXTREMELY IMPORTANT WHEN USING MEMORY DEVICES WHICH ARE NOT DIRECTLY COMPATIBLE WITH THE mcs650x FAMILY. tHE rdy LINE ON THE mcs6501, mcs6502 AND mcs6505 CAN BE USED TO STOP THE PROCESSOR IN ANY "NON WRITE" CYCLE, I.E., ANY CYCLE IN WHICH THE PRO- CESSOR IS NOT ATTEMPTING TO WRITE DATA INTO MEMORY. tHE PROCESSOR CAN BE STOPPED FOR ANY NUMBER OF CLOCK CYCLES, FROM ONE CYCLE FOR INTERFACING WITH SLOW MEMORIES TO MANY CYCLES FOR dma APPLICATIONS AND FOR SINGLE CYCLE EXE- CUT ION. 2.3.4.1 iNTERFACING sLOW promS oNE OF THE PRINCIPAL APPLICATIONS OF roy IS IN THE CONTROL OF LIGHT-ERASABLE promS OR earomS. tHESE DEVICES GENERALLY HAVE LONGER ACCESS -108- ============================================================================ ------------------ ---------------- {$7c} {$7c}a15 {$7c} {$7c} pb7 \ {$7c} +---> {$7c} +--------> {$7c} {$7c} {$7c}a14 {$7c} {$7c} pb6 {$7c} to {$7c} +---> {$7c} +--------> {$7c} {$7c} {$7c}a13 {$7c} {$7c} pb5 {$7c} fixed {$7c} +---> {$7c} +--------> {$7c} {$7c} {$7c}a12 {$7c} peripheral {$7c} pb4 {$7c} address {$7c} +---> {$7c} +--------> {$7c} {$7c} {$7c}a11 {$7c} interface {$7c} pb3 {$7c} data for {$7c} +---> {$7c} +--------> {$7c} {$7c} {$7c}a10 {$7c} device {$7c} pb2 {$7c} interrupt {$7c} +---> {$7c} +--------> {$7c} {$7c} {$7c}a9 {$7c} mcs6502 {$7c} pb1 {$7c} software {$7c} +---> {$7c} +--------> {$7c} {$7c} {$7c}a8 {$7c} {$7c} pb0 {$7c} {$7c} microprocessor +---> {$7c} +--------> {$7c} {$7c} {$7c}a7 {$7c} {$7c} {$7c} {$7c} +---> {$7c} {$7c} --> {$7c} {$7c} {$7c}a6 {$7c} {$7c} {$7c} / {$7c} +---> {$7c} {$7c} {$7c} {$7c} {$7c}a5 {$7c} {$7c} pa7 {$7c} {$7c} +---> {$7c} +------- {$7c} {$7c}a4 {$7c} {$7c} pa6 {$7c} +---> {$7c} +---------<--------- {$7c} {$7c}a3 {$7c} {$7c} pa5 {$7c} {$7c} +---> {$7c} +---------<------ {$7c} {$7c} {$7c}a2 {$7c} {$7c} pa4 {$7c} {$7c} {$7c} +---> {$7c} +---------<--- {$7c} {$7c} {$7c} {$7c}a1 {$7c} {$7c} pa3 {$7c} {$7c} {$7c} {$7c} +--->-----+ rs0 +------- {$7c} {$7c} {$7c} {$7c} {$7c}a0 {$7c} {$7c} pa2 {$7c} {$7c} {$7c} {$7c} {$7c} +--->-----+ rs1 +------+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} pa1 {$7c} {$7c} {$7c} {$7c} ------------------ {$7c} +------+ {$7c} {$7c} {$7c} {$7c} {$7c} pa0 {$7c} {$7c} {$7c} {$7c} {$7c} +------+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ---------------- -+- {$7c} {$7c} {$7c} - {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -------------+--+--+--------- {$7c} {$7c} {$7c} priority {$7c} {$7c} encoder {$7c} {$7c} {$7c} --+--+--+--+--+--+--+--+--+-- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ^ ^ ^ ^ ^ ^ ^ ^ ^ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} \___________________________/ interrupt inputs note: connecting the address lines as shown puts the two mcs6520 i/o ports in sequentiaL addresses. uSING mcs6520 FOR jUMP iNDIRECT iNTERRUPT rOUTINES figure 2.13 -109- ============================================================================ ------------------ ---------------- {$7c} {$7c} {$7c} {$7c} pb7 \ {$7c} a15+---> {$7c} +-----------> {$7c} {$7c} {$7c} {$7c} {$7c} pb6 {$7c} to {$7c} a14+---> {$7c} +-----------> {$7c} {$7c} {$7c} {$7c} {$7c} pb5 {$7c} fixed {$7c} a13+---> {$7c} +-----------> {$7c} {$7c} {$7c} {$7c} peripheral {$7c} pb4 {$7c} address {$7c} a12+---> {$7c} +-----------> {$7c} {$7c} {$7c} {$7c} interface {$7c} pb3 {$7c} data for {$7c} a11+---> {$7c} +-----------> {$7c} {$7c} {$7c} {$7c} device {$7c} pb2 {$7c} interrupt {$7c} a10+---> {$7c} +-----------> {$7c} {$7c} {$7c} {$7c} mcs6502 {$7c} pb1 {$7c} software {$7c} a9 +---> {$7c} +-----------> {$7c} {$7c} micro {$7c} {$7c} {$7c} pb0 {$7c} {$7c} processor a8 +---> {$7c} +-----------> {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a7 +---> {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a6 +---> {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a5 +---> {$7c} pa7+-----------> {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a4 +---> {$7c} pa6+-----------> {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a3 +---> {$7c} pa5+-----------> {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a2 +---> {$7c} pa4+-----------> {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a1 +--->-----+ rs0 pa3+-----------> {$7c} {$7c} {$7c} {$7c} {$7c} / {$7c} a0 +--->-----+ rs1 pa2+-----------<-------------- {$7c} {$7c} {$7c} {$7c} {$7c} ------------------ {$7c} pa1+-----------<----------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} pa0+-----------<-------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ---------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} --------------------+--+--+-- {$7c} {$7c} {$7c} priority {$7c} {$7c} encoder {$7c} {$7c} {$7c} --+--+--+--+--+--+--+--+--+-- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ^ ^ ^ ^ ^ ^ ^ ^ ^ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} \___________________________/ interrupt inputs pRIORITY eNCODER cONNECTED TO lOW oRDER bITS OFmcs6520 figure 2.14A -110- ============================================================================ ----------------- \ {$7c} periheral pa7+-----> {$7c} to other {$7c} {$7c} {$7c} {$7c} interface pa6+-----> {$7c} peripheral {$7c} {$7c} {$7c} {$7c} device pa5+-----> {$7c} devices interrupt inputs {$7c} {$7c} {$7c} _______________ {$7c} (mcs6520) pa4+-----> {$7c} / \ -------------- {$7c} {$7c} {$7c} V V V V V V V V {$7c} micro +----> {$7c} {$7c} ---> {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} / -+-+-+-+-+-+-+-+- {$7c} processor +----> {$7c} pa3+--+---------<---------+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} +----> {$7c} pa2+--+---------<---------+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} a1 +---->---+rs1 pa1+--+---------<---------+ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ----------------- {$7c} a0 +---->---+rs0 pa0+--- -------------- ----------------- pRIORITY eNCODER TO pERIPHERAL iNTERFACE sCHEME figure 2.14 B intvec --> pha rECEIVE iNTERRUPT vECTOR txa pha lda ipa a0 rEAD pia pORT and #oe cLEAR pia tax tRANSFER aCC. TO x INDEX REG. lda vec tab,x lOAD aCC. FROM iNTERRUPT vECTOR tABLE STORED IN MEMORY sta jmp1 sET lOW oRDER aDDRESS bYTE OF iNTERRUPT vECTOR inx iNCREMENT x iNDEX rEGISTER lda vec tab,x lOAD aCC. FROM iNTERRUPT vECTOR tABLE sta jmp1+1 sET HIGH ORDER aDDRESS bYTE OF iNTERRUPT vECTOR jmp (jmp1) gO TO iNTERRUPT sERVICE sOFTWARE sOFTWARE pROGRAM TO iMPLEMENT iNTERRUPT FROM ABOVE hARDWARE cONFIGURATION figure 2.15 -111- ============================================================================ TIMES THAN THAT REQUIRED BY THE MICROPROCESSOR WHEN OPERATION AT 1 mhZ CLOCK FREQUENCY AND ARE INCAPABLE OF MAKING DATA AVAILABLE ON THE DATA BUS WITHIN 100 NANOSECONDS OF THE END OF THE pHASE tWO CLOCK PULSE. tHE pHASE tWO CLOCK PULSE IS USED TO LATCH DATA OR INSTRUCTIONS ON THE DATA BUS; THEREFORE, IF THE DATA IS NOT AVAILABLE AT THE CORRECT TIME, THE PROCESSOR MUST BE HELD UP FOR ONE FULL CYCLE. tHE INSTRUCTION WILL THEN BE LATCHED ON THE FOLLOWING pHASE tWO PULSE. eXECUTION OF THE INSTRUCTION WILL THEN PROCEED DURING THE NEXT CYCLE. sUGGESTED LOGIC FOR PERFORMING THIS FUNC- TION IS SHOWN IN fIGURE 2.16. nOTE THAT THE DATA PRESENT ON THE DATA BUS DURING THE O2 CLOCK PULSE AFTER roy GOES HIGH IS THE DATA THAT WILL BE USED IN THE INSTRUCTION EXECUTION WHICH TAKES PLACE DURING THE FOLLOWING CYCLE. 2.3.4.2 dIRECT mEMORY aDDRESS (dma) tECHNIQUES tRANSFER OF DATA FROM PERIPHERAL STORAGE DEVICES INTO THE MICRO- COMPUTER DATA MEMORY (ram) CAN NORMALLY BE HANDLED ONE BYTE AT A TIME UNDER CONTROL OF THE MICROPROCESSOR. hOWEVER, IN LARGE DATA TERMINALS, CONTROL SYSTEMS, ETC. THE PRIMARY DATA STORAGE DEVICE MAY HE A HIGH-SPEED TAPE OR DISK. iN SYSTEMS SUCH AS THESE, THE DATA TRANSFER FROM THE STORAGE DEVICE INTO MEMORY MUST BE PERFORMED AT SPEEDS GREATER THAN THE PROCESSOR CAN HANDLE. tHE CONTROL OF THE TRANSFER MUST BE PERFORMED OUTSIDE OF THE PRO- CESSOR IN A SEPARATE CONTROLLER AND THE PERIPHERAL DEVICE MUST GAIN DIRECT ACCESS TO THE SYSTEM ram. dIRECT mEMORY aCCESS REQUIRES PRIMARILY THAT THE PROCESSOR HAVE NO NEED TO ACCESS THE MEMORY INVOLVED. tHIS IS GENERALLY ASSURED BY STOPPING THE PROCESSOR COMPLETELY. tHE dma CONTROLLER MUST THEN GAIN ACCESS TO THE r/w LINE AND BOTH THE ADDRESS AND DATA BUSSES ON THE MEMORY UNIT. pROVISION FOR STOPPING THE PROCESSOR IS AVAILABLE ON THE mcs6501, mcs6502 AND mcs6505. tHIS IS ACCOMPLISHED BY PULLING THE roy LINE ON THE PROCESSOR TO gnd (< 0.4v). tHE PROCESSOR WILL STOP IN THE FIRST NON-WRITE CYCLE WITH THE DATA BUS IN THE HIGH-IMPEDANCE STATE. aFTER THE PROCESSOR HAS STOPPED, THE dma CONTROLLER MUST PROVIDE THE ADDRESS AND DATA FOR THE MEMORY AND MUST CONTROL r/w IF DATA IS BEING TRANSFERRED INTO MEMORY. pROVIDING ADDRESSES FOR THE MEMORIES CAN BE ACCOMPLISHED BY GATING ADDRESSES FROM EITHER THE dma CONTROLLER OR THE MICROPROCESSOR INTO THE MEMORIES. tHIS CAN BE ACCOMPLISHED VERY EASILY WITH A qUAD 2-INPUT DATA -112- ============================================================================ SELECTOR. dURING THE dma OPERATION, THE ADDRESSES FED TO THE MEMORIES ARE THOSE GENERATED BY THE dma CONTROLLER. aFTER THE dma OPERATION IS COMPLETE, THE INPUT SELECT SIGNAL TO THE DATA SELECTOR IS INVERTED AND THE ADDRESSES GENERATED BY THE PROCESSOR ONCE AGAIN DETERMINE WHICH MEMORY WORD IS BEING ACCESSED. tHE r/w LINE TO THE MEMORIES CAN BE CONTROLLED IN THE SAME WAY AS THE ADDRESS LINES. tHE DATA BUS MUST BE CONTROLLED IN A SOMEWHAT DIFFERENT MANNER. tHIS IS NECESSITATED BY THE FACT THAT THESE LINES ARE "BI-DIRECTIONAL"; THE DATA BUS PINS ON THE PROCESSOR AND THE SUPPORT CHIPS ACT AS BOTH AN INPUT AND AN OUTPUT. tHE OUTPUT BUFFERS IN EACH OF THESE CHIPS ARE CAPABLE OF ENTERING A HIGH IMPEDANCE STATE TO ALLOW ANY OF THE DEVICES TO DRIVE THE BUS DURING DATA AND INSTRUCTION TRANSFERS. fOR THIS REASON, A BI-DIREC- TIONAL, "THREE-STATE" BUS EXTENDER IS REQUIRED TO INTERFACE THE dma CON- TROLLER TO THE SYSTEM DATA BUS. tHE LOGIC NECESSARY TO PROVIDE FULL ADDRESS BUS AND DATA BUS CONTROL FOR dma APPLICATIONS IS SHOWN IN fIGURE 2.17. tHE mcs6501 PROVIDES A bUS aVAILABLE OUTPUT TO SIGNAL THE dma CON- TROLLER THAT THE PROCESSOR HAS STOPPED AND THAT THE dma CONTROLLER CAN PRO- CEED TO ACCESS MEMORY FOR READING AND WRITING DATA. tHIS SIGNAL WILL GO HIGH DURING THE pHASE tWO CLOCK IN THE FIRST rEAD CYCLE (r/w = 1) WHICH FOLLOWS roy GOING LOW. tHIS WILL OCCUR IMMEDIATELY IF rdy IS PULLED TO gnd (< 0.4v) DURING A rEAD CYCLE. tHE DISCUSSION OF THE PROCESSORS IN sECTION 1 DESCRIBES THIS IN DETAIL. tHE mcs6502, mcs6503, mcs6504 AND mcs6505 DO NOT MAKE AVAILABLE THE bUS aVAILABLE SIGNAL. hOWEVER, THESE PROCESSORS STILL STOP IN THE FIRST NON-WRITE CYCLE. fOR THIS REASON, THE LOGIC SHOWN IN fIGURE 2.17 SHOULD BE USED TO GENERATE A bUS aVAILABLE SIGNAL FOR THE dma CONTROLLER. 2.3.4.3 cONTROL OF dYNAMIC ramS IN THE mcs6500 sYSTEM fOR SYSTEMS WHICH MUST CONTAIN A LARGE QUANTITY OF rEAD/wRITE MEMORY (ram), THE 4096-BIT DYNAMIC ramS CAN PROVIDE THE REQUIRED STORAGE WITH A MINIMUM NUMBER OF PARTS. cURRENTLY AVAILABLE DYNAMIC ramS ARE CAP- ABLE OF STORING FOUR TIMES AS MUCH DATA AS SIMILAR STATIC DEVICES. hOW- EVER, THERE IS ONE MAJOR DRAWBACK TO THESE DEVICES--THEY MUST BE REFRESHED PERIODICALLY. fOR MOST DEVICES CURRENTLY AVAILABLE, THIS REFRESH PERIOD IS ABOUT 2 MILLISECONDS FOR THE ENTIRE CHIP. rEFRESHING THE ENTIRE CHIP -113- ============================================================================ / {$7c} ------------------ {$7c}---{$7c} {$7c} {$7c} {$7c} {$7c} "j-k" flip-flop {$7c}---{$7c} {$7c} --------- address {$7c} {$7c} prom address {$7c} {$7c} {$7c} {$7c}---{$7c} +--------O---+j {$7c} lines {$7c} {$7c} detection {$7c} {$7c} {$7c} {$7c} {$7c}---{$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ----+--o{$7c}c {$7c} {$7c}---{$7c} {$7c} {$7c} {$7c} {$7c} {$7c} \ ------------------ {$7c} {$7c} {$7c} _{$7c} {$7c} O---+k q+---------rdy {$7c} {$7c} {$7c} {$7c} p1 clock --------------------------- {$7c} --------- {$7c} o {$7c} {$7c} --------- iNTERFACING sCHEME FOR sLOW promS figure 2.16 "d" type r/w ----------------------- flip-flop {$7c} ---- --------- {$7c}\ -----+ \ {$7c} {$7c} {$7c} \ {$7c} )o----+d q+-- rdy --------------+ >---------+ / {$7c} {$7c} {$7c} / ---- {$7c} {$7c} {$7c}/ {$7c} {$7c} {$7c} _{$7c} phase 2 -------------------------------------o{$7c}c q+----------- ba {$7c} {$7c} --------- lOGIC uSED TO gENERATE bUS aVAILABLE sIGNAL FOR dma aPPLICATIONS figure 2.17 -114- ============================================================================ REQUIRES 32 rEAD OPERATIONS WHICH CAN BE PERFORMED ALL AT ONCE EVERY 2 MILLISECONDS, OR 1 APPROXIMATELY EVERY 64 MICROSECONDS. uNLESS A SEPARATE CONTROLLER IS USED TO PERFORM THIS REFRESH OPERATION, THE USE OF DYNAMIC MEMORIES CAN BE VERY DETRIMENTAL TO SYSTEM PERFORMANCE. aS WITH ANY dIRECT mEMORY aCCESS, THE PROCESSOR MUST BE STOPPED TO ASSURE THAT THE PROCESSOR AND THE dma CONTROLLER ARE NOT ATTEMPTING TO ACCESS THE MEMORIES CONCURRENTLY. tHE roy INPUT PROVIDES THIS CAPABILITY. a COUNTER OPERATING DIRECTLY FROM THE SYSTEM CLOCK WILL PROVIDE A VERY CON- VENIENT REFRESH SIGNAL. eACH TIME THE COUNTER GOES THROUGH A COUNT OF 63, A "REFRESH REQUEST" PULSE IS GENERATED. tHE ACTUAL MEMORY REFRESH OPERA- TION MUST TAKE PLACE DURING A rEAD OPERATION WITH THE PROCESSOR STOPPED FOR 1 CYCLE. dETERMINING WHEN THE PROCESSOR HAS STOPPED IS EXACTLY THE SAME PROBLEM AS IN dma OPERATIONS. tHE mcs6501 WILL GENERATE A bUS aVAILABLE PULSE WHEN THE PROCESSOR HAS STOPPED. iN THE OTHER PROCESSORS, THE CONTROL- LER MUST PULL THE roy LINE LOW AND MUST THEN EXAMINE THE r/w LINE TO DETER- MINE WHEN THE PROCESSOR IS IN A rEAD CYCLE. tHE SPECIFIC OPERATION PERFORMED DURING THE REFRESH CYCLE IS A FUNCTION OF THE DEVICES BEING USED. hOWEVER, IT SHOULD BE NOTED THE TIME AVAILABLE FOR REFRESHING THE MEMORY IS "n - 1/2" CYCLES, WHERE n IS THE NUMBER OF CYCLES THAT THE PROCESSOR IS STOPPED. tHIS FORMULA IS BASED ON THE FACT THAT THE FIRST HALF CYCLE IS LOST DUE TO THE FACT THAT ba DOES NOT GO HIGH UNTIL O2 IN THE mcs6501 AND THAT THE STATE OF THE r/w LINE CANNOT BE CONSIDERED VALID UNTIL O2. cONTROL OF THE MEMORY ADDRESS LINES MUST BE RETURNED TO THE PROCESSOR AT THE BEGINNING OF O1 IF THE MEMORIES ARE TO HAVE A FULL CYCLE TO MAKE VALID DATA AVAILABLE ON THE DATA BUS. tHIS LEAVES ONE-HALF CYCLE AVAILABLE TO PERFORM THE REFRESH OPERATION IF THE PROCESSOR IS STOPPED FOR ONE CYCLE. a FULL 1-1/2 CYCLES CAN BE MADE AVAILABLE BY STOPPING THE PROCESSOR FOR TWO CYCLES. tHIS LATTER IMPLEMENTATION IS MORE COMPATIBLE WITH MOST DYNAMIC ramS CURRENTLY AVAILABLE. aS DESCRIBED ABOVE, A PRIMARY PROBLEM IN THE IMPLEMENTATION OF DYNAMIC ram SYSTEMS IS KNOWING WHEN THE PROCESSOR HAS STOPPED. a FULL ONE- HALF CYCLE IS REQUIRED IN THE IMPLEMENTATIONS DESCRIBED ABOVE. tHE mcs6502, HOWEVER, PROVIDES A SIGNAL WHICH CAN BE USED TO PREDICT THAT THE PROCESSOR WILL STOP IN THE VERY NEXT CYCLE. tHIS IS THE sync SIGNAL. iT IS IMPOSSIBLE -115- ============================================================================ FOR A wRITE OPERATION TO IMMEDIATELY FOLLOW AN INSTRUCTION FETCH CYCLE. tHIS ALLOWS THE MEMORY REFRESH CONTROLLER TO ASSUME CONTROL OF THE ADDRESS LINES AT THE BEGINNING OF THAT CYCLE INSTEAD OF AFTER THE TRAILING EDGE OF O1. tHE rdy LINE IS PULLED LOW ON O1 AND THE PROCESSOR IS GUARANTEED TO STOP. cONTROL OF THE ADDRESS LINES IS RETURNED TO THE PROCESSOR ON THE NEXT O1 AND rdy IS SET HIGH AT THE SAME TIME. tHE RESULT IS THE REFRESH LOGIC HAD A FULL 1 CYCLE TO REFRESH THE MEMORIES AND THE PROCESSOR LOST ONLY 1 CYCLE OF EXECUTION TIME. a SUGGESTED CONFIGURATION FOR THIS CONTROL LOGIC IS SHOWN IN fIGURE 2.18. ----- ------------------+ \ refresh {$7c} {$7c} )o------ grant ----- ------- {$7c} ------- ----+ / refresh ----O--+ \ {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ----- (to rdy and {$7c} {$7c} )-----+d q+---O---+d {$7c} {$7c} refresh request ----+--+ / {$7c} {$7c} {$7c} {$7c} {$7c} control) {$7c} ----- {$7c} {$7c} {$7c} {$7c} {$7c} sync {$7c} {$7c} {$7c} {$7c} _{$7c} {$7c} {$7c} ---o{$7c}c {$7c} ---o{$7c}c q+---- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ------- {$7c} ------- {$7c} {$7c} o {$7c} o {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -----------+------O------+------- {$7c} {$7c} {$7c} {$7c} p2 ---------------O-------------- cONTROL lOGIC FOR rEFRESH sIGNAL FOR dYNAMIC rams figure 2.18 -116- ============================================================================ 2.3.5 hOLD-tIME cONTROL--mcs6501 tHE DATA BUS HOLD TIME REQUIRED BY THE mcs6500 FAMILY PARTS IS DE- FINED IN cHAPTER 1. eACH CHIP IN THE SYSTEM REQUIRES THAT THE DATA ON THE DATA BUS BE HELD FOR 10 NANOSECONDS PAST THE TRAILING EDGE OF THE pHASE tWO CLOCK PULSE. aLSO, EACH DEVICE IS GUARANTEED TO HOLD DATA FOR THIS LENGTH OF TIME TO ASSURE PROPER OPERATION OF THE OTHER DEVICES IN THE SYSTEM. tHIS ONLY ASSURES THAT THE FAMILY PARTS WILL WORK TOGETHER. oPERATING WITH OTHER ramS AND PERIPHERAL DEVICES REQUIRES THAT A CAREFUL STUDY BE MADE OF THE TIMING REQUIREMENTS. tHIS SECTION DISCUSSES TECHNIQUES FOR PROPERLY INTERFACING ramS WHICH REQUIRE MORE THAN 10 NS HOLD TIME GUARANTEED BY THE PROCESSOR. tHESE TECHNIQUES ARE APPLICABLE PRIMARILY TO THE mcs6501 SINCE THIS DEVICE USES THE INPUT CLOCKS AND THE dbe INPUT. tHE DATA WHICH IS TO HE WRITTEN INTO MEMORY IS ACTUALLY AVAILABLE ON THE INPUTS TO THE PROCESSOR DATA BUS BUFFERS FROM THE BEGINNING OF THE pHASE oNE CLOCK PULSE. tHIS DATA IS NORMALLY GATED ONTO THE BUS DURING pHASE tWO. hOWEVER, IF GREATER HOLD TIME IS REQUIRED, THE DESIGNER CAN TAKE ADVANTAGE OF THE FACT THAT THIS DATA CAN REALLY BE GATED OUT DURING pHASE oNE. tHIS REQUIRES THAT A DELAY BE PROVIDED BETWEEN THE pHASE tWO AND pHASE oNE CLOCK PULSES. tHE dbe OUTPUT CAN THEN BE CONNECTED TO A pHASE oNE PULSE TO CAUSE THE DATA TO REMAIN ON THE BUS PAST pHASE tWO PULSE WHICH IS USED TO LATCH DATA IN MEMORY. tHIS TIMING IS SHOWN IN fIGURE 2.19. -117- ============================================================================ ----- ------ {$7c} {$7c} {$7c} {$7c} p1 ------- ----------- -------- {$7c} {$7c} p2 ---- ------ {$7c} ----- {$7c} {$7c} {$7c} {$7c} {$7c} ---------- ---+-------- {$7c} {$7c} {$7c} {$7c} -------- --------+--+- ---------- address bus x {$7c} {$7c} x -------- --------+--+- ---------- {$7c} {$7c} {$7c} {$7c} -------- {$7c} {$7c} ----------- r/w \ {$7c} {$7c}/ --------+--+ {$7c} {$7c} __ {$7c} {$7c} dbe(p1) ----- --------+--- --------- {$7c} {$7c} {$7c} {$7c} {$7c} ------ {$7c} ----- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c}{$7c} {$7c} ----\ /---+--+\ /------ data bus {$7c}>------<{$7c} {$7c} {$7c}{$7c}>--<{$7c} ----/ \---+--+/ \------ {$7c} {$7c} {$7c} {$7c}{$7c} {$7c} {$7c} {$7c} -->{$7c} {$7c}<-- extra hold time tIMING aNALYSIS OF dATA hOLD tIME figure 2.19 -118- ============================================================================ 2.4 additional system considerations aFTER THE BASIC SYSTEM CONFIGURATION IS COMPLETE, EXTENSIVE BREADBOARDING AND TESTING IS USUALLY REQUIRED BEFORE THE DESIGN IS FINALIZED. hOWEVER, THIS BREADBOARDING AND EVALUATION MUST BE PRECEDED BY A COMPLETE EVALUATION OF THE COST AND PERFORMANCE OF THE PROPOSED DESIGN TO ASSURE THAT THE VARIOUS GOALS OF THE PROJECT WILL BE MET. tHE FIRST STEP IN EVALUATING THE DESIGN IS TO ESTIMATE THE AMOUNT OF rom AND ram WHICH WILL BE REQUIRED AND TO ESTIMATE THE NUMBER AND TYPE OF INTERFACE DEVICES REQUIRED TO CONTROL THE PERIPHERALS 2.4.1 pERIPHERAL iNTERFACE dEVICES tHE NUMBER AND TYPE OF PERIPHERAL DEVICES CAN GENERALLY BE ESTIMATED VERY ACCURATELY. hOWEVER, IT IS IMPORTANT TO KEEP IN MIND THAT THESE ESTI- MATES MUST BE SUBJECT TO REVIEW AFTER A FULL ANALYSIS OF SYSTEM PERFORMANCE IS COMPLETED. tHE DESIGNER MAY FIND IT NECESSARY TO USE A SPECIAL-PURPOSE INTERFACE PART OR TO REDESIGN THE i/o STRUCTURE IF THE EVALUATION OF SYSTEM PERFORMANCE REVEALS THAT THE SYSTEM CANNOT OPERATE AT THE REQUIRED SPEED. uSE OF SPECIAL-PURPOSE PERIPHERAL INTERFACE PARTS WILL REDUCE THE NUMBER OF TASKS WHICH MUST BE HANDLED BY THE PROCESSOR AND CONSEQUENTLY CAN INCREASE THE OVERALL SYSTEM SPEED, BUT THIS GENERALLY INVOLVES ADDITIONAL COMPONENT COST. lIKEWISE, THE USE OF A FULLY VECTORED INTERRUPT CAN LEAD TO INCREASED PERFORMANCE AT INCREASED COST. tHE GOAL OF ANY DESIGN PROGRAM MUST BE TO MEET ALL THE SYSTEM PERFORMANCE AT THE MINIMUM POSSIBLE COST. aFTER THE VARIOUS PERIPHERAL DEVICES IN THE SYSTEM HAVE BEEN EVALU- ATED TO DETERMINE THE NUMBER OF INPUTS AND OUTPUTS REQUIRED, THE TOTAL RE- QUIRED BY ALL PERIPHERALS CAN BE DIVIDED BY 16 TO DETERMINE THE NUMBER OF DEVICES REQUIRED. tHIS IS A GOOD FIRST APPROXIMATION WHICH WILL BE RE- EVALUATED AS THE SYSTEM DEVELOPMENT PROGRESSES. 2.4.2 ram tHE EVALUATION OF THE AMOUNT OF ram REQUIRED BY THE SYSTEM IS A SOME- WHAT MORE DIFFICULT PROBLEM THAN ESTIMATION OF PERIPHERAL DEVICES. tHIS IS DUE PRIMARILY TO THE FACT THAT MUCH OF THE ram IS REQUIRED BY THE SYSTEM SOFTWARE AS WORKING STORAGE, SUCH AS STORAGE OF IMMEDIATE RESULTS IN -119- ============================================================================ ARITHMETIC OPERATIONS. sINCE THE SYSTEM PROGRAM WILL PROBABLY NOT BE WRITTEN WHEN THESE ESTIMATES ARE FIRST ATTEMPTED, THE PROBABILITY OF ERROR IN THIS PORTION OF THE ESTIMATE MAY BE FAIRLY HIGH. iN ADDITION TO WORKING STORAGE, THE ram MUST PROVIDE STORAGE FOR: 1. tHE sTACK; THIS IS DESCRIBED IN THE pROGRAMMING mANUAL. 2. pERIPHERAL INPUT DATA STORAGE. 3. pERIPHERAL OUTPUT DATA STORAGE. iTEMS 2 AND 3 ABOVE CAN BE EVALUATED QUITE ACCURATELY SINCE A DE- TAILED ANALYSIS OF THE PERIPHERAL DEVICES HAS USUALLY BEEN COMPLETED WHEN THESE ESTIMATES ARE FIRST ATTEMPTED. iN GENERAL, A BLOCK OF ram MUST BE MADE AVAILABLE FOR EACH PERIPHERAL DEVICE. tHE AMOUNT OF ram REQUIRED FOR EACH IS A FUNCTION OF THE TYPE OF PERIPHERAL DEVICE BEING INTERFACED AND JUST HOW THE DEVICE IS TO BE CONTROLLED. tHE AMOUNT OF ram REQUIRED BY THE STACK IS A FUNCTION OF BOTH THE INTERRUPT STRUCTURE AND THE SYSTEM SOFTWARE. aS A RESULT, AN ESTIMATE OF THIS REQUIREMENT MUST BE BASED ON THE SYSTEM PROGRAMMER'S BEST ESTIMATES OF HIS REQUIREMENTS. tHIS SHOULD BE COMBINED WITH AN ESTIMATE OF THE RE- QUIRED WORKING STORAGE AND THE PERIPHERAL DATA STORAGE REQUIREMENTS TO OB- TAIN AN ESTIMATE OF THE TOTAL SYSTEM ram. 2.4.3 rom tHE AMOUNT OF rom REQUIRED IN A SYSTEM CANNOT BE DETERMINED ACCU- RATELY UNTIL THE SYSTEM PROGRAM IS COMPLETED. hOWEVER, BY PARTITIONING THE SYSTEM PROGRAM INTO DEFINABLE PIECES, AN ESTIMATE CAN BE MADE OF EACH TASK AND THE TOTAL CAN BE OBTAINED OF THE rom REQUIRED BY EACH SECTION. mOST PROGRAMS CONSIST OF EASILY DEFINED SECTIONS SUCH AS THE SOFTWARE FOR EACH PERIPHERAL DEVICE, ARITHMETIC ROUTINES, ETC. tHESE ARE THE PIECES WHICH SHOULD BE EXAMINED SEPARATELY TO ESTIMATE THE rom REQUIRED BY EACH. -120- ============================================================================ 2.5 evaluating system performance aS DISCUSSED IN THE PREVIOUS SECTION, THE PERIPHERAL INTERFACE STRUCTURE FOR A SYSTEM IS FAIRLY EASY TO CONFIGURE IF ONE ASSUMES THAT mcs6520-TYPE DE- VICES ARE USED. hOWEVER, BEFORE GOING TOO FAR INTO HARDWARE CONSTRUCTION, IT IS IMPORTANT THAT THE TOTAL SYSTEM PERFORMANCE BE EVALUATED TO MINIMIZE THE PROBA- BILITY THAT MAJOR PROBLEMS WILL ARISE IN THE LATER STAGES OF THE DESIGN. eVALUATING SYSTEM PERFORMANCE INVOLVES FIRST DETERMINING WHETHER OR NOT THE PROCESSOR IS CAPABLE OF PROCESSING ALL INTERRUPTS WITH THE SPEED REQUIRED AND THEN DETERMINING THAT THE PROCESSOR HAS SUFFICIENT TIME TO PERFORM NON- INTERRUPT OPERATIONS. tHE PRIORITIZED INTERRUPT STRUCTURE ASSUMES THAT AT TIMES, MORE THAN ONE INTERRUPT WILL OCCUR AND THAT THERE WILL BE DELAYS ENCOUNTERED IN SERVICING SOME INTERRUPTS CAUSED BY THE PRESENCE OF OTHER INTERRUPTS. tHIS STRUCTURE WILL PER- FORM SATISFACTORILV IF THESE DELAYS ARE NOT TOO GREAT. tHE INTERRUPT PROCESSING TIME SHOULD BE EVALUATED STARTING WITH THE HIGHEST PRIORITY INTERRUPT, THEN GOING TO THE NEXT HIGHEST PRIORITY, EACH TIME KEEPING IN MIND THE TOTAL TIME WHICH CAN BE LOST DUE TO CONCURRENT HIGHER PRIORITY INTERRUPTS. eACH TIME AN INTERRUPT IS EXAMINED, THE WORST MICROPROCESSOR RE- SPONSE TIME WHICH CAN BE ENCOUNTERED SHOULD BE ESTIMATED. iF THIS TIME IS STILL ADEQUATE FOR THE FUNCTION BEING HANDLED BY THE INTERRUPT, THAT ASPECT OF THE SYSTEM OPERATION CAN HE EXPECTED TO PERFORM SATISFACTORILY. tHE ABILITY OF THE mcs650x MICROPROCESSORS TO HANDLE INTERRUPTS QUICKLY AND CONVENIENTLY REPRESENTS ONE OF THE REAL STRENGTHS OF THIS MICROPROCESSOR FAMILY. hOWEVER, IN ANY SYSTEM BEING DEVELOPED, IT IS IMPORTANT THAT THE PERCENTAGE OF PROCESSOR TIME SPENT SERVICING INTERRUPTS NOT BE SO LARGE THAT THE INTERNAL DATA HANDLING, ARITHMETIC OPERATIONS, ETC. CANNOT BE EXECUTED PROPERLY. sINCE THE INTERRUPTS ARE USUALLY ASYNCHRONOUS AND ARE NOT RELATED DIRECTLY TO THE MAIN LINE PROGRAM, THE TIME LOST TO INTERRUPTS CAN USUALLY BE VIEWED AS AN AVERAGE PERCENTAGE OF THE TOTAL TIME. tHE SPEED WITH WHICH THE MAIN PROGRAM CAN BE EXECUTED WILL BE REDUCED BY THIS PERCENTAGE. tHE INTERRUPT SERVICE ROUTINES ARE USUALLY SHORT AND EASY TO EVALUATE. hOWEVER, THE MAIN PROGRAM IS MUCH MORE DIFFICULT TO ESTIMATE. fORTUNATELY, IT IS ALSO USUALLY MUCH LESS CRITICAL. tHOSE OPERATIONS WHICH MUST MEET A -121- ============================================================================ PARTICULAR SPEED REQUIREMENT CAN BE EXAMINED IN DETAIL BY THE PROGRAMMER TO DE- TERMINE THE EXECUTION TIME. tHIS ESTIMATED EXECUTION TIME MUST THEN BE REDUCED TO ALLOW FOR THE TIME LOST TO INTERRUPTS. tHE FINAL STEP TO ASSURING SATISFACTORY SYSTEM PERFORMANCE IS A WORST-CASE ANALYSIS. tHIS IS TO DETERMINE IF THERE ARE ANY PLACES IN THE PROGRAM WHERE WORST-CASE INTERRUPTS CAN CAUSE EXCESSIVE DELAYS IN THE EXECUTION OF OTHER PRO- GRAMS BEING EXECUTED. aLTHOUGH THE EFFORT INVOLVED IN A COMPLETE WORST-CASE ANALYSIS IS USUALLY EXCESSIVE, THIS IS ONE PART OF THE SYSTEM DEVELOPMENT TASK WHICH CON LEAD TO SIGNIFICANTLY GREATER ASSURANCE OF SUCCESS FOR THE ENTIRE DE- VELOPMENT PROCESS. -122- ============================================================================ chapter 3 bringing up the mcs6500 microcomputer system 3.0 introduction to microcomputer testing aFTER MANY HOURS OF PLANNING, HARDWARE CONSTRUCTION, AND PROGRAMMING EFFORT, THE MICROCOMPUTER SYSTEM DESIGNER MUST FACE WHAT CAN BE HIS MOST DIFFICULT TASK: "BRINGING UP" HIS SYSTEM. tHE MODERN MICROCOMPUTER WITH ITS MINIMUM CHIP COUNT, AND ITS MINIMUM NUMBER OF CONTROL AND DATA LINES REPRESENTS A TREMENDOUS ADVANCE IN SYSTEM DESIGN WHEN EVERYTHING IS WORKING PROPERLY. hOWEVER, IT CAN ALSO REPRE- SENT A TESTING NIGHTMARE TO THE DESIGNER WHO IS ATTEMPTING TO TROUBLE-SHOOT THE HARDWARE AND SOFTWARE WHICH CONSTITUTE THE TOTAL DESIGN. a MICROCOMPUTER LACKS MANY OF THE THINGS WHICH MAKE TESTING OF CONVENTIONAL LOGIC RELATIVELY CONVENIENT. tO BEGIN WITH, ONE SIMPLY CANNOT SEE MOST OF THE CONTROL SIGNALS, DATA TRANSFERS, ETC. WHICH ALLOW THE SYSTEM TO OPERATE. iN ADDITION, IT IS IMPOSSIBLE TO EXAMINE DIRECTLY THE CONTENTS OF THE REGISTERS AND LATCHES WHICH STORE DATA WITHIN THE PROCESSOR. tHIS DATA CAN ONLY BE EXAMINED INDIRECTLY BY LOOKING AT THE SIGNALS ON THE INPUTS AND OUTPUTS TO THE CHIP AT THE PROPER TIME. tHIS PROBLEM IS COMPOUNDED BY THE FACT THAT MANY PROGRAMS MUST BE TESTED "DYNAMICALLY"; I.E., THE SYSTEM MUST BE RUNNING AT ITS FULL OPERATING SPEED WITH NON-RECURRING EVENTS OR WITH A TOTAL LACK OF USABLE OSCILLOSCOPE TRIGGERING SIGNALS. fOR THESE AND MANY OTHER REASONS, IT IS IMPORTANT THAT THE SYSTEM DESIGNER BUILD EFFECTIVE TESTING CAPABILITY INTO BOTH HIS HARDWARE AND HIS SOFTWARE. tHIS IS PARTICULARLY TRUE FOR THE PRE-PRODUCTION PROTOTYPES. wHEN COMBINED WITH THE PROCEDURES DISCUSSED BELOW, THIS WILL MINIMIZE BOTH THE TIME AND THE EFFORT SPENT IN PRODUCING THAT FIRST OPERATIONAL SYSTEM. aFTER THE PROGRAM AND THE HARDWARE ARE COMPLETELY DEBUGGED, MANY OF THE TESTING TOOLS DISCUSSED BELOW CAN BE REMOVED FROM THE PROTOTYPE DESIGN WITHOUT AFFECTING SYSTEM PERFORMANCE. tHIS ALLOWS THE DESIGNER TO ARRIVE AT HIS FINAL PRODUCTION DESIGN VERY SHORTLY AFTER HE HAS PROVEN THAT THE PROTOTYPES ARE OPERATING SATISFACTORILY. -123- ============================================================================ 3.1 static testing 3.1.1 iNTRODUCTION sTATIC TESTING, I.E., EXECUTION OF THE PROGRAM, ONE CYCLE OR ONE INSTRUCTION AT A TIME, IS THE FIRST STEP IN THE CHECKOUT OF ANY SYSTEM. iN THIS WAY, THE GENERAL FLOW OF THE PROGRAM CAN BE EXAMINED AND FOR MUCH OF THE PROGRAM THE VALIDITY OF DATA TRANSFERS INTO AND OUT OF MEMORY CAN BE VERIFIED. aS SHOWN IN fIGURE 3.1, THE LOGIC NECESSARY TO CONTROL rdy TO ALLOW sINGLE cYCLE AND sINGLE iNSTRUCTION eXECUTION IS RELATIVELY SIMPLE. tHIS HARDWARE AND ITS USE IN SYSTEM TESTING ARE DISCUSSED BELOW. 3.1.2 sINGLE cYCLE eXECUTION tHE TIMING REQUIRED FOR sINGLE cYCLE eXECUTION IS SHOWN IN fIGURE 3.2. iN THIS OPERATION, THE rdy LINE HAS BEEN BROUGHT LOW (gnd) TO HALT THE PROCESSOR. tO ALLOW EXECUTION OF A SINGLE CYCLE, THE rdy LINE GOES HIGH (+2.4V), FOR ONE CYCLE EACH TIME THE sINGLE cYCLE SWITCH IS ACTI- VATED. nOTE THAT THE rdy LINE GOES HIGH WHILE THE p1 CLOCK IS HIGH AND THE INTERNAL TIMING COUNTER ADVANCES ON THE NEXT p1 CLOCK PULSE. sINGLE CYCLE OPERATION ALLOWS STOPPING THE PROCESSOR IN ANY CYCLE EXCEPT A write CYCLE. tHIS ALLOWS DETAILED EXAMINATION OF ALL CYCLES OF THE INSTRUCTION FETCH OPERATION. iN ADDITION, IT PERMITS DETAILED EXAMINA- TION OF OPERAND FETCHES. tHUS, IT IS POSSIBLE TO VERIFY THE OPERATION OF MOST OF THE HARDWARE INVOLVED IN MEMORY ADDRESSING AND CONTROL. iT IS ALSO POSSIBLE TO VERIFY THE OPERATION OF MOST OF THE PERIPHERAL INTERFACE HARD- WARE. tHIS CAN GREATLY REDUCE THE TIME REQUIRED TO TEST THE FULL DYNAMIC OPERATION OF THE PERIPHERAL DEVICE. nOTE THAT IF DEPRESSING THE sINGLE cYCLE SWITCH ALLOWS THE PROCESSOR TO ADVANCE INTO A write CYCLE, THE PROCESSOR WILL COMPLETE THIS CYCLE AND WILL THEN STOP IN THE FIRST read CYCLE (r/w = 1) WHICH FOLLOWS. tHIS TIM- ING IS SHOWN IN fIGURE 3.2. aPPENDIX a CONTAINS A DETAILED SUMMARY OF THE DATA WHICH SHOULD APPEAR ON THE ADDRESS AND DATA LINES DURING EACH CYCLE OF THE mcs6501 AND mcs6502 INSTRUCTIONS. nOTE THAT THE PROCESSOR OFTEN PUTS OUT AN ADDRESS AND FETCHES DATA WHICH IT IGNORES. tHIS IS AN INHERENT FEATURE OF THE PROCESSOR WHICH USES A "LOOK AHEAD" APPROACH TO PIPELINING. eXAMINATION OF THE sync SIGNAL WILL ALLOW THE DESIGNER TO KEEP TRACK OF EXACTLY WHEN THE DATA FETCHED FROM MEMORY IS UTILIZED WITHIN THE PROCESSOR AND WHEN IT IS IGNORED. -124- ============================================================================ [ hard125.gif ] sUGGESTED sTATIC tEST cONTROL lOGIC figure 3.1 -125- ============================================================================ --- --- --- --- --- --- --- -/- --- --- --- --- --- p1 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -- --- --- -/- --- --- --- --- --- --- --- --- --- -- -- --- --- -/- --- --- --- --- --- --- --- --- --- -- p2 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} --- --- --- --- --- --- --- -/- --- --- --- --- --- ----- /---------------------------------------- "halt" switch {$7c} --------/ ----------------- /------ "single cycle" switch {$7c} {$7c} (note 3) --------------/ ----------------- ------- ----- ----- rdy {$7c} {$7c} {$7c} {$7c} {$7c} ------------- ----------------- ----------- -- --- --------------- --------------- --- ---- ----- address bus x x x x x x -- --- --------------- --------------- --- ---- ----- - ---/----------- -----/-------- - - --- data bus ---< >--< x x >--< >--< - ---/----------- -----/-------- - - --- --------------------------------------- ----------- r/w {$7c} {$7c} ----- internal processor states ----------------- ------- t0 {$7c} {$7c} {$7c} ------ -------------------------- --------------------- t1 {$7c} {$7c} ---------------------- ------------ ------ t2 {$7c} {$7c} ------------------------------------------ ------- notes: 1. -/- indicates an undetermined time period during which the signal will change. 2. the data bus enters the high- impedance state during each phase one pulse. however, while the processor is stopped the data bus will appear to remain high or low as shown 3. switch actuation is indicated by a low signal. sINGLE cYCLE tIMING figure 3.2 -126- ============================================================================ a VERY SIMPLE "DATA TRAP" CAN BE BUILT INTO PROTOTYPE SYSTEMS TO ALLOW EXAMINATION OF THE ADDRESS AND DATA GENERATED BY THE PROCESSOR DURING write CYCLES. tHIS TRAP MAY LATCH THE CONTENTS OF BOTH THE ADDRESS AND DATA BUSSES OR IT MAY LATCH ONLY THE ADDRESS BUS. tHE LATTER CAN BE SUF- FICIENT IF A SEPARATE MEANS OF EXAMINING DATA IN MEMORY IS PROVIDED (SEE sECTION 3.3). a SUGGESTED CONFIGURATION FOR THE "DATA TRAP" IS SHOWN IN fIGURE 3.3. tHIS CIRCUIT CAN BE USED TO DISPLAY THE CONTENTS OF THE AD- DRESS AND DATA BUSSES FOR BOTH read AND write CYCLES. tHE write DATA IS LATCHED AND HELD DURING THE NEXT read CYCLE. dEPRESSING THE lATCH rESET SWITCH THEN OPENS THE INPUTS TO THE LATCHES AND ALLOWS MONITORING OF THE SUBSEQUENT read CYCLES. 3.1.3 sINGLE iNSTRUCTION eXECUTION wHILE IT IS EXTREMELY USEFUL TO BE ABLE TO ANALYZE THE EXECUTION OF EACH INSTRUCTION IN DETAIL, IT IS OFTEN SUFFICIENT JUST TO LOOK AT THE GEN- ERAL PROGRAM FLOW. tHIS IS PARTICULARLY USEFUL WHEN EXAMINING THE OPERA- TION OF BRANCHES AND JUMPS IN A PROGRAM. sINGLE INSTRUCTION EXECUTION IS DESIGNED TO ALLOW THIS CAPABILITY ON THE mcs6502 WHICH OUTPUTS A sync SIG- NAL. tHE OPERATION OF THE SINGLE INSTRUCTION EXECUTION LOGIC IS BASED ON GENERATION OF A sync SIGNAL WITHIN THE PROCESSOR. tHIS SIGNAL GOES HIGH (> +2.4V dc) DURING EACH op code FETCH CYCLE. sINGLE INSTRUCTION EXECU- TION IS IMPLEMENTED BY USING sync TO FORCE rdy LOW (< +0.4V dc). uNDER THESE CONDITIONS, THE PROCESSOR WILL ALWAYS STOP WITH AN op code ADDRESS ON THE ADDRESS BUS AND THE op code ON THE DATA BUS. tHE TIMING FOR THIS OPERATION IS SHOWN IN fIGURE 3.4. nOTE THAT THIS DIAGRAM ASSUMES THAT THE PROCESSOR IS STOPPED IN AN op code FETCH CYCLE. dEPRESSING THE sINGLE iNSTRUCTION SWITCH (fIGURE 3.1) ALLOWS EXECUTION OF THAT INSTRUCTION. tHE PROCESSOR THEN STOPS WHEN THE NEXT op code IS FETCHED. -127- ============================================================================ ----------- ab0 ----------------+ +----------------ab0 ab1 ----------------+ +----------------ab1 ab2 ----------------+ 8 +----------------ab2 ab3 ----------------+ +----------------ab3 ab4 ----------------+ bit +----------------ab4 ab5 ----------------+ +----------------ab5 ab6 ----------------+ latch +----------------ab6 ab7 ----------------+ +----------------ab7 ---+ {$7c} {$7c} ----------- {$7c} {$7c} ----------- ab8 -------------+--+ +----------------ab8 ab9 -------------+--+ +----------------ab9 ab10-------------+--+ 8 +----------------ab10 ab11-------------+--+ +----------------ab11 ab12-------------+--+ bit +----------------ab12 ab13-------------+--+ +----------------ab13 ab14-------------+--+ latch +----------------ab14 ab15-------------+--+ +----------------ab15 +--+ {$7c} {$7c} ----------- {$7c} {$7c} ----------- db0 -------------+--+ +----------------db0 db1 -------------+--+ +----------------db1 db2 -------------+--+ 8 +----------------db2 db3 -------------+--+ +----------------db3 db4 -------------+--+ bit +----------------db4 db5 -------------+--+ +----------------dbs db6 -------------+--+ latch +----------------db6 db7 -------------+--+ +----------------db7 +--+ {$7c} {$7c} ----------- {$7c} -------------------------------------- {$7c} {$7c} ___ ----- {$7c} run ----------------+ \ {$7c} {$7c} and )-------------------- {$7c} --+ / {$7c} {$7c} {$7c} ----- o {$7c} {$7c} --------- {$7c} /o {$7c} s {$7c} {$7c} / reset latch ------+d q+---- o {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -+- {$7c} {$7c} -+- - {$7c} {$7c} d type flip - flop - {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ----- {$7c} {$7c} p2 ----------------+ \ {$7c} {$7c} ___ {$7c}\ {$7c} and )--------------o{$7c}c {$7c} r/w ----+ >o--------+ / {$7c} {$7c} {$7c}/ ----- --------- mICROPROCESSOR sINGLE cYCLE dATA tRAP figure 3.3 -128- ============================================================================ -- --- --- --- --- /- --- --- --- --- --- --- --- -- p1 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} --- --- --- --- -/ --- --- --- --- --- --- --- --- --- --- --- --- -/ --- --- --- --- --- --- --- --- p2 {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -- --- --- --- --- /- --- --- --- --- --- --- --- -- ---------- /--------------------------+----- halt switch {$7c} {$7c} ---------/ {$7c} {$7c} {$7c} ----------------------+----- sing. inst sw {$7c} {$7c} {$7c} ------------+-----/ /----- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ------------- ---+------------ {$7c} rdy {$7c} {$7c} {$7c} {$7c} {$7c} ------/ /-------- {$7c} ----+----- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ------------+-----/ /----------- ----+----- sync\\\\\\\\\\\\{$7c} {$7c} {$7c} {$7c} ------------- ------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ------------+-----/ /----------- ----+----- t0\\\\\\\\\\\\{$7c} {$7c} {$7c} {$7c} ------------- ------------- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ------------- ----- {$7c} t1\\\\\\\\\\\\{$7c} {$7c} {$7c} {$7c} ------------+-----/ /----------- ------------+----- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ------------- {$7c} ----- {$7c} t2\\\\\\\\\\\\{$7c} {$7c} {$7c} {$7c} {$7c} ------------+-----/ /----------+---- --------+----- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} ------------- {$7c} ----- {$7c} t3\\\\\\\\\\\\{$7c} {$7c} {$7c} {$7c} {$7c} ------------+-----/ /----------+-------- ----+----- {$7c} {$7c} {$7c} processor {$7c} processor {$7c}execute complete processor running {$7c} stopped {$7c} instruction {$7c} stopped {$7c} {$7c} {$7c} sINGLE iNSTRUCTION eXECUTION figure 3.4 -129- ============================================================================ 3.2 dynamic testing 3.2.1 iNTRODUCTION tHROUGH STATIC TESTING TECHNIQUES, THE DESIGNER SHOULD BE ABLE TO VERIFY THE OPERATION OF MOST OF HIS PROCESSOR INTERFACE HARDWARE, SUCH AS THE bUS eXPANDERS AND aDDRESS dECODERS (FOR SELECTING romS, ramS, ETC.). hOWEVER, THIS IS ONLY A FIRST STEP TO ASSURING PROPER SYSTEM OPERATION. mOST PERIPHERAL DEVICES CANNOT BE PROPERLY TESTED UNLESS THE PROCESSOR IS OPERATING AT FULL SPEED. tHIS NECESSITATES FULL DYNAMIC TESTING. dYNAMIC TESTING GENERALLY INVOLVES CAUSING THE PROCESSOR TO EXECUTE A PROGRAM LOOP, I.E., TO EXECUTE A REPETITIVE SEQUENCE OF INSTRUCTIONS. tHIS ALLOWS THE USE OF AN OSCILLOSCOPE IN EXAMINING THE PROCESSOR OPERA- TION. tHIS REPETITIVE OPERATION CAN BE EXTERNALLY INDUCED THROUGH THE res OR iNTERRUPT (irq OR nmi) LINES, OR IT CAN BE A PART OF THE PROGRAM BEING EXECUTED. bOTH TECHNIQUES PLAY AN IMPORTANT ROLE IN THE SYSTEM CHECKOUT PROCESS. 3.2.2 eXTERNALLY iNDUCED lOOPS tHE MOST DIRECT MEANS OF CAUSING THE PROCESSOR TO EXECUTE A LOOP IS TO DRIVE ONE OF THE DIRECT INPUTS (res, irq OR nmi) WITH A SIGNAL GEN- ERATOR. tHIS TECHNIQUE CAN BE USED TO TROUBLE-SHOOT SYSTEMS WHICH ARE ONLY PARTIALLY OPERATIONAL SINCE IT DOES NOT RELY ON PROPER EXECUTION OF A PAR- TICULAR SET OF INSTRUCTIONS TO CAUSE LOOPING TO OCCUR. hOWEVER, THIS TECH- NIQUE CAN ONLY BE USED IF AN OSCILLOSCOPE CAN BE EMPLOYED IN EXAMINING SYSTEM OPERATION. tO DO SO REQUIRES AN EFFECTIVE SCOPE-SYNCHRONIZING SIGNAL. fOR THIS REASON, THE FOLLOWING SECTION WILL DISCUSS NOT ONLY THE SIGNALS TO BE TESTED AND THE WAVEFORMS WHICH ONE SHOULD SEE BUT ALSO THE TECHNIQUES ONE MAY USE TO ASSURE GENERATION OF AN EFFECTIVE SCOPE SYNC. pROBABLY THE MOST BASIC OPERATION PERFORMED WITHIN THE PROCESSOR IS THE reset FUNCTION. wITHOUT THE reset HARDWARE AND SOFTWARE OPERATING PRO- PERLY, THE SYSTEM WILL NEVER ENTER ITS NORMAL OPERATING MODE. fOR THIS REASON, THE FIRST MAJOR FUNCTION TO BE TESTED, BOTH STATICALLY AND DYNAM- ICALLY, IS THE res INPUT. a SUGGESTED CONFIGURATION FOR DYNAMICALLY TESTING THE reset INPUT IS SHOWN IN fIGURE 3.5. iN THIS DIAGRAM, THE reset INPUT IS BEING DRIVEN FROM A SIGNAL GENERATOR. bETWEEN THE SIGNAL GENERATOR AND THE PROCESSOR IS A d- TYPE FLIP-FLOP TO SYNCHRONIZE THE CHIP RESET SIGNAL TO THE PROCESSOR CLOCKS. -130- ============================================================================ +5v o {$7c} -+- {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} -+- {$7c} --------- {$7c} {$7c} {$7c} from signal---+----+ +--- generator {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} {$7c} p2-------o{$7c}c {$7c} {$7c} {$7c} {$7c} {$7c} --------- {$7c} {$7c} ---- ----\ \ ___ from power-on------------------------) )o------ to system (res) reset ----/ / reset {$7c} ---- -- {$7c}\ {$7c} nor -++- {$7c} \ {$7c} ---o o---+ >o----- {$7c} manual {$7c} / -+- reset {$7c}/ - sUGGESTED cONFIGURATION fOR dYNAMIC rESET tESTING. figure 3.5 -131- ============================================================================ tHIS SYNCHRONIZING IS EXTREMELY IMPORTANT BECAUSE IT STABILIZES THE DATA BEING DISPLAYED ON THE OSCILLOSCOPE WITH RESPECT TO THE SCOPE SYNC. tHE MOST EFFECTIVE PROCEDURE FOR TESTING THE DYNAMIC OPERATION OF THE reset FUNCTION IS TO RESET THE SYSTEM INITIALLY AT A RATE OF APPROXI- MATELY ONE-FIFTH OF THE CLOCK RATE. tHIS WILL ALLOW THE PROCESSOR TO EXECUTE THE FIRST FEW INSTRUCTIONS IN THE RESET SEQUENCE BEFORE BEING RE- CYCLED. tHE DESIGNER CAN THEN CLOSELY EXAMINE THE TIMING OF ADDRESS, DATA AND r/w SIGNALS. uSE OF THE DELAYED SWEEP FEATURE AVAILABLE ON MOST MODERN OSCILLOSCOPES WILL ALLOW EXAMINATION OF ANY PART OF THE reset OPERATION. wHEN PROPER OPERATION OF THE reset INPUT HAS BEEN VERIFIED, THE SAME TECHNIQUE CAN BE APPLIED TO BOTH THE irq AND THE nmi INPUTS. dRIVING EITHER OF THESE INPUTS WITH A SIGNAL GENERATOR SYNCHRONIZED TO THE PROCESSOR CLOCKS WILL ALLOW A CLOSE EXAMINATION OF THE DYNAMIC OPERATION OF THE INTERRUPT POLLING SEQUENCE. tHIS PROVIDES A VERY IMPORTANT LOOK AT THE pERIPHERAL iNTERFACE SELECTION LOGIC TO ASSURE THAT ALL PERIPHERAL DEVICES ARE RESPOND- ING TO THE PROPER ADDRESS. 3.2.3 sOFTWARE lOOPS dURING SYSTEM CHECKOUT, THE DESIGNER MUST VERIFY THE OPERATION OF MANY SIMPLE FUNCTIONS WHICH MUST ALL OPERATE PROPERLY BEFORE THE ENTIRE SYS- TEM IS OPERATIONAL. tHE USE OF SIMPLE SOFTWARE LOOPS WILL ALLOW A DETAILED EXAMINATION OF ONE FUNCTION AT A TIME. mOST IMPORTANTLY, IT ALLOWS THE DESIGNER TO USE AN OSCILLOSCOPE TO EXAMINE EVENTS WHICH MAY OCCUR VERY IN- FREQUENTLY AND WHICH ARE NORMALLY VERY DIFFICULT TO SEE. tHE EXECUTION OF SOFTWARE LOOP REQUIRES THE WRITING OF A PROGRAM WHICH ENDS IN A jmp BACK TO THE BEGINNING OF THE PROGRAM. oNCE THE PROCESSOR ENTERS THE LOOP IT WILL CONTINUE TO EXECUTE THE SAME SEQUENCE OF INSTRUCTIONS UNTIL THE reset SWITCH IS PUSHED. tO UTILIZE SOFTWARE LOOPS EFFECTIVELY THERE MUST BE AN EVENT WHICH HAPPENS ONLY ONCE EACH TIME THE PROCESSOR EXECUTES THE LOOP. tHIS SIGNAL CAN BE USED TO TRIGGER THE OSCILLOSCOPE. iNCLUDING A SINGLE write OPERATION IN THE PROGRAM ALLOWS THE r/w SIGNAL TO BE USED TO TRIGGER THE SCOPE. lIKE- WISE, CAREFUL SELECTION OF ADDRESS IN THE PROGRAM WILL ALLOW USE OF AN ADDRESS LINE AS A SCOPE SYNC. fINALLY, LACKING ANYTHING ELSE, SETTING AND RESETTING A PERIPHERAL INTERFACE DEVICE OUTPUT PIN AT THE BEGINNING OF THE PROGRAM PROVIDES A VERY EFFECTIVE SYNC SIGNAL. -132- ============================================================================ 3.3 system diagnosis using hard wa re programmer aids iN ADDITION TO THE TECHNIQUES DESCRIBED IN WHICH THE USER UTILIZES OSCIL- LOSCOPES AND HIS OWN INNOVATIVE TECHNIQUES FOR ANALYZING DATA, mos tECHNOLOGY, iNC. MAKES AVAILABLE TO THE USER SEVERAL HARDWARE AIDS WHICH ASSIST IN DEBUGGING OF A MICROCOMPUTER SYSTEM AND ALSO A SOFTWARE AID CALLED THE EMULATOR. tHE HARDWARE AIDS ARE A kEYBOARD iNPUT mONITOR (kim), A tELETYPE iNPUT mONITOR (tim), AND A mICROCOMPUTER dEVELOPMENT tERMINAL (mdt) . eACH OF THESE AIDS IS DESIGNED TO ALLOW THE DEBUGGING OF MICROPROCESSOR CODE WITHOUT NEED TO RESORT TO SCOPES OR OTHER DATA TRAPPING TECHNIQUES, BUT RATHER ATTEMPTS TO REDUCE THE PROBLEM OF DEBUGGING THE CODE TO THE SAME TECHNIQUES THAT ARE AVAILABLE ON A LARGE COMPUTER SYSTEM. tHE BASIC ASSUMPTION OF EACH OF THESE DEVICES, EITHER HARDWARE OR SOFTWARE, IS THAT THE MICROPROCESSOR SYSTEM IS CONNECTED CORRECTLY, ALL THE ELECTRICAL CHARACTERISTICS HAVE ALREADY BEEN CHECKED AND MET AND THAT THE ONLY PROBLEM TO BE SOLVED IS ONE OF DEBUGGING PROGRAMS AND i/o HARDWARE WHICH HAVE BEEN ENTERED INTO THE MICROCOMPUTER. eACH OF THE HARDWARE TECHNIQUES ASSUMES THAT THE USER WILL START HIS DESIGN SEQUENCE WITH ALL OF HIS PROGRAMMING BEING DONE IN SOME FORM OF RANDOM ACCESS MEMORY WHICH IS LOADABLE FROM AN i/o DEVICE, EXAMINABLE BY THE i/o DEVICE AND CHANGEABLE BY THE i/o DEVICE. tHIS IS THE NORMAL FIRST STEP IN DEVELOPING A MICROCOMPUTER SYSTEM AND ONE THAT SHOULD BE USED PRIOR TO COMMITTING ANY OF THE HARDWARE TO promS OR ALTERABLE MEMORY. tHE ONLY EXCEPTION TO THIS IS IF THE USER IS TAKING ADVANTAGE OF THE SOFTWARE EMULATOR AND IF HIS PROGRAM IS SUCH THAT THE EMULATOR CAN GIVE HIM A SIGNIFICANT DEGREE OF CONFIDENCE IN HIS CODING IN WHICH CASE THE USE OF THE kim OR tim DEVICES IS PRIMARILY THAT OF ALLOWING HIM TO HAVE FINAL DEBUGGING ACCESS TO HIS VARIOUS MEMORY LOCATIONS. tHEREFORE, THE COMMON CHARACTERISTIC OF ALL THESE APPROACHES IS THAT BY SOME TECHNIQUE, IN THE CASE OF THE eMULATOR BY READING AN INPUT FILE, IN THE CASE OF tim BY READING IN AN INPUT TAPE FROM THE OUTPUT cROSS-aSSEMBLER, IN THE CASE OF kim LOADING A PROGRAM INTO MEMORY BY HAND, AND IN THE CASE OF mdt EITHER ASSEMBLING THE PRO- GRAM OR LOADING INPUT DATA FROM THE cROSS-aSSEMBLER, THE PROGRAM HAS BEEN ENTERED INTO A PROGRAM STORAGE. eACH OF THESE TECHNIQUES ALLOWS THE USER TO -133- ============================================================================ INITIALIZE VARIOUS MEMORY AND REGISTER LOCATIONS AND TO "START EXECUTION" OF THIS PROGRAM AT A MEMORY LOCATION. tECHNIQUES ARE IMPLEMENTED WHICH ALLOW THE USER TO STOP HIS PROGRAM AT A PARTICULAR POINT AND ANALYZE THE RESULTS OF THE OPERA- TIONS WHICH HAVE JUST BEEN COMPLETED. iF THE RESULTS ARE CORRECT, THE CODING BETWEEN THE START POINT AND THE STOP POINT IS CORRECT. iF THE CODING IS INCOR- RECT, THE USER ANALYZES THE DATA WHICH HE DISPLAYS BY USE OF THE i/o DEVICE AND THE HARDWARE OR SOFTWARE THAT INTERFACES IT, AND DETERMINES BY INSPECTION OF THE DATA AND ANALYSIS OF HIS CODING WHAT ERROR COULD CAUSE THE RESULTS DETECTED. iF THE TECHNIQUE OF JUST ANALYZING CODING IS NOT SUFFICIENT, EACH OF THESE SYSTEMS HAS THE ABILITY TO ALLOW THE USER TO GO IN AND RE-EXECUTE THE CODE WITH NEW DATA OR THE ORIGINAL DATA, ONLY STOPPING AT EARLIER STOP POINTS UNTIL HE IS ABLE TO TRAP THE OPERATION THAT CAUSES THE ERRONEOUS DATA TO OCCUR. bOTH THE EMULATOR AND mdt HAVE ADDITIONAL FEATURES WHICH ALLOW THE USER TO ANALYZE THE OPERATION OF INSTRUCTIONS AS THEY OCCUR WHICH IS VERY USEFUL IN DETERMINING WHICH PART OF THE PROGRAM CAUSES OPERATIONS TO BE PERFORMED INCORRECTLY. tHE NORMAL DESIGN CYCLE SHOULD ACTUALLY INCLUDE A COMBINATION OF TECHNIQUES. iF THE USER IS NOT USING mdt, THEN HE SHOULD WRITE HIS CODE ON A cROSS-aSSEMBLER AND DEBUG MUCH OF HIS LOOPS AND NON-i/o PROGRAMMING USING THE eMULATOR. tHE eMULATOR HAS BEEN DESIGNED TO ALLOW VERY EASY ANALYSIS OF DATA PATHS, LOOPS AND PERFORMANCE OF PROGRAM ON A NON-HARDWARE BASIS. iT IS PARTICULARLY USEFUL FOR THE USER WHO IS DEVELOPING ROUTINES WHICH HAVE SIGNIFICANT LOOP AND SUBROUTINING OR ANY COMPLETED ALGORITHM. tHE USE OF EMULATION HAS THE FOLLOWING ADVANTAGES: 1. iT GIVES THE POWER OF A LARGE MACHINE TO ALLOW TRACING OPERATIONS WHICH ARE NOT VERY FEASIBLE AT THE HARDWARE LEVEL. 2. iT MAY INDICATE PRIOR TO THE TIME THAT THE HARDWARE IS COMMITTED THAT MORE MEMORY OR MORE TIME IS REQUIRED TO PERFORM AN OPERATION WHICH MAY DRAMATICALLY CHANGE THE HARDWARE IMPLEMENTATION WHICH IS TO BE COMMITTED. iN ANY CASE, ATTEMPTING TO BRING UP THE MICROPROCESSOR SYSTEM WITHOUT USE OF ASSEMBLERS AND AN INTERFACE MODULE SUCH AS tim IS NOT THE MOST EFFICIENT USE OF THE DESIGNER'S TIME. fOR THE USER WHO IS JUST STARTING IN MICROPROCESSORS, THE kim TECHNIQUE IS ACCEPTABLE BECAUSE THE LENGTH AND COMPLEXIBILITY OF THE PROGRAMS TO BE WRITTEN SHOULD BE SHORTER AND THE USER CAN PROGRAM DIRECTLY IN hEX AND DEBUG USING THE kim EXCLUSIVELY. -134- ============================================================================ 3.3.1 kim--kEYBOARD iNPUT mONITOR kim ALLOWS THE USER TO KEY IN hEX VALUES INTO SPECIFIED MEMORY LOCA- TIONS AND TO MONITOR RESULTS. kim IS AVAILABLE TO THE SYSTEM DESIGNER IN SEVERAL FORMS. iN ITS SIMPLEST FORM, A SINGLE DEVICE OF THE mcs6530 TYPE INCLUDING 1024 BYTES OF PRE-PROGRAMMED rom MAY BE INCLUDED AS A COMPONENT IN AN EXISTING SYSTEM. tHE kim ARRAY INCLUDES A MONITOR PROGRAM WHICH PROVIDES THE FOLLOWING FEATURES: A) dATA INPUT AND OUTPUT CONTROL FROM SERIAL TELETYPEWRITERS (asr 33, sILENT 700, ETC.) B) dATA INPUT AND SYSTEM CONTROL FROM A 22-KEY KEYBOARD C) aDDRESS AND DATA DISPLAY ON A 6-DIGIT, 7-SEGMENT TYPE DISPLAY. a MICROPROCESSOR SYSTEM DESIGNED TO INCLUDE THE kim ARRAY WILL ALLOW THE DESIGNER TO PERFORM THE FOLLOWING OPERATIONS: A) tHE USER MAY SELECT KEYBOARD (kb) OR TELETYPEWRITER (tty) MODE FOR ENTRY, DISPLAY AND CONTROL. B) iF IN kb MODE, THE USER MAY ENTER ADDRESS OR DATA FIELDS FROM THE KEYBOARD. tHE USER MAY DISPLAY THE CONTENTS OF ANY ADDRESS LOCATION IN THE SYSTEM AND CAN MODIFY THE CONTENTS OF ANY ADDRESS LOCATION (OTHER THAN PRE- PROGRAMMED rom LOCATIONS). tHE STEP OPERATION (step KEY) PROVIDES A CON- VENIENT METHOD FOR DISPLAYING THE DATA CONTAINED IN SUCCESSIVE MEMORY LOCA- TIONS. pROGRAM EXECUTION MAY BE AUTHORIZED TO BEGIN FROM ANY SELECTED STARTING ADDRESS USING THE run KEY. C) iF IN THE tty MODE, THE USER MAY OBTAIN A PRINTING OF THE DATA AT ANY MEMORY LOCATION. hE CAN MODIFY THE DATA CONTAINED IN ANY MEMORY LOCA- TION. pROGRAM LISTING FROM ANY START ADDRESS TO ANY END ADDRESS MAY BE AUTHORIZED. pAPER TAPES MAY BE LOADED OR GENERATED AUTOMATICALLY. fINALLY, PROGRAM EXECUTION MAY BE INITIATED FROM ANY SELECTED STARTING ADDRESS. D) iN EITHER MODE, THE USER TERMINATES PROGRAM EXECUTION USING THE stop KEY WHICH WILL RETURN CONTROL OF THE SYSTEM TO THE kim PROGRAM. aLTERNATIVELY, A DEPRESSION OF THE rst KEY CAUSES A TOTAL RESET OF THE SYS- TEM AND A RETURN OF THE SYSTEM TO kim PROGRAM CONTROL. tHE kim ARRAY IS ALSO AVAILABLE TO THE SYSTEM DESIGNER AS A PART OF A SPECIAL DESIGN-IN SUB-SYSTEM PROVIDED IN THE FORM OF A PRINTED CIRCUIT CARD. iNCLUDED ON THIS CARD ARE THE FOLLOWING FUNCTIONAL ELEMENTS: -135- ============================================================================ A) mcs6502 MICROPROCESSOR ARRAY B) mcs6530-002 ARRAY (CONTAINING THE kim MONITOR PROGRAM) C) 22-KEY KEYBOARD AND MODE-SELECT SWITCH D) 6-DIGIT, 7-SEGMENT led DISPLAY E) 1024 x 8 ram F) MCS6530-003 ARRAY PROVIDING AN INTERVAL TIMER, 16 i/o PINS, AND 64 BYTES OF ram G) aLL INTERFACE CIRCUITS FOR OPERATION WITH SERIAL TELETYPEWRITERS. tHIS SUBSYSTEM PROVIDES THE SAINE OPERATING FEATURES DESCRIBED EARLIER BUT IS SUPPLIED AS AN OPERATING UNIT REQUIRING THE USER TO PROVIDE ONLY THE +5vOLT POWER SUPPLY IN ORDER TO COMMENCE OPERATING. aS A "STAND- ALONE" SUBSYSTEM, THE USER MAY ENTER AND DEBUG PROGRAMS OF UP TO 1024 STEPS AND CONTROL THE ACTION OF UP TO 16 i/o PINS. fOR FURHER DETAILS ON PHYSICAL AND OPERATING CHARACTERISTICS OF THE kim ARRAY AND SUBSYSTEM, THE READER IS REFERRED TO THE kim MANUAL SUPPLIED SEPARATELV. 3.3.2 tim - tELETYPE iNPUT mONITOR tim IS A PREPROGRAMMED mcs6530. tHE APPLICATION OF THE tELETYPE iNPUT mONITOR IS TO ALLOW THE USER TO INTERFACE TO AN ascii DEVICE SUCH AS A tELETYPE, crt, eXECUPORT, ETC. USING THE ascii SERIAL COMMUNICATION TECH- NIQUES TO COMMUNICATE TO AND FROM THE MICROPROCESSOR. tHIS EFFECTIVELY ALLOWS THE USER TO LOAD MEMORY FROM THE KEYBOARD OR FROM PAPER TAPE OR CASSETTE WHICH ARE ATTACHED TO HIS DEVICE. bY THE ADDITION OF A SINGLE ttl PACKAGE TO THE SYSTEM, tim CAN BE CONFIGURED SO THAT IT IS THE STARTING POINT FOR THE MICROPROCESSOR, BUT ONCE THE INITIALIZATION HAS BEEN ACCOM- PLISHED IT TRANSFERS ITSELF OUT OF THE START-UP MEMORY, CHANGES THE REST OF THE MICROPROSSESSOR MEMORY TO NORMAL CONFIGURATION AND OPERATES TRANS- PARENT TO THE MICROPROCESSOR. tHE TECHNIQUE FOR USING THE tim TO DEVELOP A MICROPROCESSOR SYSTEM IS PRIMARILY AFTER THE SYSTEM IS DETERMINED TO BE WIRED CORRECTLY BY THE TECHNIQUES ALREADY DESCRIBED. iT IS THEN USED TO DEBUG THE USER'S CODE BY MEANS OF ALLOWING THE USER TO INPUT PRE-SPECIFIED VALUES, EXECUTE PORTIONS OF THE CODE AND EXAMINE THE RESULTS. iT SHOULD BE NOTED THAT BECAUSE i/o DEVICES ARE EXTENSION OF MEMORY DEBUGGING TECHNIQUES ARE SIMPLIFIED. tHEY CAN BE CONFIGURED TO -136- ============================================================================ CONTROL i/o DEVICES TO TEST THAT LIGHTS CAN BE LIT, SWITCHES TESTED, MOTORS STARTED AND STOPPED, ETC. fOR INSTANCE, ALL OF THE CONNECTIONS TO LIGHTS AND SWITCHES CAN BE CHECKED FROM THE TELETYPE KEYBOARD BY WRITING INTO THE i/o REGISTERS THE APPROPRIATE CODE THAT TURNS ON THE LIGHTS. cORRECT OPERATION OF SWITCHES CAN BE CHECKED WITHOUT THE PROGRAM RUNNING BY PUTTING THE SWITCHES IN EITHER STATE AND READING THE i/o DEVICE RESULT INDICATED TO THE PROGRAMMER. tHIS TYPE OF CHECKING TOTALLY SHAKES OUT THE i/o CONNECTIONS TO MAKE SURE THE i/o DEVICE IS LOCATED IN THE COR- RECT MEMORY ADDRESS, DETERMINES THAT THE WIRING TO THE i/o DEVICES IS COR- RECT AND CHECKS ON THE MICROPROCESSOR BUS. a RATIONAL TECHNIQUE FOR USING EITHER tim OR kim IS TO INTERCONNECT THE DEVICE INTO THE SYSTEM TO GET THE MICROPROCESSOR TO PASS THE SINGLE- STEP START-UP SEQUENCE AND THEN TO USE THE DEBUGGING CAPABILITY OF THE tim PRIOR TO EXECUTING ANY OF THE USER'S CODE TO VERIFY THAT ALL INPUT/OUTPUT CONNECTIONS ARE CORRECT. iN CASES SUCH AS STOPPING MOTORS AND OTHER DEVICES WHICH REQUIRE TIMING, THE PROPER CONNECTION TO THE MOTORS AND OTHER DEVICES CAN BE CHECKED WITHOUT THE MOTOR ITSELF PHYSICALLY BEING CHECKED BY UNCON- NECTING LEADS, OPENING UP CONNECTORS AND VERIFYING WITH A SCOPE OR A METER THAT THE MICROPROCESSOR'S INFLUENCE AT THAT POINT IS AS WOULD BE EXPECTED ON A STATIC BASIS. tHEREFORE, THIS TECHNIQUE IS RECOMMENDED AS THE SECOND STEP OF A START-UP SEQUENCE. sIGNIFICANT DETAILS ARE GIVEN IN THE SECTION ON THE USE OF RESTART OR START SEQUENCE AND A SINGLE CYCLE OPERATION TO VERIFY THE INTERCONNEC- TION OF MOST OF THE SYSTEM. iT SHOULD BE RECALLED THAT THE INSTRUCTIONS WERE GIVEN INDEPENDENT OF THE CODING THAT WAS AVAILABLE TO THE PROGRAMMER. tHE ADVANTAGE OF USING THE tim OR kim IN THE START-UP CHECK-OUT IS THAT THERE IS KNOWN CODE WHICH IS GUARANTEED TO BE ACCURATE THAT SHOULD BE EVOKED DURING THIS START-UP SEQUENCE. bY LOOKING AT THE CODING OF THE rom AS IT APPEARS IN THE DOCUMENTATION ON THE tim OR kim, THE USER CAN USE THE KNOWN SEQUENCES FROM THE tim OR kim PROGRAM TO VERIFY THE START-UP SEQUENCE, THEREBY REMOVING ONE MORE VARIABLE. tHEREFORE, ALL INITIAL SYSTEMS CHECK- OUT SHOULD BE DONE USING tim OR kim PROGRAM FIRST IN THE START-UP SEQUENCE TO MAKE SURE THAT THE INTERCONNECTION TO tim AND TO MEMORY ARE COR- RECT. tHEN ONCE THE BASIC OPERATION OF tim HAS BEEN VERIFIED, THERE IS A KNOWN SEQUENCE THAT THE tim WILL GO THROUGH DYNAMICALLY WHICH WILL ALLOW THE USER TO VERIFY THAT THE tim IS OPERATIONAL. tHEN THE USER SHOULD -137- ============================================================================ VERIFY THE REST OF HIS MEMORY AND i/o CONNECTIONS BY USE OF WRITING AND READING IN THE MEMORY LOCATIONS USING THE DEBUGGING FEATURE OF THE tim OR kim. tHIS VERIFIES THE CONNECTION AND OPERATION OF EACH OF THE CHIPS OF THE SYSTEM AND WILL VERIFY ALL THE INTERCONNECTIONS TO ALL OUTBOARD DEVICES. nOW THE PROBLEM IS TRULY REDUCED TO MAKING SURE THAT THE PROGRAM- MER'S CODE IS CORRECT AND THE USER'S PROGRAM CAN BE LOADED BY MEANS OF EITHER THROUGH-THE-KEYBOARD OR THROUGH-THE-AUXILIARY DEVICES. tHE PROGRAM CAN BE DEBUGGED AS A PROGRAM RATHER THAN WORRYING ABOUT WHETHER OR NOT THE PROBLEM IS ONE OF HARDWARE OR SOFTWARE. bY DEFINITION OTHER THAN INCORRECT TIMING TO i/o DEVICES, THE PROBLEM HAS BEEN REDUCED TO ONE OF PROGRAMMING MISTAKES. fOR A MORE DETAILED DISCUSSION ON THE PROGRAMMING ON tim, THE USER IS REFERRED TO THE tim MANUAL SUPPLIED SEPARATELY. 3.3.3 mdt--mICROCOMPUTER dEVELOPMENT tERMINAL aLMOST ALL OF THE SECTIONS IN THIS REPORT HAD TO DO WITH HOW ONE GOES ABOUT INTERCONNECTING A SYSTEM AND DEBUGGING IT. mdt IS A PREPACKAGED SYSTEM AND, THEREFORE, SHOULD NOT HAVE THE PROBLEMS DESCRIBED ABOVE UNLESS IT IS BEING USED IN CIRCUIT EMULATION MODE. tHEREFORE, THE USER WILL PRI- MARILY BE DEBUGGING HIS PROGRAMS AND HIS BASIC INTERCONNECTION TO HIS i/o DEVICES WITH THE mdt. tHEREFORE, USE OF THE mdt REPRESENTS A SIGNIFICANTLY DIFFERENT TECHNIQUE THAN DESCRIBED IN THIS MANUAL. tHIS TECHNIQUE IS DE- SCRIBED IN THE mdt MANUAL. -138- ============================================================================ 3.4 microprocessor star tupprocedure 3.4.1 iNTRODUCTION tHIS SECTION ATTEMPTS TO TIE TOGETHER ALL OF THE TECHNIQUES PREVI- OUSLY DISCUSSED INTO ONE ORDERED PROCEDURE. tHIS PROCEDURE IS BASED ON EXPERIENCE GAINED IN BRINGING UP SYSTEMS USING PROCESSORS FROM SEVERAL DIFFERENT MANUFACTURERS. wHILE IT IS CERTAINLY TRUE THAT NO SINGLE PRO- CEDURE CAN BE EXPECTED TO CATCH ALL THE SOFTWARE AND HARDWARE ERRORS WHICH CAN EXIST IN MICROCOMPUTER SYSTEMS, IT IS HOPED THAT THIS STEP-BY-STEP APPROACH WILL ALLOW THE DESIGNER TO BRING UP HIS SYSTEM WITH AN ABSOLUTE MINIMUM OF DIFFICULTY. tHIS PROCEDURE ASSUMES THE EXISTENCE OF sINGLE cYCLE AND/OR sINGLE iNSTRUCTION LOGIC. aNY OF THE sYSTEM dEVELOPMENT TOOLS DISCUSSED IN sEC- TION 3.3 WILL ASSIST THE USER IN BRINGING UP HIS SYSTEM. tHESE DEVICES ALLOW CONVENIENT ENTRY OF TEST PROGRAMS AS WELL AS MODIFICATION OF THE SYS- TEM PROGRAM AND DATA. eACH STEP IN THE PROCEDURE INCLUDES THE FOLLOWING INFORMATION: * sECTION OF THE sYSTEM HARDWARE/SOFTWARE TO BE CHECKED. * hARDWARE, TEST EQUIPMENT, ETC. REQUIRED TO PERFORM THE TEST. * aCTION TO BE TAKEN IN IMPLEMENTING THE TEST. * eXPECTED RESULTS. * sUGGESTED PROCEDURES FOR ANALYZING FAILURE MODES. iT CANNOT BE EMPHASIZED TOO STRONGLY THAT ONE MUST UTILIZE A VERY METHODICAL, STEP-BY-STEP PROCEDURE AIMED AT SOLVING ONE PROBLEM AT A TIME WITHIN THE SYSTEM. iT IS VERY EASY FOR SEVERAL PROBLEMS TO AMPLIFY EACH OTHER TO SUCH AN EXTENT THAT NOTHING WITHIN THE SYSTEM SEEMS TO BE OPERAT- ING PROPERLY. cORRECTING PROBLEMS ONE AT A TIME WILL ULTIMATELY YIELD A COMPLETE WORKING SYSTEM WITH MINIMUM FRUSTRATION. 3.4.2 sYSTEM pOWER--sTEP 1 iT IS GENERALLY RECOMMENDED THAT FIRST PROTOTYPES OF MICROCOMPUTER SYSTEMS BE BUILT USING SOCKETS FOR THE icS (PROCESSOR, MEMORIES, ETC.). oNE DISTINCT ADVANTAGE OF THIS TECHNIQUE IS THAT IT ALLOWS THE DESIGNER TO VERIFY THAT vDD AND vSS ARE PROPERLY CONNECTED TO EACH SOCKET BEFORE THE CHIPS ARE INSERTED. tHE vDD LINE SHOULD BE WITHIN THE TOLERANCES SPECIFIED ABOUT THE 5 VOLT NOMINAL RELATIVE TO vSS. tHIS BASIC FIRST STEP CAN HELP AVOID POWER SUPPLY CONNECTIONS WHICH MAY BE FATAL TO THE CHIPS IN THE SYS- TEM. -139- ============================================================================ aFTER USING A VOLTMETER OR OSCILLOSCOPE TO CHECK POWER CONNECTIONS, INSERT THE PROCESSOR INTO ITS SOCKET AND VERIFY THAT THE ADDITIONAL CUR- RENT DRAIN IS WITHIN SPECIFICATIONS FOR THIS DEVICE. bEFORE INSERTING THE OTHER DEVICES, EXAMINE THE ADDRESS LINES, sync LINE (6502) AND THE OUTPUT CLOCKS (6502, 6503) TO MAKE SURE THAT THE PRO- CESSOR IS GENERATING SIGNALS. tHE ADDRESS LINES SHOULD BE INCREMENTING AND THE SYNC LINE SHOULD BE GENERATING REGULAR, POSITIVE GOING PULSES. tHE res LINE AND THE rdy LINE SHOULD BE HIGH (> +2.4v) FOR THIS TEST. iF THE PROCESSOR APPEARS TO BE OPERATING AND POWER CONSUMPTION IS REASONABLE, THE REST OF THE DEVICES IN THE SYSTEM CAN BE INSERTED INTO THEIR SOCKETS. 3.4.3 bASIC sYSTEM tIMING--sTEP 2 bEFORE ONE CAN EXPECT A MICROPROCESSOR SYSTEM TO FUNCTION, PROPER OPERATION OF THE BASIC SYSTEM TIMING SIGNALS (p1, p2, ETC.) MUST BE VERI- FIED. tHE MOST IMPORTANT OF THESE SIGNALS IS THE SYSTEM CLOCK. a COMMON FAULT IN mc6800 AND mcs6501 SYSTEMS IS GENERATION OF INPUT CLOCKS (p1 AND p2) WHICH ARE NOT FULL VOLTAGE OR WHICH HAVE SIGNIFICANT OVERLAP. aNOTHER VERY SERIOUS DIFFICULTY OFTEN ENCOUNTERED IS UNDERSHOOT. eACH OF THE SPECIFICATIONS LISTED IN THE DATA SHEET FOR THE SYSTEM CLOCKS MUST BE PROPERLY MET. fIGURE 3.6A ILLUSTRATES THE PROBLEMS OFTEN EN- COUNTERED IN CLOCK SIGNALS SUCH AS UNDERSHOOT AND OVERLAP. fIGURE 3.6B IS AN EXAMPLE OF mcs6501 p1 AND p2 CLOCKS AS THEY WOULD NORMALLY APPEAR IN A PROPERLY OPERATING SYSTEM. iN SYSTEMS BASED ON OTHER THAN THE mcs6501, THE CLOCKS WHICH MUST BE EXAMINED ARE THE PROCESSOR OUTPUT CLOCKS. iN THE 6502, BOTH PHASES (p1 AND p2) ARE AVAILABLE FOR DRIVING THE REST OF THE SYSTEM. iN THIS SYSTEM IT IS NECESSARY TO CHECK THE CLOCK TIMING VERY CAREFULLY TO ASSURE THAT THE TIMING OF THE CLOCK SIGNALS WITHIN THE PROCESSOR IS COMPATIBLE WITH THAT USED ON THE SUPPORT CHIPS. uSING AN OSCILLOSCOPE, COMPARE THE p1 INPUT CLOCK AND THE p2 CLOCK PRESENTED TO THE SUPPORT CHIPS TO VERIFY THAT THE DELAY DUE TO CLOCK BUF- FERING DOES NOT EXCEED THE ALLOWABLE MAXIMUM. 3.4.4 sYSTEM rESET--sTEP 3 sTATIC AND DYNAMIC ANALYSIS OF THE rESET FUNCTION CAN PROVIDE VERY DETAILED INFORMATION ON HOW THE SYSTEM IS OPERATING. iN FACT, IT IS THIS -140- ============================================================================ [ pICTURE OF oSCILLOSCOPE DISPLAY ] figure 3 6A - iMPROPER cLOCKS (nOTE UNDERSHOOT AND OVERLAP) [ pICTURE OF oSCILLOSCOPE DISPLAY ] figure 3.6B - pROPER cLOCKS mcs65o1 cLOCK tIMING sIGNALS figure 3.6 -141- ============================================================================ [ pICTURE OF oSCILLOSCOPE DISPLAY ] figure 3. 7A - pROPER aDDRESS lINES [ pICTURE OF oSCILLOSCOPE DISPLAY ] figure 3. 7B - eXCESS aDDRESS lINE lOADING aDDRESS lINES IN mcs650x sYSTEMS figure 3.7 -142- ============================================================================ [ pICTURE OF oSCILLOSCOPE DISPLAY ] [ pICTURE OF oSCILLOSCOPE DISPLAY ] tHE dATA bUS IN mcs650x sYSTEMS figure 3.8 -143- ============================================================================ STEP WHICH WILL VERIFY THE OPERATION OF MOST OF THE BASIC SYSTEM HARDWARE. tHE TOOLS REQUIRED ARE: * sINGLE cYCLE/sINGLE iNSTRUCTION lOGIC * oSCILLOSCOPE * sIGNAL GENERATOR (FOR DRIVING reset) 3.4.4.1 sTATIC aNALYSIS OF sYSTEM dETAILS dEPRESS THE halt BUTTON AND THEN THE MANUAL reset SWITCH; THEN PUSH THE SINGLE CYCLE SWITCH SIX TIMES. tHIS WILL STEP THE PROCESSOR THROUGH THE FIRST PART OF THE brk SEQUENCE AND INTO THE reset VECTOR FETCH. aT THIS TIME THE PROCESSOR SHOULD BE GENERATING fffc ON THE ADDRESS BUS AND THE rom SHOULD HAVE PUT THE LOW ORDER BYTE OF THE reset VECTOR ONTO THE DATA BUS IN RESPONSE TO THIS ADDRESS. tHIS IS AN EXCELLENT TIME TO CHECK THE FOLLOWING VERY BASIC ITEMS: a. aDDRESS lINES: uSING THE OSCILLOSCOPE, VERIFY THAT THE LOGIC LEVELS ON THE ADDRESS LINES ARE PROPER AND THAT THEY ARE REFLECTED PROPERLY THROUGH ANY BUS EXPANDERS ONTO THE MEMORY AND PERIPHERAL CHIPS. tHIS IS A VERY IMPORTANT TEST SINCE IMPROPER IMPLEMEN- TATION OF BUS EXPANDERS IS A VERY COMMON CIRCUIT FAULT. b. rom/prom CHIP SELECTS: uSING THE OSCILLOSCOPE, VERIFY THAT THE ADDRESS fffc DOES SELECT THE rom WHICH CONTAINS THE LOW ORDER BYTE OF THE reset VECTOR. c. dATA bUS: uSING THE OSCILLOSCOPE, VERIFY THAT THE VOLTAGES ON THE DATA BUS PINS OF THE PROCESSOR ARE PROPER. iT IS IMPORTANT THAT THESE SIGNALS BE ANALYZED AT THE PROCESSOR TO ASSURE PROPER OPERATION OF ANY BI-DIRECTIONAL BUS EXPANDERS IN THE SYSTEM. iN THIS TEST, THE MOST COMMON INDICATION OF IMPROPER OPERATION OF THE DATA BUS EXPANDERS IS "FLOATING" PROCESSOR DATA BUS PINS, I.E., THE PROCESSOR DATA BUS PINS ARE BEING DRIVEN NEITHER HIGH NOR LOW BECAUSE THE BUS EXPANDERS ARE IN THE OPEN-CIRCUIT CONDITION OR ARE REVERSED. -144- ============================================================================ d. mISCELLANEOUS pROCESSOR pINS: uSING THE OSCILLOSCOPE, BRIEFLY EXAMINE THE OTHER PROCESSOR PINS (r/w, irq, nmi, ETC.) TO ASSURE THAT THERE ARE NO VOLT- AGE LEVEL PROBLEMS DETECTABLE AT THIS POINT. bOTH OF THE INTERRUPT INPUTS AND THE r/w OUTPUT SHOULD BE HIGH. eXAMINE THE r/w SIGNAL ON THE INPUT TO THE MEMORY AND PERIPHERAL DEVICES. aFTER THESE INITIAL TESTS ARE COMPLETE, IT SHOULD BE POSSIBLE TO PRESS THE SINGLE STEP SWITCH ONCE MORE TO FETCH THE HIGH ORDER BYTE OF THE INTERRUPT VECTOR FROMADDRESS fffd. oN THE NEXT ACTUATION OF THE SINGLE CYCLE SWITCH, THE PROCESSOR ADDRESS BUS SHOULD CONTAIN THE reset VECTOR WHICH WAS FETCHED FROM MEMORY. aT THIS POINT, THE PROCESSOR IS READY TO EXECUTE THE SYSTEM INI- TIALIZATION ROUTINE. dURING INITIALIZATION, IT CAN BE EXPECTED THAT PRO- GRAM MEMORY WILL BE ACCESSED, PERIPHERAL REGISTERS WILL BE LOADED, AND INTERNAL PROCESSOR REGISTERS WILL BE CLEARED OR SET TO A STARTING VALUE. iT IS EXTREMELY USEFUL TO EXECUTE THIS ROUTINE ONE INSTRUCTION AT A TIME TO DETERMINE THAT EACH TIME PROGRAM MEMORY IS ACCESSED, THE PROPER INSTRUCTION IS RETURNED. hOWEVER, UNLESS A DATA TRAP IS PROVIDED, IT WILL BE MORE MEANINGFUL TO UTILIZE DYNAMIC ANALYSIS TECHNIQUES TO ANALYZE THE OPERATION OF PERIPHERAL DEVICES, SINCE MOST PERIPHERAL ACCESSES WILL BE FOR THE PUR- POSE OF WRITING EITHER THE i/o CONTROL OR THE CONTROL REGISTERS IN THE PERIPHERAL DEVICES. 3.4.4.2 dYNAMIC aNALYSIS OF sYSTEM dETAILS tHE GENERAL TECHNIQUE OF DYNAMIC ANALYSIS IS DISCUSSED IN sECTION 3.2. tHE DISCUSSION WHICH FOLLOWS WILL USE THIS TECHNIQUE TO ANALYZE MANY OF THE DETAILS OF THE SYSTEM OPERATION. sET UP THE SYSTEM AS DESCRIBED IN sECTION 3.2.2. aFTER THE TEST EQUIPMENT IS OPERATING PROPERLY, MOST OF THE SYSTEM OPERATION CAN BE VERI- FIED USING ONLY THE OSCILLOSCOPE. 3.4.4.2.1 aDDRESS bUS vERIFICATION tHE FIRST ITEM WHICH MUST BE CHECKED IS THE SPECIFIC TIMING OF THE ADDRESS LINES. tHESE LINES WILL CHANGE DURING THE FIRST PART OF p1 BUT AFTER THE SPECIFIED PERIOD, THEY SHOULD STABILIZE AND REMAIN STABLE THROUGH -145- ============================================================================ THE REST OF THE CYCLE. fIGURE 3.7A SHOWS THE WAVEFORM WHICH ONE SHOULD EX- PECT TO SEE WHILE EXAMINING p1, p2 AND TWO ADDRESS LINES. iN THIS ILLUS- TRATION, ONE ADDRESS LINE IS GOING HIGH AND THE OTHER IS GOING LOW. tHESE LINES ARE BEING GENERATED WITHIN THE PROCESSOR AND ARE GUARANTEED TO OPER- ATE PROPERLY PROVIDED THE TOTAL LOADING ON THE PINS IS WITHIN SPECIFICA- TIONS. tHE MOST COMMON CAUSE OF BOTH VOLTAGE LEVEL AND RISE TIME PROBLEMS IS OVERLOADING. vOLTAGE LEVEL PROBLEMS ARE COMMONLY EVIDENCED BY THE "ZERO" LEVEL BEING TOO HIGH, I.E., THE ADDRESS BUFFER IS BEING ASKED TO SINK TOO MUCH CURRENT. eXCESS CAPACITANCE IS USUALLY EVIDENCED BY THE RISE ATID FALL TIMES BEING TOO LONG (fIGURE 3.7B). iN EXAMINING THE ADDRESS LINES, IT IS IMPORTANT THAT THE DATA BE EXAMINED ON THE PROCESSOR AND DIRECTLY ON THE VARIOUS SUPPORT CHIPS. tHIS WILL ASSURE THAT ANY BUS EXPANDERS IN THE SYSTEM ARE OPERATING PROPERLY AND THAT THE ADDRESSES ARE VALID WHERE THEY ARE ACTUALLY BEING USED. 3.4.4.2.2 dATA bUS vERIFICATION aFTER THE ADDRESSES HAVE BEEN VERIFIED, THE NEXT STEP IS TO EX- AMINE THE DATA BUS TO VERIFY THE VALIDITY OF DATA BEING TRANSFERRED BOTH FROM THE PROCESSOR TO THE SUPPORT CHIPS AND FROM THE SUPPORT CHIPS BACK INTO THE PROCESSOR. fIGURE 3.8 ILLUSTRATES THE WAVEFORM WHICH ONE CAN EXPECT TO SEE ON THE DATA BUS LINES. iT IS VERY IMPORTANT TO NOTE THAT DURING 80 THERE IS NO WAY TO PREDICT THE VOLTAGE ON THE DATA BUS SINCE NEITHER THE PROCES- SOR NOR THE SUPPORT CHIPS ARE DRIVING THESE LINES. hOWEVER, DURING p1 THE DATA BUS PINS SHOULD GO EITHER HIGH OR LOW. iT IS ONLY DURING p2 (HIGH) THAT THE VALIDITY OF THE DATA CAN BE VERIFIED. tHREE VERY IMPORTANT PARAMETERS MUST BE CONSIDERED WHEN EXAMIN- ING THE DATA BUS. tHESE ARE THE VOLTAGE LEVELS, THE TIME AT WHICH THE DATA IS VALID AND THE DELAY FROM THE TRAILING EDGE OF p2 TO DATA BECOMING IN- VALID. a. vOLTAGE lEVELS: tHE LOGIC LEVELS ON THE PROCESSOR DATA BUS MUST ALWAYS BE GREATER THAN 2.4 VOLTS FOR A LOGIC 1 AND LESS THAN 0.4 VOLTS FOR A LOGIC 0. tHIS IS A VERY BASIC CONCEPT BUT A QUICK CHECK ON THESE LEVELS VERY EARLY IN THE CHECKOUT PROCEDURE CAN HELP THE DESIGNER AVOID HOURS OF ATTEMPTING TO MAKE A -146- ============================================================================ SYSTEM OPERATE WITH SIGNALS WHICH ARE ACTUALLY MARGINAL BUT WHICH ON THE SURFACE APPEAR TO BE SATISFACTORY. aNOTHER VERY IMPORTANT ITEM TO CHECK IS WHETHER OR NOT THE LOGIC "0" VOLTAGE IS ACTUALLY GOING NEGATIVE (BELOW gnd). iT IS VERY IMPORTANT THAT THE LOGIC SIGNALS GOING INTO ALL THE CHIP INPUTS NOT BE ALLOWED TO GO BELOW -0.3 VOLTS AS INDICATED IN THE SPECIFICATIONS. b. dATA vALID tIME: tHE TIME AT WHICH DATA BECOMES VALID INDICATES THE TOTAL TIME WHICH THE PROCESSOR OR MEMORY HAS AVAILABLE TO STABIL- IZE THE GATES AND LATCHES USED TO TRAP THE DATA WITHIN THE CHIP. fOR THIS REASON THE DATA MUST NOT TAKE TOO LONG TO REACH EITHER A VALID HIGH "1" OR A VALID LOW "0." tHE PRI- MARY CAUSE OF SLOW SIGNALS ON THE DATA BUS IS EXCESSIVE LOADING, EITHER RESISTIVE OR CAPACITIVE. cAREFULLY CHECK THE DEVICES WHICH ARE ATTACHED TO THE BUS TO MAKE SURE THAT THE TOTAL LOADING IS WITHIN SPECIFICATIONS. c. hOLD tIME: tHE LAST IMPORTANT CONSIDERATION, "HOLD TIME," IS DEFINED AS THE TIME BETWEEN THE TRAILING EDGE OF THE p2 PULSE AND THE POINT AT WHICH DATA IS NO LONGER VALID. a MINIMUM OF 10 NSEC HOLD TIME IS REQUIRED FOR THE PROCESSOR TO TRAP THE DATA INTO ITS INTERNAL INPUT LATCHES. tHE PROCESSOR INTER- NAL p2 PULSE IS USED TO GATE THE CONTENTS OF THE DATA BUS INTO THESE LATCHES. hOLD TIME IS ALSO REQUIRED BY THE VARI- OUS SUPPORT CHIPS WITHIN THE SYSTEM. cAREFULLY CHECK THE SIGNALS AS THEY APPEAR ON THE ramS, romS, ETC. TO VERIFY THAT EACH IS BEING OPERATED IN ACCORDANCE WITH ITS SPECIFI- CATION. -147- ============================================================================ 3.4.5 dETAILED cOMPONENT cHECK aFTER THE DYNAMIC CHECK OF THE RESET ROUTINE, THE NEXT STEP IS TO ATTEMPT TO RUN THE SYSTEM PROGRAM. tHE SUCCESS OF THIS OPERATION WILL DETERMINE WHETHER OR NOT A FURTHER DETAILED COMPONENT CHECK IS NECESSARY. iT IS IMPORTANT TO NOTE THAT THE CHECKOUT OF THE SYSTEM PROGRAM SHOULD PROCEED ONE STEP AT A TIME IN MUCH THE SAME MANNER AS WE HAVE APPROACHED THE HARDWARE CHECKOUT. iF A CAREFUL EXAMINATION HAS BEEN MADE OF ALL OF THE DEVICES, DATA PATHS, ETC. IN THE SYSTEM, THE SOFTWARE CHECKOUT CAN PROCEED UNDER THE ASSUMPTION THAT THE HARDWARE IS FULLY OPERATIONAL. hOW- EVER, IT IS INEVITABLE THAT DOUBTS WILL ARISE. tHERE ARE TIMES IN THE SOFTWARE CHECKOUT PROCESS THAT THE PROGRAM WILL APPEAR TO BE INCORRECT; DATA WON'T BE GOING INTO MEMORY AS IT SHOULD OR, IN GENERAL, SOME HARDWARE FAILURE WILL BE INDICATED. aS SOON AS THIS HAPPENS, THE SUSPECTED COM- PONENTS SHOULD BE EXAMINED IN DETAIL. iN KEEPING WITH THE POLICY OF "ONE STEP OR ONE PROBLEM AT A TIME," IT IS IMPORTANT THAT POTENTIAL HARDWARE PROBLEMS NOT BE ALLOWED TO INVALIDATE THE EFFORT BEING PUT INTO THE SOFT- WARE CHECKOUT. cOMPONENT PROBLEMS CAN BE ONE OF TWO TYPES: COMPONENT FAILURE, I.E., A PART NOT OPERATING PER SPECIFICATIONS; OR SYSTEM FAILURE, I.E., A PART BEING USED WRONG IN THE SYSTEM. tHE LATTER PROBLEM CAN BE A RESULT OF INCORRECT SYSTEM DESIGN OR INCORRECT WIRING. tHE PROBLEM OF FUNCTIONAL COMPONENTS NOT OPERATING PROPERLY IN THE SYSTEM IS THE ONE WHICH WILL BE ADDRESSED HERE. iN FACT, IF THERE IS ANY DOUBT ABOUT A COMPONENT BEING FUNCTIONAL, IT SHOULD BE REPLACED IMMEDIATELY UPON VERIFICATION OF PROPER SIGNALS TO ALL INPUTS. iF IT STILL DOES NOT OPERATE PROPERLY, THE PROBLEM IS MOST LIKELY SYSTEM RELATED. tHE DETAILED COMPONENT CHECK IS PERFORMED MOST EFFECTIVELY BY LOAD- ING A SMALL LOOPING PROGRAM INTO THE SYSTEM ram. fOR THIS REASON, THE tim OR kim DEBUG SOFTWARE (SEE tim AND kim mANUALS) CAN BE OF SIGNIFICANT VALUE IN THIS PROCESS. tHE PROCEDURE INVOLVES STATIC AND DYNAMIC OPERATION OF A SMALL TEST PROGRAM WHICH EXERCISES EACH OF THE COMPONENTS IN THE SYS- TEM. tHE GOAL OF THIS STEP SHOULD BE A COMPLETE VERIFICATION THAT ALL CHIP SELECTS ARE OPERATING PROPERLY, THAT ALL DATA ADDRESS LINES ARE OPERATING PROPERLY AND THAT THE SUPPORT CHIPS ARE DRIVING THE PROCESSOR PROPERLY. -148- ============================================================================ tHE SUGGESTED PROCEDURE FOR CHECKOUT OF EACH TYPE OF COMPONENT IS DISCUSSED SEPARATELY BELOW. a. romS (proms): tHE MOST STRAIGHTFORWARD COMPONENT IN ANY MICROPROCESSOR SYSTEM IS THE rom. tHIS DEVICE SIMPLY PUTS OUT AN 8-BIT WORD ONTO THE DATA BUS IN RESPONSE TO AN ADDRESS. dIFFICULTY WITH roms IS USUALLY CAUSED BY IMPROPER CHIP SELECTS OR BY MIS-APPLICATION OF DEVICES WHICH ARE NOT PART OF THE mcs6500 FAMILY. fOR THIS REASON, STATIC TESTING OF romS IS USUALLY A VERY EFFECTIVE FIRST STEP. tHIS REQUIRES ENTERING A TEST PROGRAM INTO ram AND EXE- CUTING THIS PROGRAM USING THE SINGLE CYCLE SWITCH. tHE PROGRAM ITSELF SHOULD SIMPLY PERFORM A read (FOR EXAMPLE, AN lda OR ldx INSTRUCTION) OF A SELECTED WORD FOR EACH rom CHIP TO BE TESTED. tHE CHIP SELECTS CAN THEN BE EXAMINED AND AT THE SAME TIME, THE ADDRESS LINES PRESENTED TO THE CHIPS CAN BE EXAMINED ALONG WITH THE DATA PUT ON THE DATA BUS. aFTER THE CHIP SELECT, ADDRESS BUS AND DATA BUS HAVE BEEN VERIFIED STATICALLY, IT MAY BE NECESSARY TO EXECUTE THE SAME TEST PROGRAM DYNAMICALLY TO ASSURE THAT ALL CHIPS IN THE SYSTEM ARE OPERATING AT SYSTEM SPEED. aT THIS POINT, IT MAY BE NECES- SARY TO INCLUDE A write OPERATION (sta, stx, sty, ETC.) IN THE LOOP TO PROVIDE A SYNC SIGNAL. aNALYSIS OF THE DYNAMIC OPERATION OF THE romS SHOULD INVOLVE FIRST LOOKING AT EACH ADDRESS AND DATA BUS LINES DIRECTLY ON THE PROCESSOR CHIP. iT IS HERE THAT THE ADDRESS IS BEING GENERATED, AND IT IS HERE THAT THE DATA MUST MEET A SPEED SPECIFICATION. iF DATA IS NOT VALID AT THE PROPER TIME, THE NEXT STEP IS TO DETERMINE WHERE EXCESSIVE DELAY HAS BEEN INTRODUCED INTO THE DATA PATH FROM ADDRESS OUTPUT, THROUGH THE rom AND BACK TO THE PROCESSOR DATA BUS. kEEP IN MIND THAT IT IS THIS ENTIRE PATH WHICH MUST OPERATE AT SPEED TO ASSURE PROPER PROCESSOR OPERA- TION. iN FACT, IF THE DELAYS ARE EXCESSIVE, IT MAY BE NECESSARY TO SLOW DOWN THE SYSTEM CLOCK RATE TO ALLOW THE PROGRAM DATA TO REACH THE PROCESSOR IN TIME. aN ALTERNATIVE SOLUTION TO THIS PROBLEM IS THE IMPLEMENTATION OF THE rdy SIGNAL TO HOLD THE PRO- -149- ============================================================================ CESSOR FOR ONE CYCLE EACH TIME IT FETCHES DATA OR PROGRAM FROM THE roms. aLTHOUGH THE PROBLEMS DISCUSSED ABOVE MAY BE ENCOUNTERED AT THIS POINT, IT IS MUCH MORE LIKELY THAT A WIRING ERROR WILL CAUSE A SINGLE ADDRESS OR DATA LINE TO BE EXCESSIVELY LOADED SO THAT IT OPERATES SLOW OR NOT AT ALL. tHIS PROBLEM CAN USUALLY BE DETECTED AND FIXED QUITE EASILY BY LOOKING AT EACH COMPONENT IN THE DATA PATH. b. ramS: oPERATION OF THE ramS IN A MICROPROCESSOR SYSTEM CAN BE CHECKED IN MUCH THE SAME MANNER AS THE romS. eXECUTION OF A TEST LOOP PROGRAM BOTH STATICALLY AND DYNAMICALLY FOR EACH CHIP IN THE SYSTEM SHOULD BE SUFFICIENT TO VERIFY PROPER OPERATION OF THE ramS IN THE SYSTEM. fOR EACH ram, BOTH A write AND A read OPER- ATION SHOULD BE INCLUDED IN THE TEST LOOP. tHIS WILL ALLOW CHECKOUT OF DATA TRANSFERS IN BOTH DIRECTIONS. dURING SINGLE CYCLE EXECUTION OF THE TEST LOOP, THE PROCES- SOR WILL STOP ONLY IN THE ram READ OPERATIONS. hOWEVER, THIS WILL ALLOW A STATIC CHECK OF THE CHIP SELECT LOGIC AND THE ADDRESS AND DATA LINES. rUNNING THE PROGRAM DYNAMICALLY WILL ALLOW VERIFICATION THAT THE DATA AND ADDRESS SIGNALS PRESENTED TO THE ramS DURING THE write OPERATION ARE WITHIN SPECIFICA- TION FOR THE ram BEING USED IN THE SYSTEM AND THAT THE TOTAL DELAYS THROUGH THE ADDRESS, ram, AND DATA BUS PATH ARE WITHIN SPECIFICATIONS FOR THE PROCESSOR DURING THE read OPERATIONS. aS WITH THE romS, THE MOST LIKELY PROBLEM TO BE ENCOUNTERED AT THIS POINT IS WIRING ERRORS WHICH CAUSE A SPECIFIC DEVICE TO OPERATE IMPROPERLY. a CAREFUL CHECK OF EACH PIN WILL ALLOW DETECTION OF THIS TYPE OF PROBLEM. c. piaS: tHE PERIPHERAL INTERFACE DEVICES (6520, 6530, ETC.) CAN ALL BE CHECKED OUT IN THE MANNER DESCRIBED ABOVE. hOWEVER, SINCE THESE CHIPS DO MANY DIFFERENT OPERATIONS, THE TEST PROGRAM MUST BE MUCH MORE COMPLEX THAN THAT REQUIRED FOR THE rom AND ram. -150- ============================================================================ hOWEVER, IT CAN USUALLY BE LIMITED TO TESTING ONLY THOSE FUNC- TIONS WHICH ARE USED IN THE SYSTEM. a LARGE PART OF THE OPERATION OF THE PERIPHERAL INTERFACE DEVICES CAN BE VERIFIED BY DOING A write FOLLOWED BY A read FOR EACH REGISTER ON THE CHIP. tHIS WILL ALLOW A COMPLETE CHECKOUT OF THE DATA PATHS BETWEEN THE PROCESSOR AND THE CHIPS AS WELL AS A CHECKOUT OF ALL THE CHIP SELECT FUNCTIONS. hOWEVER, A MORE COMPLETE ANALYSIS MAY BE REQUIRED TO VERIFY THAT DATA IS APPEAR- ING PROPERLY ON THE OUTPUT PINS OF THE PERIPHERAL CHIP AND THAT DATA ON THE INPUTS IS BEING REFLECTED PROPERLY BACK INTO THE PROCESSOR. tHIS WILL INVOLVE DISCONNECTING THE PERIPHERAL SUB- SYSTEM WHICH THE PROCESSOR IS ATTEMPTING TO DRIVE AND MANUALLY PUTTING DATA INTO THE INPUTS. a SEPARATE TEST CAN VERIFY THE VALIDITY OF OUTPUT DATA. aFTER THE SYSTEM HARDWARE HAS BEEN EXAMINED IN THE DETAIL DISCUSSED ABOVE, THE DESIGNER WILL HAVE DEVELOPED CONFIDENCE THAT HIS SYSTEM CAN OPERATE PROPERLY ONCE THE SYSTEM PROGRAM IS COMPLETELY DEBUGGED. vERIFICATION OF THE SYSTEM PRO- GRAM SHOULD PROCEED WITH A SECTION-BY-SECTION CHECKOUT AS DISCUSSED ABOVE. eACH SUBROUTINE, INTERRUPT ROUTINE, ETC. SHOULD BE EXAMINED SEPARATELY. tHEY CAN THEN BE COMBINED TO FORM THE MAJOR PERIPHERAL OPERATING ROUTINES, ARITHMETIC ROUTINES, ETC. THAT MAKE UP THE SYSTEM. tHE FINAL RESULT SHOULD BE A FUNCTION- ING PROGRAM WHICH HAS BEEN EXAMINED IN ALL ITS DETAILS RUNNING ON A SYSTEM WHICH IS FULLY OPERATIONAL. -151- ============================================================================ appendix a summary of single cycle execution tHIS SECTION CONTAINS AN OUTLINE OF THE DATA ON BOTH THE ADDRESS BUS AND THE DATA BUS FOR EACH CYCLE OF THE VARIOUS PROCESSOR INSTRUCTIONS. iT TELLS THE SYSTEM DESIGNER EXACTLY WHAT TO EXPECT WHILE SINGLE CYCLING THROUGH A PROGRAM. nOTE THAT THE PROCESSOR WILL NOT STOP IN ANY CYCLE WHERE r/w IS A 0 (WRITE CYCLE). iNSTEAD, IT WILL GO RIGHT INTO THE NEXT READ CYCLE AND STOP THERE. fOR THIS REASON, SOME INSTRUCTIONS MAY APPEAR TO BE SHORTER THAN INDICATED HERE. aLL INSTRUCTIONS BEGIN WITH t0 AND THE FETCH OF THE op code AND CONTINUE THROUGH THE REQUIRED NUMBER OF CYCLES UNTIL THE NEXT t0 AND THE FETCH OF THE NEXT op code. wHILE THE BASIC TERMINOLOGY USED IN THIS APPENDIX IS DISCUSSED IN THE pRO- GRAMMING mANUAL, IT HAS BEEN DEFINED BELOW FOR EASE OF REFERENCE WHILE STUDYING sINGLE cYCLE eXECUTION. op code--tHE FIRST BYTE OF THE INSTRUCTION CONTAINING THE OPERATOR AND MODE OF ADDRESS. operand--tHE DATA ON WHICH THE OPERATION SPECIFIED IN THE op code IS PERFORMED. base address--tHE ADDRESS IN iNDEXED ADDRESSING MODES WHICH SPECIFIES THE LOCA- TION IN MEMORY TO WHICH INDEXING IS REFERENCED. tHE HIGH ORDER OF BYTE OF THE BASE ADDRESS (ab08 TO ab15) IS bah (bASE aDDRESS hIGH) AND THE LOW ORDER BYTE OF THE BASE ADDRESS (ab00 TO ab07) IS bal (bASE aDDRESS lOW). effective address--tHE DESTINATION IN MEMORY IN WHICH DATA IS TO BE FOUND. tHE EFFECTIVE ADDRESS MAY BE LOADED DIRECTLY AS IN THE CASE OF pAGE zERO AND aBSOLUTE aDDRESSING OR MAY BE CALCULATED AS IN iNDEXING OPERATIONS. tHE HIGH ORDER BYTE OF THE EFFECTIVE ADDRESS (ab08 TO ab15) IS adh AND THE LOW ORDER BYTE OF THE EFFECTIVE ADDRESS (ab00 TO ab07) IS adl. indirect address--tHE ADDRESS FOUND IN THE OPERAND OF INSTRUCTIONS UTILIZING (iNDIRECT),y WHICH CONTAINS THE LOW ORDER BYTE OF THE BASE ADDRESS. iah AND ial REPRESENT THE HIGH AND LOW ORDER BYTES. jump address--tHE VALUE TO BE LOADED INTO pROGRAM cOUNTER AS A RESULT OF A jUMP INSTRUCTION. a-1 ============================================================================ a. 1. single byte instructions asl dex nop tax tya clc dey rol tay cld inx sec tsx cli iny sed txa clv lsr sei txs tHESE SINGLE BYTE INSTRUCTIONS REQUIRE TWO CYCLES TO EXECUTE. dURING THE SECOND CYCLE THE ADDRESS OF THE NEXT INSTRUCTION IN PROGRAM SEQUENCE WILL BE PLACED ON THE ADDRESS BUS. hOWEVER, THE op code WHICH APPEARS ON THE DATA BUS DURING THE SECOND CYCLE WILL BE IGNORED. tHIS SAME INSTRUCTION WILL BE FETCHED ON THE FOLLOWING CYCLE AT WHICH TIME IT WILL BE DECODED AND EXECUTED. tHE asl, rol AND lsr INSTRUCTIONS APPLY TO THE ACCUMULATOR MODE OF ADDRESS. tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 op code 1 (dISCARDED) t0 pc + 1 op code 1 nEXT iNSTRUCTION a. 2. internal execution on memory data adc cmp bor ldy and cpx lda ora bit cpy ldx sbc tHE INSTRUCTIONS LISTED ABOVE WILL EXECUTE BY PERFORMING OPERATIONS IN- SIDE THE MICROPROCESSOR USING DATA FETCHED FROM THE EFFECTIVE ADDRESS. tHIS TOTAL OPERATION REQUIRES THREE STEPS. tHE FIRST STEP (ONE CYCLE) IS THE op code FETCH. tHE SECOND (ZERO TO FOUR CYCLES) IS THE CALCULATION OF AN EFFECTIVE ADDRESS. tHE FINAL STEP IS THE FETCHING OF THE DATA FROM THE EFFECTIVE ADDRESS. eXECUTION OF THE INSTRUCTION TAKES PLACE DURING THE FETCHING AND DECODING OF THE NEXT INSTRUCTION. PAG ============================================================================ a. 2.1. iMMEDIATE aDDRESSIN0 (2 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 dATA 1 fETCH dATA t0 pc + 2 op code 1 nEXT iNSTRUCTION a. 2.2. zERO pAGE aDDRESSIN0 (3 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 adl 1 fETCH eFFECTIVE aDDRESS t2 00, adl dATA 1 fETCH dATA t0 pc + 2 op code 1 nEXT iNSTRUCTION a. 2.3. aBSOLUTE aDDRESSING (4 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 adl 1 fETCH LOW ORDER eFFECTIVE aDDRESS BYTE t2 pc + 2 adh 1 fETCH HIGH ORDER eFFECTIVE aDDRESS BYTE t3 adh, adl dATA 1 fETCH dATA t0 pc + 3 op code 1 nEXT iNSTRUCTION a. 2.4. iNDIRECT, x aDDRESSING (6 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 ba1 1 fETCH pAGE zERO bASE aDDRESS t2 00, bal dATA 1 (dISCARDED) t3 00, bal + x adl 1 fETCH LOW ORDER BYTE OF eFFECTIVE aDDRESS t4 00, bal + adh 1 fETCH HIGH ORDER BYTE OF x + l eFFECTIVE aDDRESS t5 adh, adl dATA 1 fETCH dATA t0 pc + 2 op code 1 nEXT iNSTRUCTION a-3 ============================================================================ a. 2.5. aBSOLUTE, x OR aBSOLUTE, y aDDRESSING (4 OR 5 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 bal 1 fETCH LOW ORDER BYTE OF bASE aDDRESS t2 pc + 2 bah 1 fETCH HIGH ORDER BYTE OF bASE aDDRESS t3 adl: bal + dATA* 1 fETCH DATA (NO PAGE CROSS- INDEX REGISTER ING) adh: bah + c cARRY IS 0 OR 1 AS RE QUIRED FROM PREVIOUS ADD OPERATION t4* adl: bal + dATA 1 fETCH DATA FROM NEXT PAGE INDEX REGISTER adh: bah + 1 t0 pc + 3 op code 1 nEXT iNSTRUCTION *iF THE PAGE BOUNDARY IS CROSSED IN THE INDEXING OPERATION, THE DATA FETCHED IN t3 IS IGNORED. iF PAGE BOUNDARY IS NOT CROSSED, THE t4 CYCLE IS BYPASSED. a. 2.6. zERO pAGE, x OR zERO pAGE, y aDDRESSING mODES (4 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 bal 1 fETCH pAGE zERO bASE aDDRESS t2 00, bal dATA 1 (dISCARDED) t3 00, bal + dATA 1 fETCH dATA (NO PAGE CROSS INDEX ING) REGISTER t0 pc + 2 op code 1 nEXT iNSTRUCTION a-4 ============================================================================ a. 2.7. iNDIRECT, y aDDRESSING hODE (5 OR 6 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code tI pc + 1 ial 1 fETCH pAGE zERO iNDIRECT aDDRESS t2 00, ial bal 1 fETCH LOW ORDER BYTE OF bASE aDDRESS t3 00, ial + 1 bah 1 fETCH HIGH ORDER BYTE OF bASE aDDRESS t4 adl: bal + y dATA* 1 fETCH dATA FROM SAME PAGE adh: bah + c cARRY IS 0 OR 1 AS RE QUIRED FROM PREVIOUS ADD OPERATION t5* adl: bal + y dATA 1 fETCH dATA FROM NEXT PAGE adh: bah + 1 t0 pc + 2 op code 1 nEXT iNSTRUCTION *iF PAGE BOUNDARY IS CROSSED IN INDEXING OPERATION, THE DATA FETCH IN t4 IS IGNORED. iF PAGE BOUNDARY IS NOT CROSSED, THE t5 CYCLE IS BY- PASSED. a. 3. st0re operations sta stx sty tHE SPECIFIC STEPS TAKEN IN THE sTORE oPERATIONS ARE VERY SIMILAR TO THOSE TAKEN IN THE PREVIOUS GROUP (iNTERNAL EXECUTION ON MEMORY DATA). hOWEVER, IN THE sTORE oPERATION, THE FETCH OF DATA IS REPLACED BY A write (r/w = 0) CYCLE. nO OVERLAPPING OCCURS AND NO SHORTENING OF THE INSTRUCTION TIME OCCURS ON INDEXING OPERATIONS. a. 3.1. zERO pAGE aDDRESSING (3 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code tI pc + 1 adl 1 fETCH zERO pAGE eFFECTIVE aDDRESS t2 00, adl dATA 0 wRITE INTERNAL REGISTER TO MEMORY t0 pc + 2 op code 1 nEXT iNSTRUCTION a-5 ============================================================================ a. 3.2. aBSOLUTE aDDRESSING (4 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 adl 1 fETCH LOW ORDER BYTE OF eFFECTIVE a0DRESS t2 pc + 2 adh 1 fETCH HIGH ORDER BYTE OF eFFECTIVE aDDRESS t3 adh, adl dATA 0 wRITE INTERNAL REGISTER TO MEMORY t0 pc + 3 op code 1 nEXT iNSTRUCTION a. 3.3. iNDIRECT, x aDDRESSING (6 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 bal 1 fETCH pAGE zERO bASE aDDRESS t2 00, bal dATA 1 (dISCARDED) t3 00, bal + x adl 1 fETCH LOW ORDER BYTE OF eFFECTIVE aDDRESS t4 00, bal + adh 1 fETCH HIGH ORDER BYTE OF x + 1 eFFECTIVE aDDRESS t5 adh, aLL dATA 0 wRITE INTERNAL REGISTER TO MEMORY t0 pc + 2 op code 1 nEXT iNSTRUCTION a. 3.4. aBSOLUTE, x OR aBSOLUTE, y aDDRESSING (5 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 bal 1 fETCH LOW ORDER BYTE OF bASE aDDRESS t2 pc + 2 bah 1 fETCH HIGH ORDER BYTE OF bASE aDDRESS t3 adl: bal + dATA 1 INDEX (dISCARDED) REGISTER adh: bah + c t4 adh, adl dATA 0 wRITE INTERNAL REGISTER TO MEMORY t0 pc + 3 op code 1 nEXT iNSTRUCTION a-6 ============================================================================ a. 3.5. zERO pAGE, x OR zERO pAGE, y aDDRESSING mODES (4 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code tI pc + 1 bal 1 fETCH pAGE zERO bASE aDDRESS t2 00, bal dATA 1 (dISCARDED) t3 adl: bal + dATA 0 wRITE INTERNAL REGISTER INDEX TO MEMORY REGISTER t0 pc + 2 op code 1 nEXT iNSTRUCTION a. 3.6. iNDIRECT, y aDDRESSING mODE (6 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code tI pc + 1 ial 1 fETCH pAGE zERO iNDIRECT aDDRESS t2 00, ial bal 1 fETCH LOW ORDER BYTE OF bASE aDDRESS t3 00, ial + 1 bah 1 fETCH HIGH ORDER BYTE OF bASE aDDRESS t4 adl: bal + y dATA 1 (dISCARDED) adh: bah 15 alh, adi dATA 0 wRITE iNTERNAL rEGISTER TO MEMORY t0 pc + 2 op code 1 nEXT iNSTRUCTION a. 4. read--modify--write operations asl lsr dec rol inc ror tHE rEAD--mODIFY--wRITE OPERATIONS INVOLVE THE LOADING OF OPERANDS FROM THE OPERAND ADDRESS, MODIFICATION OF THE OPERAND AND THE RESULTING MODI- FIED DATA BEING STORED IN THE ORIGINAL LOCATION. nOTE: tHE ror INSTRUCTION WILL BE AVAILABLE ON mcs650x MICROPROCESSORS AFTER jUNE, 1976. a-7 ============================================================================ a. 4.1. zERO pAGE aDDRESSING (5 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 aLL 1 fETCH pAGE zERO eFFECTIVE aDDRESS t2 00, adl dATA 1 fETCH dATA t3 00, adl dATA 0 t4 00, adl mODIFIED 0 wRITE MODIFIED dATA BACK dATA TO MEMORY t0 pc + 2 op code 1 nEXT iNSTRUCTION a. 4.2. aBSOLUTE aDDRESSING (6 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code tI pc + 1 adl 1 fETCH LOW ORDER BYTE OF eFFECTIVE aDDRESS t2 pc + 2 adh 1 fETCH HIGH ORDER BYTE OF eFFECTIVE aDDRESS t3 adh, adl dATA 1 t4 adh, adl dATA 0 t5 adh, adl mODIFIED 0 wRITE MODIFIED dATA BACK dATA INTO MEMORY pc + 3 op code 1 nEXT iNSTRUCTION a. 4.3. zERO pAGE, x aDDRESSING (6 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 bal 1 fETCH pAGE zERO bASE aDDRESS t2 00, bal dATA 1 (dISCARDED t3 adl: bal + x dATA 1 fETCH dATA (WITHOUT CARRY) t4 adl: bal + x dATA 0 (WITHOUT CARRY) t5 adl: bal + x mODIFIED 0 wRITE MODIFIED dATA BACK (WITHOUT dATA INTO MEMORY CARRY) t0 pc + 2 op code 1 nEXT iNSTRUCTION a-8 ============================================================================ a. 4.4. aBSOLUTE, x aDDRESSING (7 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 bal 1 fETCH LOW ORDER BYTE OF bASE aDDRESS t2 pc + 2 bah 1 fETCH HIGH ORDER BYTE OF bASE aDDRESS t3 adl: bal + x dATA 1 (dISCARDED) adh: bah + c t4 adl: bal + x dATA 1 fETCH dATA adh: bah + c t5 adh, adl dATA 0 t6 alh, adl mODIFIED 0 wRITE MODIFIED dATA BACK dATA INTO MEMORY t0 pc + 3 op code 1 nEW iNSTRUCTION a. 5. miscellaneous operations bcc brk php bcs bvc pla beq bvs plp bmi jmp rti bne jsr rts bpl pha a. 5.1. pUSH oPERATION--php, pha (3 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 op code 1 (dISCARDED) t2 sTACK pOINTER* dATA 0 wRITE iNTERNAL rEGISTER INTO sTACK t0 pc + 1 op code 1 nEXT iNSTRUCTION *sUBSEQUENTLY REFERRED TO AS "sTACK pTR." a-9 ============================================================================ a. 5.2. pULL oPERATIONS--plp, pla (4 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 op code 1 (dISCARDED) t2 sTACK pTR. dATA 1 (dISCARDED) t3 sTACK pTR. + 1 dATA 1 fETCH dATA FROM sTACK t0 pc + 1 op code 1 nEXT iNSTRUCTION a. 5.3. jUMP TO sUBROUTINE--jsr (6 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 adl 1 fETCH LOW ORDER BYTE OF sUBROUTINE aDDRESS t2 sTACK pTR. dATA 1 (dISCARDED) t3 sTACK pTR. pch 0 pUSH HIGH ORDER BYTE OF PROGRAM COUNTER TO sTACK t4 sTACK pTR. - 1 pcl 0 pUSH LOW ORDER BYTE OF PROGRAM COUNTER TO sTACK t5 pc + 2 adh 1 fETCH HIGH ORDER BYTE OF sUBROUTINE aDDRESS t0 sUBROUTINE op code 1 nEXT iNSTRUCTION aDDRESS (adh, adl) a-10 ============================================================================ a. 5.4. bREAK oPERATION--(hARDWARE iNTERRUPT)-brk (7 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH erk op code (OR FORCE brk) t1 pc + 1 dATA 1 (pc ON HARD- (dISCARDED) WARE INTER RUPT) t2 sTACK pTR. pch 0 pUSH HIGH ORDER BYTE OF PROGRAM COUNTER TO sTACK t3 sTACK pTR. - 1 pcl 0 pUSH LOW ORDER BYTE OF PROGRAM COUNTER TO sTACK t4 sTACK pTR. - 2 p 0 pUSH sTATUS rEGISTER TO sTACK t5 fffe adi 1 fETCH LOW ORDER BYTE OF (nmi-fffa) INTERRUPT VECTOR (res-fffc) t6 ffff adh 1 fETCH HIGH ORDER BYTE OF (nni-fffb) INTERRUPT VECTOR (res-fffd) t0 iNTERRUPT vEC- op code 1 nEXT iNSTRUCTION TOR (adh, adl) a. 5.5. rETURN FROM iNTERRUPT-rti (6 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 dATA 1 (dISCARDED) t2 sTACK pTR. dATA 1 (dISCARDED) t3 sTACK pTR. + 1 dATA 1 pULL p FROM sTACK t4 sTACK pTR. + 2 dATA 1 pULL pcl FROM sTACK t5 sTACK pTR. + 3 dATA 1 pULL pch FROM sTACK t0 pch, pcl op code 1 nEXT iNSTRUCTION a-11 ============================================================================ a. 5.6. jUMP oPERATION--jmp a.5.6.L. aBSOLUTE aDDRESSING mODE (3 YC0CLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 adl 1 fETCH LOW ORDER BYTE OF jUMP aDDRESS t2 pc + 2 adh 1 fETCH HIGH ORDER BYTE OF jUMP aDDRESS t0 adh, adl op code 1 nEXT iNSTRUCTION a.5.6.2. iNDIRECT aDDRESSIN0 mO0DE0(5 YC0LES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 ial 1 fETCH LOW ORDER BYTE OF iNDIRECT aDDRESS t2 pc + 2 iah 1 fETCH HIGH ORDER BYTE OF iNDIRECT aDDRESS t3 iah, ial adl 1 fETCH LOW ORDER BYTE OF jUMP aDDRESS t4 iah, ial + 1 adh 1 fETCH HIGH ORDER BYTE OF jUMP aDDRESS t0 adh, adl op code 1 nEXT iNSTRUCTION a. 5.7. rETURN FROM sUBROUTINE--rts (6 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code t1 pc + 1 dATA 1 (dISCARDED) t2 sTACK pTR. dATA 1 (dISCARDED) t3 sTACK pTR. + 1 pcl 1 pULL pcl FROM sTACK t4 sTACK pTR. + 2 pch 1 pULL pch FROM sTACK t5 pch, pcl (FROM dATA 1 sTACK) (dISCARDED) t0 pch, pcl + 1 op code 1 nEXT iNSTRUCTION a-12 ============================================================================ a. 5.8. bRANCH oPERATION--bcc, bcs9 beq, bmi, bne, bpl, bvc9 bvs (2, 3, OR 4 CYCLES) tN aDDRESS bUS dATA bUS r/w cOMMENTS t0 pc op code 1 fETCH op code tI pc + 1 oFFSET 1 fETCH bRANCH oFFSET t2* pc + 2 + op code 1 oFFSET aDDED TO pROGRAM OFFSET (W/O cOUNTER CARRY) t3** pc + 2 + op code 1 cARRY aDDED OFFSET (WITH CARRY) *sKIP IF BRANCH NOT TAKEN **sKIP IF BRANCH NOT TAKEN; SKIP IF BRANCH OPERATION DOESN T CROSS PAGE BOUNDARY a-13 ============================================================================