home
***
CD-ROM
|
disk
|
FTP
|
other
***
search
/
CP/M
/
CPM_CDROM.iso
/
mbug
/
mbug184.arc
/
ROS34.LBR
/
ROS.CZK
/
ROS.CLK
Wrap
Text File
|
1979-12-31
|
3KB
|
93 lines
{ ROS.CLK - Remote Operating System Clock Routines }
{ File: QX-10.CLK
Description: This driver set is designed to support the Epson QX-10 internal
clock. Two routines are provided to perform BCD to binary and
binary to BCD conversion.
Date: 8/3/85
Author: Mick Gaitor
Credits: Kevin Karns and Steve Fox
Description: Comment update.
Date: 9/7/85
Author: Steve Fox
}
function BCD_to_Bin(BCD : Byte): byte;
{ Convert packed BCD value to binary }
begin
BCD_to_Bin := (10 * (BCD div 16)) + (BCD mod 16)
end; {BCD_to_Bin}
function Bin_to_BCD(Bin : byte): byte;
{ Convert binary value to packed BCD }
begin
Bin_to_BCD := (16 * (Bin div 10)) + (Bin mod 10)
end; {Bin_to_BCD}
procedure GetTAD(var t: tad_array);
{ Return a 6 element integer array of the current system time in
seconds, minutes, hours, day, month, and year.
This routine is based on a BASIC routine in THE EPSON QX-10
USER'S GUIDE by James Hansen (1984 - Scott, Foresman & Co.). [MAG]
}
const
ClkAddr = $3D;
ClkData = $3C;
var
ClkRegs : array[0..9] of byte;
ndx : integer;
begin
repeat
{ read all registers into a holding array for ease of access }
for ndx := 0 to 9 do
begin
port[ClkAddr] := ndx; { write RAM addr to clock port }
ClkRegs[ndx] := port[ClkData]{ read register data }
end;
{ check seconds data }
port[ClkAddr] := 0; { write secs addr to clock port }
until port[ClkData] = ClkRegs[0]; { make sure time hasn't changed }
{ return time and date to calling routine }
t[0] := BCD_to_Bin(ClkRegs[0]); { secs }
t[1] := BCD_to_Bin(ClkRegs[2]); { mins }
t[2] := BCD_to_Bin(ClkRegs[4]); { hrs }
t[3] := BCD_to_Bin(ClkRegs[7]); { day }
t[4] := BCD_to_Bin(ClkRegs[8]); { mo }
t[5] := BCD_to_Bin(ClkRegs[9]); { yr }
end;
procedure SetTAD(var t: tad_array);
{ Set the system time using a 6 element byte array which contains
seconds, minutes, hours, day, month, and year.
(Same credit for clock access routine as GetTAD [MAG])
}
const
ClkAddr = $3D;
ClkData = $3C;
var
ClkRegs : array[0..9] of integer;
ndx : integer;
begin
{ read all registers into a holding array for ease of access }
for ndx := 0 to 9 do
begin
port[ClkAddr] := ndx; { write RAM addr to clk port }
ClkRegs[ndx] := port[ClkData] { read register data }
end;
{ place new time and date in holding array slots }
ClkRegs[0] := Bin_to_BCD(t[0]); { secs }
ClkRegs[2] := Bin_to_BCD(t[1]); { mins }
ClkRegs[4] := Bin_to_BCD(t[2]); { hrs }
ClkRegs[7] := Bin_to_BCD(t[3]); { day }
ClkRegs[8] := Bin_to_BCD(t[4]); { mo }
ClkRegs[9] := Bin_to_BCD(t[5]); { yr }
{ write holding array back to clock port }
for ndx := 0 to 9 do
begin
port[ClkAddr] := ndx; { write RAM addr to clock port }
port[ClkData] := ClkRegs[ndx] { write register data }
end
end;