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**** HOW TO PUT 2Meg AGNUS INTO A2000 + 2M/1M enhancements **** (FULL) Hi ! Many people asked me for a 2Meg Agnus hack repost... As I cannot E-mail my articles directly, I post BOTH OF THEM again here. Part ONE deals with "simply" putting a new 2M Agnus into A2000s. Part TWO deals with some enhancements to the original project, such as using again the original on-board 1M as slowFAST RAM, or saving 1M of CHIP by re-using these 1M. If you're interested in one part only, just "search" the words "PART ONE" or "PART TWO" in the text below. They're only once. DON'T FORGET THAT I HAVE ==NOT== MY AMIGA HERE IN JAPAN, SO THAT THESE HACKS HAVEN'T BEEN TESTED YET. NOR I CAN SUPPLY YOU WITH ANY SCHEMATICS OR PCB ! Ready ? Set, Go ! ----PART ONE : how to put 2M Agnus into A2000---- Hello folks, I'm back ! After having posted here again my article about 2Meg AGNUS inside A2000, I found I was a lazy boy to not have SERIOUSLY thought about it yet. I finally achieved the artwork this morning. This has NOT been tested on my own A2000, because it has now a looong rest in France... I'd really like to, but as I can't, please feel free to TRY it by yourself if you're brave enough to face the difficulties (personally, I would NEVER hesitate...). This hack is made for the people who have an A2000-B, 0.5M/1M Agnus and would like to become members of the 2M CHIP circle. It will require lots of time, checkings and CARE, of course. May anybody from C= read this, and correct me if required... THANKS ! !!! NOTES !!! ** When I say "xx M Agnus", it means that this Agnus has the ability ** to address xx M of CHIP RAM. For example, 0.5M Agnus (8370/8371) can ** address 0.5M of CHIP RAM only, but also 0.5M of "FAST" RAM at #C00000. ** I will talk about the 2M CHIP Agnus release for A2000 and A3000 : ref 8372B. ** It is DIFFERENT from the release for A500+, ref 8375, because the A500+ ** has its memory splitted between on-board chips (1M) and A501+ (1M), so ** that /RAS0 and /RAS1 still EXIST. ** The followings may not apply to A500(+) because of this, but A500+ owners ** have already access to 2M CHIP (A500+ + A501+) !! Lucky they are !! ** The schematics I'll give you are the ones for A2000-B rev 2 with 0.5M Agnus. ** These are the ONLY ones I own at this time. ** But I've been able to check the ones of new A500+. ** For A2000-B with 1M Agnus, I will tell you IF some things differ. ** Revs. 2 thru 4.2 of A2000-B should not be too different, ** but I'd like you to CHECK the differences before trying anything !!! ** Rev 6 of A2000-B doesn't differ on memory parts, so that's also O.K. !!! 1> Jumpers and RAM configurations for Gary and Agnus ---------------------------------------------------- Hereafter, I will name the addresses by their first 2 digits only : example, #C0 means #C00000..C0FFFF. These two digits are A23..A20 (1st) and A19..A16 (2nd). The other "forgotten" ones are A15..A0 (4 digits). ------------------------ Note about CHIP/FAST RAM ------------------------ RAM at location #00..1F is called "CHIP" because all custom chips and 68000 have access to it. Due to this shared access, this memory is a little bit slower than "other" memory. RAM at location above #20 and at #C0..C7 is called "FAST" because only 68000 has access to it. No DMA is possible here. In fact, RAM at #C0..C7 is UNPROPERLY called "FAST" because it is still managed by Agnus, so that this is still a "SLOW" memory. The correct term should be "SLOW/FAST" memory, but I'll still employ "FAST", to distinguish between "CHIP" and "not CHIP" memory, even if the term employed is not really accurate... ----------- The jumpers ----------- Two jumpers are directly connected to Gary and Agnus : - J101 : selects A19 or A23 as "A19" input for Agnus - J500 : if in, tells Gary that some "fast" RAM is here at #C0..C7 Gary receives as inputs A17..A23 from 68000 bus. Then it is able to decode both #00..1F and #C0..C7 address locations, which correspond respectively to the first 2Mb of CHIP and the 0.5Mb of "FAST" RAM. If J500 is in, Gary assumes that there is effectively some RAM in #C0..C7, and will, later on, assert /RAMEN to tell Agnus to manage some RAM at these locations. If J500 is out, Gary assumes there is no memory at #C0..C7, so that it will not assert /RAMEN later on at these locations, and will assert /RAMEN only at #00..1F for CHIP RAM. Agnus then ignores locations #C0..C7. If J101 is on pins 1-2, A23 from 68000 bus is connected to A19 of Agnus. This position is called "normal" on A2000 (old) schematics, because on these old ones, the configuration 512k CHIP (#00..07) and 512k FAST (#C0..C7) is still assumed. These RAM are respectively managed by /RAS0 and /RAS1 of Agnus. The bank selection is made upon A19 input : /RAS0 is asserted when A19=0 and /RAS1 is asserted when A19=1 (of course, not permanently, only during RAM accesses !). This gives two banks of RAM. Agnus receives A1..A18 from 68000 bus, but doesn't decode addresses by itself. It's the the role of the Gary signal /RAMEN, which acts like a /CS_RAM signal, to tell Agnus to manage RAM or not. Further on, Agnus should be aware of the 512k CHIP at #00 and also of the 512k FAST at #C0. As Agnus cannot decode addresses, A23 will be connected to Agnus "A19" to make sure that the 1st bank of CHIP will be selected when /RAMEN=0 and A23=0 (=#00..1F) and the 2nd bank of FAST when /RAMEN=0 and A23=1 (=#C0..C7). If J101 is at pins 2-3 (called "special" position), A19 from 68000 bus is now connected to Agnus "A19" input, so that the 2nd bank of RAM (/RAS1) is selected when A19=1, NOT when A23=1. The new memory map is now : 1st bank CHIP (/RAS0) at #00..07 and 2nd bank CHIP (/RAS1) at #08..0F. According to the previous arguments, you can now set up this chart : configuration | J101 | J500 | comments ----------------|-----------|-----------|------------------------------------- 512k CHIP+ 512k FAST 1-2 in The 1st bank will be at #00..07 The 2nd bank will be at #C0..C7 To be used with 0.5Mb Agnus ------------------------------------------------------------------------------ 1Mb CHIP+ no fast 2-3 out The 1st bank will be at #00..07 The 2nd bank will be at #08..0F To be used with 1Mb Agnus ------------------------------------------------------------------------------ 512k CHIP 1-2 out The 1st bank will be at #00..07 Gary assumes there is nothing at #C0 Works but only 512k...not so useful! ------------------------------------------------------------------------------ 512k CHIP, bad memory map 2-3 in The 1st bank will be at #00..07 but Gary assumes the 2nd at #C0..C7 while Agnus decodes it at #08..0F !! *** STOP, YOU MISLEAD YOUR AMIGA *** ------------------------------------------------------------------------------- So that if you upgrade from 0.5M Agnus to 1M Agnus, pull J500 out and move J101 to pins 2-3 : that's all ! And also, if you want to "backgrade" from 1M Agnus to 0.5M Agnus, put J500 in and move J101 to pins 1-2... could be useful when, for example, you burnt your 1M Agnus and your local supplier has only 0.5M spare Agnus to give you while ordering for new 1M ones, so that you can still use your Amiga with 512k CHIP + 512k FAST (it happened to me one year ago... I had to use it !). For owners of 0.5M Agnus : an easy way to "disconnect" FAST memory (with games or else) is to put a switch in place of J500. With switch "ON", you have 512k CHIP + 512k FAST. With switch "OFF", you have only 512k CHIP. But remember to move the switch during Reset ONLY, not while working... 2> The new 2M CHIP version of Agnus ----------------------------------- Somebody previously posted this here in this newsgroup : >The pinout of the 8372b (the 2MB agnus) is the same of the 8370/8371 agnus, >which you can find in the A500/A2000 manuals, except for 3 pin: >The RAS0 is now RAS alone, the RAS1 is now MA9 (the tenth bit of the >multiplexed address for DRAM), the XCLK (external clock) is now A20 (the >20th address bit of 68000 address bus). >NOTE: the external clock enable is now kept high by a pullup, so (and for the >lack of XCLK), using the 8372b, you cannot clock the system externally. This >may be the reason because the NewTek Video Toaster doesn't work on the A3000. >-- > red@alessia.dei.unipd.it It means that the new 2M CHIP Agnus : - now has an only /RAS line instead of former /RAS0 and /RAS1 - now supplies the RAMs with a new multiplexed address line : MA9 (to have access to full 2Mb instead of 0.5Mb with MA0...MA8 only) - now has no possibility to be "genlocked" thru XCLK (this should be made externally with a FAST multiplexer) Only one RAS line is now available : /RAS. It means that only one 16-bit bank of RAM is managed by /RAS from Agnus. Such a bank could be made of 16 chips of 1Mx1 RAM : they are splitted into 2 groups of 8, providing 2 banks of 8 bits accessed by /CASL and /CASU from Agnus (/CASL and /CASU are still here). You may also use 4 chips of 1Mx4 RAM, and split them into 2 groups of 2 chips (the PCB is smaller and easier to design, and it should suck less power). But, due to the new MA9 line, RAM multiplexed address bus is now 10 bits wide : 256k RAM cannot be used anymore (9 bits wide), unless you design some "hack" to use them. Another annoying feature is that you cannot "genlock" your Amiga with an external signal connected to XCLK of video port. You should now do this EXTERNALLY, using a FAST (due to frequencies involved) multiplexer whose inputs are connected to internal 28M and external XCLK, while input select is achieved by XCLKEN. The output is then connected to Agnus "28M" input, and to all the other chips that make use of the system clock. You may or may not wish to do this little hack too, depending on the genlock board you have or not (I don't have some, so NOW I don't care for it). 3> What do you have to change to use a 2M Agnus ? ------------------------------------------------- The 10 bits wide address bus for RAM will force you to use some 1Mx.. RAM, unles you'd like to design a (little more complex) "glue" to switch (lots of) 256kx... RAM chips. Remember now that the on-board RAM chips will be out of use with your 2M Agnus ! But I'll provide you with a hack with which you'll still be able to use half of them. Please follow my next article ! Some pins have changed, so you'll have to "cut" (safely !) your main board to connect these pins to new places. 4> Pins to cut/ to remove ------------------------- Agnus pin # | old name | new name | what to do on Agnus socket ? --------|-----------|-----------|---------------------------------------------- 57 RAS0 RAS still goes to RAMs, no change required ------------------------------------------------------------------------------- 56 RAS1 MA9 still goes to RAMs, but signal is different no change required BTW ------------------------------------------------------------------------------- 35 XCLK A20 the track from video port should be cut, then pin 35 should be connected to 68000 bus ------------------------------------------------------------------------------- 36 XCLKEN XCLKEN the name and function didn't change, but it'd be better to prevent ANY assertion that may mislead Agnus, so cut the track ! ------------------------------------------------------------------------------- In details : - pin 57 is still a /RAS signal which goes to RAM banks : as former /RAS0 selected the 1st RAM bank, you should now cut this signal to prevent any conflict between the RAM you'll had and the one on board. 74F244 (U541) --- former /RAS0 |\ 22 ohms (RP502) | (not used now) Agnus pin 57 ---------| >----^-^-^-^----+-- cut here --+-- 1st bank /RAS 8 |/ 12 3 4 | | | --^-^-^-^-|+5 here you have now /RAS duly buffered----^ pull-up 470 ohms Existing parts : - 74F244 (U541) - RP502 (quad resistor pack) You'll have to cut : - between RP502 and RAM themselves You'll have to add : - a resistor 470 ohms, 1/2W after the cut - pin 56 takes now part of the multiplexed address bus of RAM banks : as former /RAS1 selected the 2nd RAM bank, you should now cut this signal to prevent any conflict between the RAM you'll had and the one on board. 74F244 (U541) --- former /RAS1 |\ 22 ohms (RP502) | (not used now) Agnus pin 56 ---------| >----^-^-^-^----+-- cut here --+-- 2nd bank /RAS 13 |/ 7 9 10 | | | --^-^-^-^-|+5 here you have now MA9 duly buffered-----^ pull-up 470 ohms Look at the previous hack for the 1st bank, it's same, except for pin numbers ! - pin 35 : the XCLK track from video port should be cut, then pin 35 should be connected to 68000 address bus, pin 48 (A20). XCLK from video ----------- cut here -+----------------- Agnus pin 35 | ------------------ 68000 pin 48 - pin 36 : XCLKEN should be tied to +5v thru a pull-up. Fortunately, this pull-up still exists on the main board (RP109, 4.7k, pins 1 & 2). So first, look for it and cut the XCLKEN track from video port BEFORE this resistor. XCLKEN from video ----------- cut here -+----------------- Agnus pin 36 | --^-^-^-^--- pull-up is here ! That should be all for cutting operations. The next step will be soldering only !... but more complicated. 5> The new RAM to use ---------------------- Now your A2000-B is motified to accept without problems the new 2M Agnus. BUT the major problem is now about RAM themselves : 256kx.. cannot be used anymore ! You'll have to build your own memory board wht 1Mx.. RAM chips to fit the new requirements of 2M Agnus ! As I am a lucky boy, a friend of mine gave me a full hand of ZIP 1Mx1 RAM (32 chips !!!), given that "some of them are burnt and he didn't want to waste his time to check all of them, so that he bought a new set of RAM" !! Some guys like to waste their money... but it was a chance for me ! After testings, I have now all the 16 required chips for the memory board. You can also use four 1Mx4 chips, but maybe more expensive or less easy to find. But you can !!! The connections to 2M Agnus are now straight-forward, VERY easy, with NO additional "glue" (i.e. gates). This was the old configuration with 0.5M Agnus : ------------------------------- /CASL----------------------------------*---| /CAS = /CASL 1/2 Bank 0 | | | bits 0..7 | /RAS0-----*----------------------------^---| /RAS = /RAS0 8x256kx1 | | | ------------------------------- | | | | ------------------------------- /CASU-----^-----------------*----------^---| /CAS = /CASU 1/2 Bank 0 | | | | | bits 8..15 | ------------------^----------^---| /RAS = /RAS0 8x256kx1 | | | ------------------------------- | | | | ------------------------------- | ----| /CAS = /CASL 1/2 Bank 1 | | | bits 0..7 | /RAS1----------*------------^--------------| /RAS = /RAS1 8x256kx1 | | | ------------------------------- | | | | ------------------------------- | ---------------| /CAS = /CASU 1/2 Bank 1 | | | bits 8..15 | ----------------------------| /RAS = /RAS1 8x256kx1 | ------------------------------- This was the old configuration with 1M Agnus since A2000-B rev 6 : (everything is same except RAM chips, now 256kx4 type) ------------------------------- /CASL----------------------------------*---| /CAS = /CASL 1/2 Bank 0 | | | bits 0..7 | /RAS0-----*----------------------------^---| /RAS = /RAS0 2x256kx4 | | | ------------------------------- | | | | ------------------------------- /CASU-----^-----------------*----------^---| /CAS = /CASU 1/2 Bank 0 | | | | | bits 8..15 | ------------------^----------^---| /RAS = /RAS0 2x256kx4 | | | ------------------------------- | | | | ------------------------------- | ----| /CAS = /CASL 1/2 Bank 1 | | | bits 0..7 | /RAS1----------*------------^--------------| /RAS = /RAS1 2x256kx4 | | | ------------------------------- | | | | ------------------------------- | ---------------| /CAS = /CASU 1/2 Bank 1 | | | bits 8..15 | ----------------------------| /RAS = /RAS1 2x256kx4 | ------------------------------- This will be the new configuration with 2M Agnus and 1Mx1 RAM : ------------------------------- /CASL--------------------------------------| /CAS = /CASL 1/2 Bank | | bits 0..7 | /RAS -----*--------------------------------| /RAS = /RAS0 8x1Mx1 | | ------------------------------- | | ------------------------------- /CASU-----^--------------------------------| /CAS = /CASU 1/2 Bank | | | bits 8..15 | ---------------------------------| /RAS = /RAS0 8x1Mx1 | ------------------------------- And finally this will be the new configuration with 2M Agnus and 1Mx4 RAM : ------------------------------- /CASL--------------------------------------| /CAS = /CASL 1/2 Bank | | bits 0..7 | /RAS -----*--------------------------------| /RAS = /RAS0 2x1Mx4 | | ------------------------------- | | ------------------------------- /CASU-----^--------------------------------| /CAS = /CASU 1/2 Bank | | | bits 8..15 | ---------------------------------| /RAS = /RAS0 2x1Mx4 | ------------------------------- 6> How to design your board : ----------------------------- Since no extra gate is required, building it should be really easy. Most of pins are connected straight-forward from one chip to another. Note that 1Mx1 RAM chips have separate DIN/DOUT pins. To use them hereafter, these pins should be connected to each other on your board. Here is the diagram using 1Mx1 RAM chips (a double bar means one chip) : -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- || || || || || || || || || || || || || || || || MA0..MA8----------||-||-||-||-||-||-||-||----------||-||-||-||-||-||-||-|| /WE1--------------||-||-||-||-||-||-||-|| /WE2---||-||-||-||-||-||-||-|| || || || || || || || || || || || || || || || || 4> MA9------------||-||-||-||-||-||-||-||----------||-||-||-||-||-||-||-|| 4> /RAS-----------||-||-||-||-||-||-||-||----------||-||-||-||-||-||-||-|| || || || || || || || || || || || || || || || || /CASL-------------||-||-||-||-||-||-||-|| /CASU--||-||-||-||-||-||-||-|| || || || || || || || || || || || || || || || || -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D0..15------------0 1 2 3 4 5 6 7-----------8 9 10 11 12 13 14 15 Here is the diagram using 1Mx4 RAM chips (a vertical bar means one chip) : -- -- -- -- || || || || MA0..MA8----------||----||-----------||-----|| /WE1--------------||----|| /WE2---||-----|| || || || || 4> MA9------------||----|| ----------||-----|| 4> /RAS-----------||----||-----------||-----|| || || || || /CASL-------------||----|| /CASU--||-----|| || || || || -- --- -- -- D0..15------------0123 4567---------891011 12131415 On A2000 with 256kx1 chips : You'll find... MA0 at pin 5 of U501..532 MA1 at pin 7 MA2 at pin 6 MA3 at pin 12 MA4 at pin 11 MA5 at pin 10 MA6 at pin 13 MA7 at pin 9 MA8 at pin 1 MA9 after the 22 ohms resistor of chapter. 4> /RAS after the 22 ohms resistor of chapter. 4> /CASL at pin 15 of U501..508 and U517..524 /CASU at pin 15 of U509..516 and U525..532 /WE1 at pin 3 of U501..516 /WE2 at pin 3 of U517..532 D0 at pins 2/14 of U501 and U517 D1 at pins 2/14 of U502 and U518 D2 at pins 2/14 of U503 and U519 D3 at pins 2/14 of U504 and U520 D4 at pins 2/14 of U505 and U521 D5 at pins 2/14 of U506 and U522 D6 at pins 2/14 of U507 and U523 D7 at pins 2/14 of U508 and U524 D8 at pins 2/14 of U509 and U525 D9 at pins 2/14 of U510 and U526 D10 at pins 2/14 of U511 and U527 D11 at pins 2/14 of U512 and U528 D12 at pins 2/14 of U513 and U529 D13 at pins 2/14 of U514 and U530 D14 at pins 2/14 of U515 and U531 D15 at pins 2/14 of U516 and U532 +5V at pin 8 of U501..532 <= put a 0.22 uf decoupling GND at pin 16 of U501..532 <= capacitor for EACH chip ! A2000-B with 1M Agnus and 256kx4 RAM chips have different pinouts. Search by yourself !! I used separate /WE for lower/upper bits to avoid overloading a single line with too many chips, and since this line is already doubly buffered on board. This makes a lot of pins to connect ! But since the same pin can be found at different locations on the board, you can conect them the way you want. BUT don't use excessively long wires... too much noise may occur on buses ! May I give you a trick : to fix your board and make connections easier, try to use wire-wrapping IC sockets and sold their legs DIRECTLY to older RAM chips. That way, your board will be fasten to the main PCB AND you will easily pick up the signals on the sockets themselves, not on the PCB (of course, don't use one socket per RAM chip !!!). May your Amiga bless you... he (sorry, SHE) has 2M CHIP now !!! Good luck. Tell me more about your own works... P-chan. --- ----PART TWO : how to put 2M Agnus into A2000 ++++ MORE RAM !!!---- Can you remember my first article ? I promised you a continuation. HERE IT IS !!! ### All of this couldn't have been done without the help of ### Dave Haynie (from CBM) and many other people on net, ### who replied to my questions gracefully. Thanks, guys ! This addendum to my previous hack will give you the possibility : - either to add 1Meg of FAST ram at $C0 address, USING the EXISTING 1 MEG RAM originally on the main board, - or to save 1Meg by using this original on-board 1Meg RAM (no need for extra 2Meg, 1Meg is enough to have 2Meg of CHIP) I assume that you have read my previous article. I will try here to give you the most accurate informations as possible, but since I cannot try it on my own A2000, I cannot help you to put it inside your computer. The article is made of 4 chapters (all in one post) : - the 1st will deal with problems to face when trying to add more RAM to on-board one - the 2nd one will explain you how to use the internal 1Meg AND an extra external 1Meg to provide 2Meg CHIP, assuming that you didn't make the 2Meg hack yet - the 3rd one will explain you how to use the internal 1Meg again as "slowFAST" RAM, assuming that you already made the 2Meg hack - the 4th one (rather short) will explain you how to generate the main clock multiplexer for 28M and XCLK clocks, in order to be able to use some genlock again, since the new 2Meg Agnus does not do this internally any more For each part, I will explain the theory, then the realization. >>> I SUGGEST YOU TO READ ALL CHAPTERS, EVEN IF SOME OF THEM MAY >>> BE OF NO INTEREST TO YOU AT FIRST For anything related to my previous article, please read it again ! I will not repeat all of it, just the required points. Ready ? Set... Go ! 1> How Agnuses manage internal RAM; how to add extra RAM ======================================================= 1.1> Agnus 0.5Mb and 1Mb ------------------------ Agnuses 0.5Mb and 1Mb CHIP manage the RAM the same way. They provide : - /CASL for CAS of the lower 8 bits 7...0 - /CASU for CAS of the upper 8 bits 15...9 - /RAS0 for RAS of the lower 512Ko (bank 0) - /RAS1 for RAS of the upper 512Ko (bank 1) - MA0..MA8 for multiplexed address bus (256k wide) The only difference comes from the address where bank 1 is assumed. For Agnus 0.5M CHIP (8370/8371 releases), since only 0.5M CHIP RAM is available for CPU, custom chips, etc..., the 2nd bank of 512Ko (bank 1) is mapped at $C0, using address bit A23 to switch between bank 0 ($00) and bank 1 ($C0). Gary is aware of this, and selects Agnus at $C0 addresses too. This gives you 512Ko CHIP at $00..07 and 512Ko "pseudoFAST" at $C0..C7. For Agnus 1M CHIP (8372A), the 2nd bank of 512Ko now follows the 1st one, at $08. This gives you 512Ko CHIP at $00..07 and 512Ko CHIP at $08..0F, for a total of 1M CHIP at $00..0F. Internal jumpers should be set like this : J101 J500 ------------------------------------- 0.5M Agnus 1-2 IN A23 is used to select /RAS0 or /RAS1 There is EXTENDED RAM at $C0 1M Agnus 2-3 OUT A19 is used to select /RAS0 or /RAS1 There is no RAM at $C0 RAMs to be used should be 256k model, since address bus for RAMs is 9 bits wide. 1.2> Agnus 2Mb -------------- This newest release (8372B) now manages RAM a different way. It provides : - /CASL and /CASU again (same functions) - an unique /RAS for all RAM - an address bus MA0..MA9 of 10 bits (1M wide) One unique bank of 1Mb is now used, with 1Mx1 chips (16) or 1Mx4 (4). The jumpers are in the same configuration as for 1M Agnus. A19 and A20 are now multiplexed to give the last MA9 address line. 1.3> Major differencies, and problems to solve ---------------------------------------------- [1] The new address bus is now 10 bits wide, for 1M parts, instead of 9 [2] There is now only one /RAS signal for all chips [3] How to perform refresh cycles now ? Let's study each of them separately... 1.3.1> Bus is 10 bits wide -------------------------- The old address bits multiplexing chart for 0.5M/1M agnus was : Multiplexed Bit MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 Address Bit for ROWS A9 A10 A11 A12 A13 A14 A15 A16 A17 Address Bit for COLS A1 A2 A3 A4 A5 A6 A7 A8 A18 There is no A0, because the 68000 uses /UDS and /LDS instead. These /UDS and /LDS will generate /CASU and /CASL. The "A19" input, COMING FROM JUMPER J101 !!!, was used to switch between /RAS0 (A19=0) and /RAS1 (A19=1). The new Agnus 2Meg now has a new MA9 bit. The chart is now : Multiplexed Bit MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 Address Bit for ROWS A9 A10 A11 A12 A13 A14 A15 A16 A17 A19 Address Bit for COLS A1 A2 A3 A4 A5 A6 A7 A8 A18 A20 You can notice that the former one is STILL valid, for compatibility. But the old 256k RAMS used with 0,5M/1M Agnuses had a 9 bits wide bus only. If we want to use these 256k chips again, the new hack will have to manage the signals some way to handle both 9 and 10 bits wide buses. 1-3-2> Only one /RAS -------------------- Old Agnuses used two banks of 512Kb with two /RAS0,/RAS1 signals. They were forced to do this because 256K chips were to be bundled into 16 bits wide data bus to match 68000 requirements. To be given a total of 512Kb, two banks of 256Kb, i.e. 128K x 16 bits, were to be used. 68000 could see a total of 256K x 16 bits. Now, new 2M Agnus has one /RAS signal, because new chips are 1Mx1 (or x4) wide, so that a few number of them would be necessary to be given a 16 bits wide data bus. To be given a total of 1Mb, one bank of 1Mb, i.e. 512K x 16 bits, is used. Since old RAMs used two separate /RAS signals, the new hack will have to generate these two /RAS again. These chips couldn't be splitted any more into two banks of 16 bits. 1-3-3> Refresh cycles --------------------- All Agnuses perform RAS-only refresh cycles. It means that, during refresh cycle, all RAS signals are asserted and transmitted to RAMs. It also means that the new hack will have to do it the same way. It finally means that the RAM bank switching should <<<NOT>>> be made with /RAS signals, since all of them <<MUST>> be asserted during refresh. The only other possible solution is to play with /CASU and /CASL to switch between different RAM banks. 1-4> How to mix 9 bits wide and 10 bits wide buses -------------------------------------------------- You have noticed in 1-3-2 that the first 9 bits of 2M Agnus and the full 9 bits of 0.5M/1M Agnuses are EXACTLY SAME. It will be VERY USEFUL. If things had been changed inside 2M Agnus address multiplexers, maybe the hack WOULD NOT HAVE BEEN POSSIBLE ! Let's read further on. "Old" 256k chips used MA0..MA8. "New" 1M chips use MA0..MA8 + MA9. Since MA0..MA8 are COMMON to both models, and are assigned to the SAME ADDRESS BITS, we can simply mix them on the same bus. MA9 will be simply not used on 256k chips (left unconnected). But old chips use two /RAS signals, while new ones use only one /RAS. AND ALL /RAS SIGNALS SHOULD BE ASSERTED DURING REFRESH CYCLES !! Sigh... there is no way to switch between banks with /RAS signals. This would have been VERY easy to do. Well, forget it ! The only signals we can use are now /CASU and /CASL. Can you imagine the solution ?... - ALL /RAS signals will be connected to each other : that way, refresh cycles could be done on EVERY RAM bank, with no problem - /CASU and /CASL will be selected or not for each bank, upon the accessed address : * if A23=0 : addresses $00..1F are assumed --> 2Meg CHIP is to be r/w --> /CASU and /CASL for 2Meg CHIP will be asserted ONLY --> all other /CASL and /CASU will be left at "1" (not selected) * if A23=1 : addresses over $C0 are assumed --> extra "slowFAST" is to be r/w --> /CASU and /CASL for "slowFAST" will be asserted ONLY --> all other /CASL and /CASU will be left at "1" (not selected) To manage "slowFAST" at addresses above $C0, we will simply have to play with /CAS signals. To switch between the 4 banks of 256kb (for the extra 1M + on-board 1M), we will also have to play with /CAS signals. Remember : now /RAS signal is unique and common to ALL CHIPS !! 2> Reusing the on-board 1Meg to be given 2Meg of CHIP ===================================================== You have now understood that you'll have to use 256k chips. Using 1M chips doesn't make any sense, since you will need 16 of them (or 4 using 1Mx4) to be able to generate a 16 bits wide data bus, and this will give you a total of 2Mb !!! And you wanted to save 1Mb didn't you ?... Now check your components warehouse, and the RAM chips on your Amiga PCB. I would suggest you to use the SAME MODEL for the extra 1Meg you will have to add, because, this way, it will be very easy : - solder the new chips OVER the old ones, LEAVING /CAS and /RAS pins twisted upwards (signals not connected yet) ! If you want to use a different model (i.e. 4 chips of 256kx4 while there are 16 chips of 256kx1 on board), you'll have to make your own PCB, with new RAMs on it, then make appropriate links to old RAMs to pick up signals and power. Anyway, you will need : - either 4 chips of 256k x 4, 120ns or less - or 16 chips of 256k x 1, 120ns or less You can also use two 256kx8 SIMMs or SIPPs, or even 256kx9 (the ones for Pee-Cees), leaving the last 9th bit unused. Now the problem of RAMs to use is solved. We still have to manage the new RAS and CAS signals. Here is the way to do it. INV is a single inverter. OR3 is a 3-inputs OR gate. from 2M Agnus to RAMs A20--*-------> 20 20--| | 19--|OR3>---> /CASU bank I-1 --INV---> INV20 /U--| A19--*-------> 19 20--| | 19--|OR3>---> /CASL bank I-1 --INV---> INV19 /L--| /CASU----> /U /R----------> /RAS bank I-1 /CASL----> /L 20--| /RAS ----> /R INV19--|OR3>---> /CASU bank I-2 /U--| 20--| INV19--|OR3>---> /CASL bank I-2 /L--| /R----------> /RAS bank I-2 INV20--| 19--|OR3>---> /CASU bank II-1 /U--| INV20--| 19--|OR3>---> /CASL bank II-1 /L--| /R----------> /RAS bank II-1 INV20--| INV19--|OR3>---> /CASU bank II-2 /U--| INV20--| INV19--|OR3>---> /CASL bank II-2 /L--| /R----------> /RAS bank II-2 The way it works is VERY easy to understand : A20=0 : 1st bank of 1Mb used (on-board) - A19=0 : 1st half bank of 256kb used : bank I-1 - A19=1 : 2nd half bank of 256kb used : bank I-2 A20=1 : 2nd bank of 1Mb used (extra, soldered over the 1st bank, or on a separate PCB) - A19=0 : 1st half bank of 256kb used : bank I-1 - A19=1 : 2nd half bank of 256kb used : bank I-2 Now you are FREE to make it the way you want. I suggest you to use some ALS or F parts instead of common LS, to avoid extra delays as far as possible. Since there is no OR-3 available in TTL technology, you could use instead a F241 buffer, and some OR-2 gates (F32) before : - /1G and 2G are connected to A20 : switch between bank I and II is done, and one inverter is saved (since /1G is an inverted input, and 2G is a true one) - 1Y1..1Y4 outputs are connected to /CASU and /CASL of bank I-1, /CASU and /CASL of bank I-2 - same thing for 2Y1..2Y4 outputs for bank II (1 and 2) - there is one inverter free of use in U107 (F04), pins 12 and 13, feel free to use it to invert A19 and get a INV19 this way - A19 is combined separately with /CASU and /CASL with OR-2, their output being the inputs of F241 itself, like this : F241: 1Y1=/CASU I-1 1Y2=/CASL I-1 1Y3=/CASU I-2 1Y4=/CASL I-2 2Y1=/CASU II-1 2Y2=/CASL II-1 2Y3=/CASU II-2 2Y4=/CASL II-2 20 -*-> /1G | --> 2G 19| /U|OR2>--> 1A1,2A1 19| /L|OR2>--> 1A2,2A2 INV19| /U|OR2>--> 1A3,2A3 INV19| /L|OR2>--> 1A4,2A4 The cheapest way : 1 F241 and 1 F32 only ! And more, ALL /CAS signal are buffered again ! The most convenient part would have been a PAL, but since only a few people might be able to burn it, I thought it was better to use discrete TTL parts... I suggest you to add some resistors in serial with /CAS lines, to avoid overshoots, a common problem while using DRAMs, like this : 47 ohms output from TTL ------^-^-^-^-----*-------> input to DRAMs | +5V |-^-^-^-^------ 470 ohms You can notice that there is a pullup to VCC here, because I make use of a F241 whose outputs are tri-stated for a non-selected bank. Such pullups will avoid untimely peeks to confuse your DRAMs. The next step should be to distinguish between the respective banks and /CAS signals. Suppose that bank I-1 and I-2 are the on-board original chips, and bank II-1 and II-2 are the extra soldered chips. You should consider a full row of 16 chips (or 4 if you have 256kx4). Check which ones are connected to original /CASL and /CASU signals from "old" Agnus. Buffered /CASU is available at pin 14 of U541 (F244), buffered /CASL is available at pin 16 of U541 (F244). Once you know WHERE each /CAS signal IS, you can CUT the tracks from U541. PLEASE BE CAREFUL TO CUT ONLY LINKS TO u541, NOT LINKS BETWEEN CHIPS !!! You will then have the 2 /CASU and 2 /CASL signals for bank I. For the new 1Mb you added, it is much easier because /CAS signals were left unconnected. You should connect /CAS pins by groups of 8 chips (or 2 with 256kx4). You will then have the 2 /CASU and 2 /CASL signals for bank II. You should now have 8 /CAS signals : 4 /CASL and 4 /CASU. Connect them to the new F241... that's all for /CAS. NOTE TO WARPED PEOPLE: You have in your left hand 4 /CASL signals from F541, and in your right hand 4 /CASL inputs to RAMs. Since all RAMs are selected via an unique /RAS, you can FREELY MIX THEM THE WAY YOU WANT ! YOU CAN EVEN FORGET THE Banks I,II,1,2 ! YOU CAN, OF COURSE, ALSO DO IT WITH /CasU SIGNALS ! It will also work PERFECTLY, but I'm afraid you'll have some problems to trace the data bits and to order the banks properly in your schematics... BY THE WAY, NEVER MIX /CasL with /CasU, because 68000 will be misled... You can make your RAMs crazy, but now the 68000 itself... For /RAS signals, I told you in my previous post to cut /RAS0 and /RAS1 from U541 (pins 12 and 7). Since now all /RAS are same, you will have to connect again BOTH /RAS0 and /RAS1 to pin 12 of U541 (please read my previous article !). This way, /RAS0=/RAS1=/RAS. For data bus, you should connect : - bank II-1 to bits 15..8 (since it uses /CASU) - bank II-2 to bits 7..0 (since it uses /CASL) ... if you didn't solder new RAMs onto old ones, and preferred using our own PCB. DON'T MAKE ANY MISTAKE : CHECK THAT Bits 15..8 GO TO /CASU BANKS, AND Bits 7..0 GO TO /CASL BANKS ! (did you read my "NOTE TO WARPED PEOPLE" ?...) Don't forget to put a few more decoupling capacitors on the new RAMs, they will enjoy them a lot. The last thing should be to set the jumpers J101 and J500. Put J101 in 2-3 position and pull J500 out. Read Chapter 1 for more explanations (or my previous post). Of course, you will need a 2M Agnus. So please read my previous post to see how to put it in, and which tracks to cut/add. THAT'S FINISHED ! ---rahhh, I should have some rest here, typing for 2 hours 1/2 ... --- 3> 2Meg CHIP + 1Meg FAST in your Amiga 2000 ! ============================================= ---an only rest of 10 seconds...my fingers are painful--- I suppose now that you have already made my previous 2Meg hack. You should have now a new bank of 2Mb (made of 16 chips 1Mx1 or something like that), an the on-board chips (1Mb) left unused. How pitiful they are, sucking current from power suplply for NOTHING. You'd better give them some work to do, don't you ? Let's study the problem. The "authorized" CHIP address range ($00..1F) is already full with your 2Mb of CHIP RAMs you added previously. Do you guess where there is some place free ? Above $C0 of course ! This is where "old" "slowFAST" 512Kb were put when you had your ancestral 0.5Mb (if you ever had some...). CBM says that they "officially" support only 512Kb here, but there is some more place, free of use. Of course, you shouldn't dare the devil up to death, and I think an extra 1M here is a safe limit... By the way, you will put at $C0 the sleeping chips of your main board, for FREE (considering the price of TTL parts compared to memory...), giving you a total of 2Mb CHIP and 1Mb "slowFAST". Not too bad hmmm ??? I hope you read Chapter 2 earlier. I will take some ideas from it, since the principle is the SAME. You have your 2Mb CHIP managed with /RAS, /CASL and /CASU from 2M Agnus. You have the on-board 1M RAM managed with former /RAS0, /RAS1, and /CASL, /CASU from former 0.5M/1M Agnus. We now have to switch between them, using /CAS instead of /RAS. The technique is really similar, but now A23 will switch between CHIP and "slowFAST" (instead of A20 in Chapter 2), and there is only 1 pair of /CASU+/CASL signals to give to the 2M CHIP, giving a total of 3 /CASU and 3 /CASL to manage (instead of 4 /CASU and 4 /CASL in Chapter 2). The schematics are really straightforward... let's go !!!!! INV is a single inverter. OR2 is a 2-inputs OR gate. OR3 is a 3-inputs OR gate. from 2M Agnus (or 68000 for A23) to RAMS A23--*-------> 23 23--| | /U--|OR2>---> /CASU 2M CHIP --INV---> INV23 A19--*-------> 19 23--| | /L--|OR2>---> /CASL 2M CHIP --INV---> INV19 /CASU----> /U /R----------> /RAS 2M CHIP /CASL----> /L /RAS ----> /R INV23--| 19--|OR3>---> /CASU 1M bank 1 /U--| INV23--| 19--|OR3>---> /CASL 1M bank 1 /L--| /R----------> /RAS 1M bank 1 INV23--| INV19--|OR3>---> /CASU 1M bank 2 /U--| INV23--| INV19--|OR3>---> /CASL 1M bank 2 /L--| /R----------> /RAS 1M bank 2 Once more, the way it works is VERY easy to understand : A23=0 : 2M CHIP used : - A19/A20 are handled by 2M Agnus (MA9) A23=1 : 1M on-board used : - A19=0 : 1st half bank of 256kb used : bank 1 - A19=1 : 2nd half bank of 256kb used : bank 2 Now you are FREE to make it the way you want. I suggest you to use some ALS or F parts instead of common LS, to avoid extra delays as far as possible. Since there is no OR-3 available in TTL technology, you could use instead a F241 buffer, and some OR-2 gates (F32) before : - /1G and 2G are connected to A23 : switch between CHIP and "slowFAST" is done, and one inverter is saved (since /1G is an inverted input, and 2G is a true one) - 1Y1,1Y2 outputs are connected to /CASU and /CASL of 2M CHIP, 1Y3,1Y4 are left unconnected - 2Y1,2Y2 outputs are connected to /CASU and /CASL of bank 1 (1M on board), and 2Y3,2Y4 to /CASU and /CASL of bank 2 (1M on board) - there is one inverter free of use in U107 (F04), pins 12 and 13, feel free to use it to invert A19 and get a INV19 this way - A19 is combined separately with /CASU and /CASL with OR-2, their output being the inputs of F241 itself, like this : F241: 1Y1=/CASU 2M CHIP 1Y2=/CASL 2M CHIP 1Y3= n.c 1Y4= n.c. 2Y1=/CASU bank 1 2Y2=/CASL bank 1.. of 1M on board 2Y3=/CASU bank 2 2Y4=/CASL bank 2.. of 1M on board 23 -*-> /1G | --> 2G /U-------> 1A1 /L-------> 1A2 19| /U|OR2>--> 2A1 19| /L|OR2>--> 2A2 INV19| /U|OR2>--> 2A3 INV19| /L|OR2>--> 2A4 The cheapest way : 1 F241 and 1 F32 only ! And more, ALL /CAS signal are buffered again ! I suggest you to add some resistors in serial with /CAS lines, to avoid overshoots, a common problem while using DRAMs, like this : 47 ohms output from TTL ------^-^-^-^-----*-------> input to DRAMs | +5V |-^-^-^-^------ 470 ohms You can notice that there is a pullup to VCC here, because I make use of a F241 whose outputs are tri-stated for a non-selected bank. Such pullups will avoid untimely peeks to confuse your DRAMs. The next step should be to distinguish between the respective banks and /CAS signals in the on-board 1Meg. There should have two rows of 16 (or 4 if you have 256kx4) chips. You can choose freely which one will be bank 1 and which one bank 2. You should now consider a full bank. Check which chips are connected to original /CASL and /CASU signals from "old" Agnus. Buffered /CASU is available at pin 14 of U541 (F244), buffered /CASL is available at pin 16 of U541 (F244). Once you know WHERE each /CAS signal IS, you can CUT the tracks from U541. PLEASE BE CAREFUL TO CUT ONLY LINKS TO u541, NOT LINKS BETWEEN CHIPS !!! You will then have the 2 /CASU and 2 /CASL signals for the on-board 1Meg. You should now disconnect /CASU and /CASL (of 2M CHIP) links to main board. According to my previous hack, you should have connected them to U541, or on-board 1Meg. You will have to connect them instead to the new hack, at 1Y1 and 1Y2 of F241. You should now have 6 /CAS signals : 3 /CASL and 3 /CASU. Connect them to the new F241... that's all for /CAS. For /RAS signals, I told you in my previous post to cut /RAS0 and /RAS1 from U541 (pins 12 and 7). Since now all /RAS are same, you will have to connect again BOTH /RAS0 and /RAS1 to pin 12 of U541 (please read my previous article !). This way, /RAS0=/RAS1=/RAS. /RAS link has been already done previously for the new 2M CHIP. Same thing for data bus. Now you have some extra RAM at $C0. So that you should put the jumper J500 in, to tell Gary to assert Agnus during $C0... accesses. If you forget to do this, your new 1M of "slowFAST" will NEVER be detected ! Of course, no need for "ADDRAM" or some other utilities. AUTOMATICALLY, the system will sense your 2Meg CHIP, and, due to J500 IN, the $C0... addresses. Check the WB title bar : you should have over 2Mb now ! ---now I REALLY need for a rest... see you again in about half an hour--- 4> SYSTEM CLOCK MULTIPLEXER =========================== The former 0.5M/1M Agnuses received both 28M and XCLK, and selected one of them (upon /XCLKEN) internally. The new 2M Agnus needed 1 more I/O pad for A20, so that XCLK has been sacrificed. In my previous article, I told you how to cut XCLK from Agnus socket, but I didn't tell you how to be able to switch again between internal and external system frequencies. The remedy is so easy. This is the version using NAND-2 gates. 74F00,S00 or AS00 MUST be used, because of the high frequencies involved : internal oscillator, pin 8----- | --| ---------| /XCLKEN---*-|NAND2>--------------------|NAND2>-----| | ---|NAND2>---28M -----------------------------| | XCLK-----------------------------------|NAND2>--- And here is the version with 74 S 51 : internal oscillator, pin 8----> 13 /XCLKEN-----------------------> 1, 2, 3 XCLK--------------------------> 10 to ground---------------------> 4, 5 8 -----------------> 28M 6 and 9 connected to each other 14 to VCC, 7 to ground You can choose the one you prefer, but the installation procedure is the same. - look for the main oscillator (28.xxx MHZ) - cut its output (pin 8), leave the track free - connect this pin 8 to the multiplexer - connect the output of the multiplexer to the previous track - connect XCLK from video connector to the multiplexer (it can be also found close to Agnus since you cut this track for the 2M hack...) - connect /XCLKEN from Agnus to the multiplexer Don't forget to use a decoupling capacitor for the TTL part. 5> AS A CONCLUSION ================== Your Amiga is now ready for new experiments. 2M CHIP, and 1M "slowFAST" eventually, should be enough for many of you, I suppose. You didn't need any memory expansion board at all : you made yours ! Easily... I'm now waiting for your replies. Try this new enhanced hack if you DARE ! P-chan. --- Pascal JANIN - Amiga maniac.. /// ..and Anime addict Forever... STANLEY ELECTRIC CO. /// R&D Group 71G, Japan \\\ /// "Yappappaa yappappaa Pi-i chan desu!" Fax: 81+ 45-911-0007 \\X// Email:NO! Fax/"F":YES! \/ "Kyoko-san ! Suki jaaa-- !!" >Godai-kun -- ****** REMEMBER : I canNOT reply you by E-mail, only r/w here !!! ****** **** To all friends who mail me directly and ask me for a mailed reply : **** don't forget that I CANNOT reply to you via E-mail !