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fastrom040.c
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C/C++ Source or Header
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1991-11-05
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7KB
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251 lines
/*
FastROM040 V1.0a for the Progressive Peripipherals & Software 040/A3000
by Greg Tibbs; some code from SetCPU V1.4 by Dave Haynie
MAIN PROGRAM
Assumptions: The PPS 040 for the A3000 only works under 2.0+, so
assumptions that exec knows about an 040, that ROMsize
is 512K. The PPS 040 has no onboard memory, so the
area mapped from 0x0100000 on to the base of the A3000
motherboard Ram is made invalid in the Address translation
cache and accesses there will yield an address error
exception. Zorro III memory area is made data &
instruciton cachable, with ZorroII I/o space not
cachable at all (040 limitation in that there is no
ddistinction in the ATC between data accesses and
instruction accesses. The only way around this is
with the mTTX registers which will be used primarily
in fast ram.
*/
#define PROGRAM_VERSION "V1.0a"
#include <exec/types.h>
#include <exec/execbase.h>
#include <exec/nodes.h>
#include <exec/interrupts.h>
#include <stdio.h>
/* ====================================================================== */
/* Define all bit components used for manipulation of the Cache Control
Register. */
#define CACR_INST (1L<<15)
#define CACR_DATA (1L<<31)
#define CACR_ENB (CACR_INST | CACR_DATA)
#define ROUND 0x00002000L
#define ROMBASE 0x00F80000L
#define ROMSIZE 0x00080000L
#define TABSIZE (128L * sizeof(ULONG))
#define LEV3TABSIZE 0x2000L
/* ====================================================================== */
/* Define important bits used in various MMU registers. */
/* Here are the TC definitions. The TC register is 32 bits long. */
#define TC_ENB ((1L<<15)+(1L<<14)+(1L<<31)+(1L<<30)) /* Enable the MMU with 8K pages*/
/* Here are the page descriptor definitions, for short desctriptors only,
since that's all I'm using at this point. */
/* ====================================================================== */
/* Some external declarations. */
void SetCACR(), DumpCache(), SetCRP(), SetTC();
void SetITT0(), SetITT1(), SetDTT0(), SetDTT1();
ULONG GetCACR(), GetTC(), GetCPUType(), GetCRP();
ULONG GetDTT0(), GetDTT1(), GetITT0(), GetITT1();
/* ====================================================================== */
/* This replaces the Lattice "stricmp()" function, plus it's a better form
for my needs here. */
static BOOL striequ(s1,s2)
char *s1,*s2;
{
BOOL aok;
while (*s1 && *s2 && (aok = (*s1++ & 0xdf) == (*s2++ & 0xdf)));
return (BOOL) (!*s1 && aok);
}
/* ====================================================================== */
/* Page tables and other MMU stuff must be on a page sized boundary, and
that boundary must be a power of two. This routine allocates such an
aligned block of memory. */
void *AllocAligned(size,bound)
ULONG size;
ULONG bound;
{
void *mem, *aligned;
if (!(mem = (void *)AllocMem(size+bound,0L))) return NULL;
Forbid();
aligned = (void *)(((ULONG)mem + bound - 1) & ~(bound - 1));
FreeMem(mem,size+bound);
mem = (void *)AllocAbs(size,aligned);
Permit();
return mem;
}
int main(argc,argv)
int argc;
char *argv[];
{
ULONG i, cpu, myCRP, myTC, cacr, ROMADDR, *MMUTable;
ULONG dtt0,*MMUTable2,*MMUTable3, *ROM32;
ULONG fdtt0, fdtt1,fitt0,fitt1,cache;
/* If they're just asking for help */
if (argc >= 2 && argv[1][0] == '?') {
printf("\n\2337mFASTROM040 %s For PPS 040/A3000\2330m [CACHEZ2]\n"
,PROGRAM_VERSION);
exit(0L);
}
cache = 0L;
if (argc >=2 && striequ(argv[1],"CACHEZ2"))
{
cache=1L;
printf("Zorro II area will be cached!\n");
}
/* Let's find out what we have, and perform the ROM translation */
if ((cpu=GetCPUType())==68040)
{
printf("68040 CPU found.\n");
}
else
{
printf("68040 Not Present!!!\n");
exit(5L);
}
myTC=GetTC();
if (myTC & TC_ENB) {
printf("MMU in operation! FastROM not performed.\n");
exit(5L);
}
/* This routine creates the Fast ROM. If the memory can't be allocated,
it returns FALSE, otherwise, TRUE. */
/* First off, get the memory for the 32 bit ROM and the MMU table. */
ROM32 = AllocAligned(ROMSIZE,ROUND);
MMUTable = AllocAligned(TABSIZE,ROUND);
MMUTable2 = AllocAligned(TABSIZE,ROUND);
MMUTable3 = AllocAligned(LEV3TABSIZE,ROUND);
if (!ROM32 || !MMUTable || !MMUTable2 || !MMUTable3) {
if (MMUTable) FreeMem(MMUTable,TABSIZE);
if (MMUTable2) FreeMem(MMUTable2,TABSIZE);
if (MMUTable3) FreeMem(MMUTable3,LEV3TABSIZE);
if (ROM32) FreeMem(ROM32,ROMSIZE);
printf("Memory Failure in FastROM allocation!\n");
exit(5L);
}
ROMADDR=(ULONG)ROM32;
/* Here I set up the ROM, as quickly as possible! */
CopyMemQuick(ROMBASE,ROM32,ROMSIZE);
/* MMUTable is the root pointer table for the ATC. mTTx covers 3/4 of all RAM
so all but the lowest 32 Meg is declared invalid to save table space. The
mTTx registers overrides this table, so most A3000 ram areas are OK except
some Zorro III areas, which are spotty.
MMUTable2 is the 2nd level table for the lower 32 Meg of address space.
The upper 16 Meg will be declared invalid to save space. The lower
16 meg is addressed via MMUTable3 which actually contains 64 tables of
thirty-two 8K page descriptors. */
/* Set up 1st Level Table */
for (i = 1; i < 128; i++) *(MMUTable+i) = 0L; //Invalid Pages (> 32Meg)
MMUTable[0] = (((ULONG)MMUTable2 & ~0x1ffL) | 0x3L); //Point to Level 2 Table
/* Set up 2nd Level Table */
for (i=64; i<128;i++) *(MMUTable2+i)=0L; //Invalid Pages (>16Meg, < 32Meg)
for (i=0;i<64;i++) *(MMUTable2+i)=(((ULONG)&MMUTable3[i*32]&~0x7fL)|0x3L);
/* Set up 3rd level Tables */
for (i=0;i<1984;i++) *(MMUTable3+i) = (((8192*i) & ~0x1fffL) | 0x441L);
for (i=0;i<64;i++) *(MMUTable3+i+1984)=(((ROMADDR+(8192*i))&~0x1fffL)|0x405L);
if(cache>0) for(i=256;i<1280;i++) *(MMUTable3+i)+=0x3CL; // Turn on Z2 caching
/* Now I have to set up the MMU. The User Root Pointer tells the MMU about
the table I've set up, and the Translation Control register will turn
the thing on. */
/* itt0 = 0L;
itt1 = 0xffc000L;*/
dtt0 = 0xc040L;
/* dtt1 = 0xffc020L; Default Progressive Translation register values */
fdtt0=0x04fbc020L; // Set up Data Translation Registers
fdtt1=0x08f7c020L;
fitt0=0x04fbc000L; // Set up Instruction Translation Registers
fitt1=0x08f7c000L;
Forbid();
Disable();
SetDTT1(0L);
SetDTT0(dtt0);
SetITT1(0L);
SetITT0(0L);
SetTC(0L); // Disable Address Translations
SetCACR(0L); // Turn I & D Caches off
DumpCache(); // Flush Data, Instruction and ATC
/* Note that mTTx are overriding all ATC entries that I set up */
myCRP = (ULONG)MMUTable & ~0x1ffL; // Set URP & SRP
SetCRP(myCRP);
SetDTT1(fdtt1);// Send new mTTx registers which match ATC Tables
SetDTT0(fdtt0);
SetITT1(fitt1);
SetITT0(fitt0);
myTC = TC_ENB;
SetTC(myTC); // Enable Translation via tables
Enable();
Permit();
DumpCache();
cacr = CACR_ENB;
SetCACR(cacr); // Turn on Data and Instruction Caches
printf("Fastrom enabled.\n ");
exit(0L);
}