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GNU Info File
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1994-02-06
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45KB
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767 lines
This is Info file gcc.info, produced by Makeinfo-1.49 from the input
file gcc.texi.
This file documents the use and the internals of the GNU compiler.
Copyright (C) 1988, 1989, 1992 Free Software Foundation, Inc.
Permission is granted to make and distribute verbatim copies of this
manual provided the copyright notice and this permission notice are
preserved on all copies.
Permission is granted to copy and distribute modified versions of
this manual under the conditions for verbatim copying, provided also
that the sections entitled "GNU General Public License" and "Protect
Your Freedom--Fight `Look And Feel'" are included exactly as in the
original, and provided that the entire resulting derived work is
distributed under the terms of a permission notice identical to this
Permission is granted to copy and distribute translations of this
manual into another language, under the above conditions for modified
versions, except that the sections entitled "GNU General Public
License" and "Protect Your Freedom--Fight `Look And Feel'", and this
permission notice, may be included in translations approved by the Free
Software Foundation instead of in the original English.
File: gcc.info, Node: Patterns, Next: Example, Prev: Machine Desc, Up: Machine Desc
Everything about Instruction Patterns
=====================================
Each instruction pattern contains an incomplete RTL expression, with
pieces to be filled in later, operand constraints that restrict how the
pieces can be filled in, and an output pattern or C code to generate
the assembler output, all wrapped up in a `define_insn' expression.
A `define_insn' is an RTL expression containing four or five
operands:
1. An optional name. The presence of a name indicate that this
instruction pattern can perform a certain standard job for the
RTL-generation pass of the compiler. This pass knows certain
names and will use the instruction patterns with those names, if
the names are defined in the machine description.
The absence of a name is indicated by writing an empty string
where the name should go. Nameless instruction patterns are never
used for generating RTL code, but they may permit several simpler
insns to be combined later on.
Names that are not thus known and used in RTL-generation have no
effect; they are equivalent to no name at all.
2. The "RTL template" (*note RTL Template::.) is a vector of
incomplete RTL expressions which show what the instruction should
look like. It is incomplete because it may contain
`match_operand', `match_operator', and `match_dup' expressions
that stand for operands of the instruction.
If the vector has only one element, that element is the template
for the instruction pattern. If the vector has multiple elements,
then the instruction pattern is a `parallel' expression containing
the elements described.
3. A condition. This is a string which contains a C expression that
is the final test to decide whether an insn body matches this
pattern.
For a named pattern, the condition (if present) may not depend on
the data in the insn being matched, but only the
target-machine-type flags. The compiler needs to test these
conditions during initialization in order to learn exactly which
named instructions are available in a particular run.
For nameless patterns, the condition is applied only when matching
an individual insn, and only after the insn has matched the
pattern's recognition template. The insn's operands may be found
in the vector `operands'.
4. The "output template": a string that says how to output matching
insns as assembler code. `%' in this string specifies where to
substitute the value of an operand. *Note Output Template::.
When simple substitution isn't general enough, you can specify a
piece of C code to compute the output. *Note Output Statement::.
5. Optionally, a vector containing the values of attributes for insns
matching this pattern. *Note Insn Attributes::.
File: gcc.info, Node: Example, Next: RTL Template, Prev: Patterns, Up: Machine Desc
Example of `define_insn'
========================
Here is an actual example of an instruction pattern, for the
68000/68020.
(define_insn "tstsi"
[(set (cc0)
(match_operand:SI 0 "general_operand" "rm"))]
""
"*
{ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
return \"tstl %0\";
return \"cmpl #0,%0\"; }")
This is an instruction that sets the condition codes based on the
value of a general operand. It has no condition, so any insn whose RTL
description has the form shown may be handled according to this
pattern. The name `tstsi' means "test a `SImode' value" and tells the
RTL generation pass that, when it is necessary to test such a value, an
insn to do so can be constructed using this pattern.
The output control string is a piece of C code which chooses which
output template to return based on the kind of operand and the specific
type of CPU for which code is being generated.
`"rm"' is an operand constraint. Its meaning is explained below.
File: gcc.info, Node: RTL Template, Next: Output Template, Prev: Example, Up: Machine Desc
RTL Template for Generating and Recognizing Insns
=================================================
The RTL template is used to define which insns match the particular
pattern and how to find their operands. For named patterns, the RTL
template also says how to construct an insn from specified operands.
Construction involves substituting specified operands into a copy of
the template. Matching involves determining the values that serve as
the operands in the insn being matched. Both of these activities are
controlled by special expression types that direct matching and
substitution of the operands.
`(match_operand:M N PREDICATE CONSTRAINT)'
This expression is a placeholder for operand number N of the insn.
When constructing an insn, operand number N will be substituted
at this point. When matching an insn, whatever appears at this
position in the insn will be taken as operand number N; but it
must satisfy PREDICATE or this instruction pattern will not match
at all.
Operand numbers must be chosen consecutively counting from zero in
each instruction pattern. There may be only one `match_operand'
expression in the pattern for each operand number. Usually
operands are numbered in the order of appearance in `match_operand'
expressions.
PREDICATE is a string that is the name of a C function that
accepts two arguments, an expression and a machine mode. During
matching, the function will be called with the putative operand as
the expression and M as the mode argument (if M is not specified,
`VOIDmode' will be used, which normally causes PREDICATE to accept
any mode). If it returns zero, this instruction pattern fails to
match. PREDICATE may be an empty string; then it means no test is
to be done on the operand, so anything which occurs in this
position is valid.
Most of the time, PREDICATE will reject modes other than M--but
not always. For example, the predicate `address_operand' uses M
as the mode of memory ref that the address should be valid for.
Many predicates accept `const_int' nodes even though their mode is
`VOIDmode'.
CONSTRAINT controls reloading and the choice of the best register
class to use for a value, as explained later (*note
Constraints::.).
People are often unclear on the difference between the constraint
and the predicate. The predicate helps decide whether a given
insn matches the pattern. The constraint plays no role in this
decision; instead, it controls various decisions in the case of an
insn which does match.
On CISC machines, PREDICATE is most often `"general_operand"'.
This function checks that the putative operand is either a
constant, a register or a memory reference, a