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i960.h
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1994-02-06
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/* Definitions of target machine for GNU compiler, for Intel 80960
Copyright (C) 1992 Free Software Foundation, Inc.
Contributed by Steven McGeady, Intel Corp.
Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
/* Note that some other tm.h files may include this one and then override
many of the definitions that relate to assembler syntax. */
/* Names to predefine in the preprocessor for this target machine. */
#define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960"
/* Name to predefine in the preprocessor for processor variations. */
#define CPP_SPEC "%{mic*:-D__i960\
%{mka:-D__i960KA}%{mkb:-D__i960KB}%{mkc:-D__i960KC}\
%{msa:-D__i960SA}%{msb:-D__i960SB}%{msc:-D__i960SC}\
%{mmc:-D__i960MC}\
%{mca:-D__i960CA}%{mcb:-D__i960CB}%{mcc:-D__i960CC}\
%{mcf:-D__i960CF}}\
%{mka:-D__i960KA__ -D__i960_KA__}\
%{mkb:-D__i960KB__ -D__i960_KB__}\
%{mkc:-D__i960KC__ -D__i960_KC__}\
%{msa:-D__i960SA__ -D__i960_SA__}\
%{msb:-D__i960SB__ -D__i960_SB__}\
%{msc:-D__i960SC__ -D__i960_SC__}\
%{mmc:-D__i960MC__ -D__i960_MC__}\
%{mca:-D__i960CA__ -D__i960_CA__}\
%{mcb:-D__i960CB__ -D__i960_CB__}\
%{mcc:-D__i960CC__ -D__i960_CC__}\
%{mcf:-D__i960CF__ -D__i960_CF__}\
%{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\
%{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}}}}"
/* -mic* options make characters signed by default. */
#define SIGNED_CHAR_SPEC \
(DEFAULT_SIGNED_CHAR ? "%{funsigned-char:-D__CHAR_UNSIGNED__}" \
: "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}")
/* Specs for the compiler, to handle processor variations. */
#define CC1_SPEC \
"%{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\
%{!mcc:%{!mcf:-mkb}}}}}}}}}}}\
%{mbout:%{g*:-gstabs}}\
%{mcoff:%{g*:-gcoff}}\
%{!mbout:%{!mcoff:%{g*:-gstabs}}}"
/* Specs for the assembler, to handle processor variations.
For compatibility with Intel's gnu960 tool chain, pass -A options to
the assembler. */
#define ASM_SPEC \
"%{mka:-AKA}%{mkb:-AKB}%{mkc:-AKC}%{msa:-ASA}%{msb:-ASB}\
%{msc:-ASC}%{mmc:-AMC}%{mca:-ACA}%{mcb:-ACB}%{mcc:-ACC}%{mcf:-ACF}\
%{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\
%{!mcc:%{!mcf:-AKB}}}}}}}}}}}"
/* Specs for the linker, to handle processor variations.
For compatibility with Intel's gnu960 tool chain, pass -F and -A options
to the linker. */
#define LINK_SPEC \
"%{mka:-AKA}%{mkb:-AKB}%{mkc:-AKC}%{msa:-ASA}%{msb:-ASB}\
%{msc:-ASC}%{mmc:-AMC}%{mca:-ACA}%{mcb:-ACB}%{mcc:-ACC}%{mcf:-ACF}\
%{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\
%{!mcc:%{!mcf:-AKB}}}}}}}}}}}\
%{mbout:-Fbout}%{mcoff:-Fcoff}"
/* Specs for the libraries to link with, to handle processor variations.
Compatible with Intel's gnu960 tool chain. */
#define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\
%{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}"
/* Omit frame pointer at -O2. Inline functions at -O3. */
#define OPTIMIZATION_OPTIONS(LEVEL) \
{ \
if ((LEVEL) >= 2) \
{ \
flag_omit_frame_pointer = 1; \
target_flags |= TARGET_FLAG_LEAFPROC; \
target_flags |= TARGET_FLAG_TAILCALL; \
} \
if ((LEVEL) >= 3) \
flag_inline_functions = 1; \
}
/* Print subsidiary information on the compiler version in use. */
#define TARGET_VERSION fprintf (stderr," (intel 80960)");
/* Generate DBX debugging information. */
#define DBX_DEBUGGING_INFO
/* Generate SDB style debugging information. */
#define SDB_DEBUGGING_INFO
/* Generate DBX_DEBUGGING_INFO by default. */
#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
/* Redefine this to print in hex like iC960. */
#define PUT_SDB_TYPE(A) fprintf (asm_out_file, "\t.type\t0x%x;", A)
/* Run-time compilation parameters selecting different hardware subsets. */
/* 960 architecture with floating-point. */
#define TARGET_FLAG_NUMERICS 0x01
#define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS)
/* 960 architecture with memory management. */
/* ??? Not used currently. */
#define TARGET_FLAG_PROTECTED 0x02
#define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED)
/* The following three are mainly used to provide a little sanity checking
against the -mARCH flags given. */
/* Nonzero if we should generate code for the KA and similar processors.
No FPU, no microcode instructions. */
#define TARGET_FLAG_K_SERIES 0x04
#define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES)
/* Nonzero if we should generate code for the MC processor.
Not really different from KB for our purposes. */
#define TARGET_FLAG_MC 0x08
#define TARGET_MC (target_flags & TARGET_FLAG_MC)
/* Nonzero if we should generate code for the CA processor.
Enables different optimization strategies. */
#define TARGET_FLAG_C_SERIES 0x10
#define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES)
/* Nonzero if we should generate leaf-procedures when we find them.
You may not want to do this because leaf-proc entries are
slower when not entered via BAL - this would be true when
a linker not supporting the optimization is used. */
#define TARGET_FLAG_LEAFPROC 0x20
#define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC)
/* Nonzero if we should perform tail-call optimizations when we find them.
You may not want to do this because the detection of cases where
this is not valid is not totally complete. */
#define TARGET_FLAG_TAILCALL 0x40
#define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL)
/* Nonzero if use of a complex addressing mode is a win on this implementation.
Complex addressing modes are probably not worthwhile on the K-series,
but they definitely are on the C-series. */
#define TARGET_FLAG_COMPLEX_ADDR 0x80
#define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR)
/* Align code to 8 byte boundaries for faster fetching. */
#define TARGET_FLAG_CODE_ALIGN 0x100
#define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN)
/* Append branch prediction suffixes to branch opcodes. */
/* ??? Not used currently. */
#define TARGET_FLAG_BRANCH_PREDICT 0x200
#define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT)
/* Forces prototype and return promotions. */
/* ??? This does not work. */
#define TARGET_FLAG_CLEAN_LINKAGE 0x400
#define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE)
/* For compatibility with iC960 v3.0. */
#define TARGET_FLAG_IC_COMPAT3_0 0x800
#define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0)
/* For compatibility with iC960 v2.0. */
#define TARGET_FLAG_IC_COMPAT2_0 0x1000
#define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0)
/* If no unaligned accesses are to be permitted. */
#define TARGET_FLAG_STRICT_ALIGN 0x2000
#define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN)
/* For compatibility with iC960 assembler. */
#define TARGET_FLAG_ASM_COMPAT 0x4000
#define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT)
/* For compatibility with the gcc960 v1.2 compiler. Use the old structure
alignement rules. Also, turns on STRICT_ALIGNMENT. */
#define TARGET_FLAG_OLD_ALIGN 0x8000
#define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN)
extern int target_flags;
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
where VALUE is the bits