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gmicro.h
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1994-02-06
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/* Definitions of target machine for GNU compiler. Gmicro (TRON) version.
Ported by Masanobu Yuhara, Fujitsu Laboratories LTD.
(yuhara@flab.fujitsu.co.jp)
Copyright (C) 1987, 1988, 1989 Free Software Foundation, Inc.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Among other things, the copyright
notice and this notice must be preserved on all copies.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* Note that some other tm.h files include this one and then override
many of the definitions that relate to assembler syntax. */
/* Names to predefine in the preprocessor for this target machine. */
#define CPP_PREDEFINES "-Dgmicro"
/* #define CPP_SPEC ** currently not defined **/
/* #define CC1_SPEC ** currently not defined **/
/* Print subsidiary information on the compiler version in use. */
/*
#define TARGET_VERSION fprintf (stderr, " (Gmicro syntax)");
*/
/* Run-time compilation parameters selecting different hardware subsets. */
extern int target_flags;
/* Macros used in the machine description to test the flags. */
/* Compile for a Gmicro/300. */
#define TARGET_G300 (target_flags & 1)
/* Compile for a Gmicro/200. */
#define TARGET_G200 (target_flags & 2)
/* Compile for a Gmicro/100. */
#define TARGET_G100 (target_flags & 4)
/* Compile FPU insns for floating point (not library calls). */
#define TARGET_FPU (target_flags & 8)
/* Pop up arguments by called function. */
#define TARGET_RTD (target_flags & 0x10)
/* Compile passing first args in regs 0 and 1.
This exists only to test compiler features that will be needed for
RISC chips. It is not usable and is not intended to be usable on
this cpu ;-< */
#define TARGET_REGPARM (target_flags & 0x20)
#define TARGET_BITFIELD (target_flags & 0x40)
#define TARGET_NEWRETURN (target_flags & 0x80)
/* Do not expand __builtin_smov (strcpy) to multiple movs.
Use the smov instruction. */
#define TARGET_FORCE_SMOV (target_flags & 0x100)
/* default options are -m300, -mFPU,
with bitfield instructions added because it won't always work otherwise.
If there are versions of the gmicro that don't support bitfield instructions
then it will take some thinking to figure out how to make them work. */
#define TARGET_DEFAULT 0x49
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
where VALUE is the bits to set or minus the bits to clear.
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
{ { "g300", 1}, \
{ "g200", 2}, \
{ "g100", 4}, \
{ "fpu", 8}, \
{ "soft-float", -8}, \
{ "rtd", 0x10}, \
{ "no-rtd", -0x10}, \
{ "regparm", 0x20}, \
{ "no-regparm", -0x20}, \
#if 0 /* Since we don't define PCC_BITFIELD_TYPE_MATTERS or use a large
STRUCTURE_SIZE_BOUNDARY, we must have bitfield instructions. */
{ "bitfield", 0x40}, \
{ "no-bitfield", -0x40}, \
#endif
{ "newreturn", 0x80}, \
{ "no-newreturn", -0x80}, \
{ "force-smov", 0x100}, \
{ "no-force-smov", -0x100}, \
{ "", TARGET_DEFAULT}}
/* Blow away G100 flag silently off TARGET_fpu (since we can't clear
any bits in TARGET_SWITCHES above) */
#define OVERRIDE_OPTIONS \
{ \
if (TARGET_G100) target_flags &= ~8; \
}
/* target machine storage layout */
/* Define this if most significant bit is lowest numbered
in instructions that operate on numbered bit-fields.
This is true for Gmicro insns.
We make it true always by avoiding using the single-bit insns
except in special cases with constant bit numbers. */
#define BITS_BIG_ENDIAN 1
/* Define this if most significant byte of a word is the lowest numbered. */
/* That is true on the Gmicro. */
#define BYTES_BIG_ENDIAN 1
/* Define this if most significant word of a multiword number is the lowest
numbered. */
/* For Gmicro we can decide arbitrarily
since there are no machine instructions for them. ????? */
#define WORDS_BIG_ENDIAN 0
/* number of bits in an addressable storage unit */
#define BITS_PER_UNIT 8
/* Width in bits of a "word", which is the contents of a machine register. */
#define BITS_PER_WORD 32
/* Width of a word, in units (bytes). */
#define UNITS_PER_WORD 4
/* Width in bits of a pointer.
See also the macro `Pmode' defined below. */
#define POINTER_SIZE 32
/* Allocation boundary (in *bits*) for storing arguments in argument list. */
#define PARM_BOUNDARY 32
/* Boundary (in *bits*) on which stack pointer should be aligned. */
#define STACK_BOUNDARY 32
/* Allocation boundary (in *bits*) for the code of a function. */
/* Instructions of the Gmicro should be on half-word boundary */
/* But word boundary gets better performance */
#define FUNCTION_BOUNDARY 32
/* Alignment of field after `int : 0' in a structure. */
#define EMPTY_FIELD_BOUNDARY 32
/* No data type wants to be aligned rounder than this. */
/* This is not necessarily 32 on the Gmicro */
#define BIGGEST_ALIGNMENT 32
/* Set this non-zero if move instructions will actually fail to work
when given unaligned data. */
Unaligned data is allowed on Gmicro, though the access is slow. */
#define STRICT_ALIGNMENT 1
#define SLOW_UNALIGNED_ACCESS 1
/* Make strings word-aligned so strcpy from constants will be faster. */
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
(TREE_CODE (EXP) == STRING_CST \
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
/* Make arrays of chars word-aligned for the same reasons. */
#define DATA_ALIGNMENT(TYPE, ALIGN) \
(TREE_CODE (TYPE) == ARRAY_TYPE \
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
/* Define number of bits in most basic integer type.
(If undefined, default is BITS_PER_WORD). */
#define INT_TYPE_SIZE 32
/* #define PCC_BITFIELD_TYPE_MATTERS 1 ????? */
/* #define CHECK_FLOAT_VALUE (MODE, VALUE) ????? */
/* Standard register usage. */
/* Number of actual hardware registers.
The hardware registers are assigned numbers for the compiler
from 0 to just below FIRST_PSEUDO_REGISTER.
All registers that the compiler knows about must be given numbers,
even those that are not normally considered general registers.
For the Gmicro, we give the general registers numbers 0-15,
and the FPU floating point registers numbers 16-31. */
#define FIRST_PSEUDO_REGISTER 32
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator.
On the Gmicro, the stack pointer and the frame pointer are
such registers. */
/* frame pointer is not indicated as fixed, because fp may be used freely
when a frame is not built. */
#define FIXED_REGISTERS \
{0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, \
/* FPU registers. */ \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, }
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
registers that can be used without being saved.
The latter must include the registers where values are returned
and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like. */
#define CALL_USED_REGISTERS \
{1, 1, 1, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, \
/* FPU registers. */ \
1, 1, 1, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, }
/* Make sure everything's fine if we *don't* have a given processor.
This assumes that putting a register in fixed_regs will keep the
compilers mitt's completely