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fx80.h
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1994-02-06
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/* Definitions of target machine for GNU compiler. Alliant FX version.
Copyright (C) 1989 Free Software Foundation, Inc.
Adapted from m68k.h by Paul Petersen (petersen@uicsrd.csrd.uiuc.edu)
and Joe Weening (weening@gang-of-four.stanford.edu).
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
/* This file is based on m68k.h, simplified by removing support for
the Sun FPA and other things not applicable to the Alliant. Some
remnants of these features remain. */
/* Names to predefine in the preprocessor for this target machine. */
#define CPP_PREDEFINES "-Dmc68000 -Dalliant -Dunix"
/* Print subsidiary information on the compiler version in use. */
#define TARGET_VERSION fprintf (stderr, " (Alliant)");
/* Run-time compilation parameters selecting different hardware
subsets. The Alliant IP is an mc68020. (Older mc68010-based IPs
are no longer supported.) The Alliant CE is 68020-compatible, and
also has floating point, vector and concurrency instructions.
Although the IP doesn't have floating point, it emulates it in the
operating system. Using this generally is faster than running code
compiled with -msoft-float, because the soft-float code still uses
(simulated) FP registers and ends up emulating several fmove{s,d}
instructions per call. So I don't recommend using soft-float for
any Alliant code. -- JSW
*/
extern int target_flags;
/* Macros used in the machine description to test the flags. */
/* Compile for a 68020 (not a 68000 or 68010). */
#define TARGET_68020 (target_flags & 1)
/* Compile CE insns for floating point (not library calls). */
#define TARGET_CE (target_flags & 2)
/* Compile using 68020 bitfield insns. */
#define TARGET_BITFIELD (target_flags & 4)
/* Compile with 16-bit `int'. */
#define TARGET_SHORT (target_flags & 040)
/* Default 3 means compile 68020 and CE instructions. We don't use
bitfield instructions because there appears to be a bug in the
implementation of bfins on the CE. */
#define TARGET_DEFAULT 3
/* Define __HAVE_CE__ in preprocessor according to the -m flags.
This will control the use of inline FP insns in certain macros.
Also inform the program which CPU this is for. */
#if TARGET_DEFAULT & 02
/* -mce is the default */
#define CPP_SPEC \
"%{!msoft-float:-D__HAVE_CE__ }\
%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
#else
/* -msoft-float is the default */
#define CPP_SPEC \
"%{mce:-D__HAVE_CE__ }\
%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
#endif
/* Link with libg.a when debugging, for dbx's sake. */
#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
/* Make the linker remove temporary labels, since the Alliant assembler
doesn't. */
#define LINK_SPEC "-X"
/* Every structure or union's size must be a multiple of 2 bytes. */
#define STRUCTURE_SIZE_BOUNDARY 16
/* This is BSD, so it wants DBX format. */
#define DBX_DEBUGGING_INFO
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
where VALUE is the bits to set or minus the bits to clear.
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
{ { "68020", 5}, \
{ "c68020", 5}, \
{ "bitfield", 4}, \
{ "68000", -7}, \
{ "c68000", -7}, \
{ "soft-float", -2}, \
{ "nobitfield", -4}, \
{ "short", 040}, \
{ "noshort", -040}, \
{ "", TARGET_DEFAULT}}
/* target machine storage layout */
/* Define this if most significant bit is lowest numbered
in instructions that operate on numbered bit-fields.
This is true for 68020 insns such as bfins and bfexts.
We make it true always by avoiding using the single-bit insns
except in special cases with constant bit numbers. */
#define BITS_BIG_ENDIAN 1
/* Define this if most significant byte of a word is the lowest numbered. */
/* That is true on the 68000. */
#define BYTES_BIG_ENDIAN 1
/* Define this if most significant word of a multiword number is the lowest
numbered. */
/* For 68000 we can decide arbitrarily
since there are no machine instructions for them. */
#define WORDS_BIG_ENDIAN 0
/* number of bits in an addressable storage unit */
#define BITS_PER_UNIT 8
/* Width in bits of a "word", which is the contents of a machine register.
Note that this is not necessarily the width of data type `int';
if using 16-bit ints on a 68000, this would still be 32.
But on a machine with 16-bit registers, this would be 16. */
#define BITS_PER_WORD 32
/* Width of a word, in units (bytes). */
#define UNITS_PER_WORD 4
/* Width in bits of a pointer.
See also the macro `Pmode' defined below. */
#define POINTER_SIZE 32
/* Allocation boundary (in *bits*) for storing arguments in argument list. */
#define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
/* Boundary (in *bits*) on which stack pointer should be aligned. */
#define STACK_BOUNDARY 16
/* Allocation boundary (in *bits*) for the code of a function. */
#define FUNCTION_BOUNDARY 16
/* Alignment of field after `int : 0' in a structure. */
#define EMPTY_FIELD_BOUNDARY 16
/* No data type wants to be aligned rounder than this. */
#define BIGGEST_ALIGNMENT 16
/* Set this non-zero if move instructions will actually fail to work
when given unaligned data. */
#define STRICT_ALIGNMENT 1
/* Define number of bits in most basic integer type.
(If undefined, default is BITS_PER_WORD). */
#define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
/* Define these to avoid dependence on meaning of `int'.
Note that WCHAR_TYPE_SIZE is used in cexp.y,
where TARGET_SHORT is not available. */
#define WCHAR_TYPE "long int"
#define WCHAR_TYPE_SIZE 32
/* Standard register usage. */
/* Number of actual hardware registers.
The hardware registers are assigned numbers for the compiler
from 0 to just below FIRST_PSEUDO_REGISTER.
All registers that the compiler knows about must be given numbers,
even those that are not normally considered general registers.
For the Alliant, we give the data registers numbers 0-7,
the address registers numbers 010-017,
and the floating point registers numbers 020-027. */
#define FIRST_PSEUDO_REGISTER 24
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator.
On the Alliant, these are a0 (argument pointer),
a6 (frame pointer) and a7 (stack pointer). */
#define FIXED_REGISTERS \
{0, 0, 0, 0, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0 }
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
registers that can be used without being saved.
The latter must include the registers where values are returned
and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like.
The Alliant calling sequence allows a function to use any register,
so we include them all here. */
#define CALL_USED_REGISTERS \
{1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1 }
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
This is ordinarily the length in words of a value of mode MODE
but can be less for certain modes in special long registers.
On the Alliant, ordinary registers hold 32 bits worth;
for the FP registers, a single register is alway