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066010000030000132002000000006000
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F0110030001
9[......◆.......................................................................]0110
ÇüINSTRUCTIONEXECUTIONTIMESÇ
üD.1INTRODUCTIONÇ
ThisAppendixcontainslistingsoftheinstructionexecutiontimesintermsof
externalclock(CLK)periods.Inthisdata,itisassumedthatbothmemoryread
andwritecycletimesarefourclockperiods.Alongermemorycyclewillcause
thegenerationofwaitstateswhichmustbeaddedtothetotalinstructiontime.
Thenumberofbusreadandwritecyclesforeachinstructionisalsoincluded
withthetimingdata.Thisdataisenclosedinparantheisisfollowingthenumber
ofclockperiodsandisshownas:(r/w)whereristhenumberofreadcyclesand
wisthenumberofwritecyclesincludedintheclockperiodnumber.Recalling
thateitherareadorwritecyclerequiresfourclockperiods,atimingnumber
as18(3/1)relatesto12clockperiodsforthethreereadcycles,plus4clock
periodsfortheonewritecycle,plus2cyclesrequiredforsomeinternal
functionsoftheprocessor.
üNOTEÇ
Thenumberofperiodsincludesinstructionfetchandallapplicableoperand
fetchesandstores.
üD.2EFFECTIVEADDRESSOPERANDCALCULATIONTIMINGÇ
TableD-1liststhenumberofclockperiodsrequiredtocomputean
instruction'seffectiveaddress.Itincludesfetchingofanyextension
words,theaddresscomputation,andfetchingofthememoryoperand.The
numberofbusreadandwritecyclesisshowninparenthesis(r/w).Note
therearenowritecyclesinvolvedinprocessingtheeffectiveaddress.
üTableD-1.EffectiveAddressCalculationTimingÇ
+-----------------------------------------------------------+---------+--------+
|AddressingMode|Byte/Word|Long|
+------------+----------------------------------------------+---------+--------+
||Register|||
|Dn|DataRegisterDirect|0(0/0)|0(0/0)|
|An|AddressRegisterDirect|0(0/0)|0(0/0)|
+------------+----------------------------------------------+---------+--------+
||Memory|||
|An@|AddressRegisterIndirect|4(1/0)|8(2/0)|
|An@+|AddressRegisterIndirectwithPostincrement|4(1/0)|8(2/0)|
+------------+----------------------------------------------+------------------+
|An@-|AddressRegisterIndirectwithPredecrement|6(1/0)|10(2/0)|
|An@(d)|AddressRegisterIndirectwithDisplacement|8(2/0)|12(3/0)|
+------------+----------------------------------------------+------------------+
|An@(d,ix)*|AddressRegisterIndirectwithIndex|10(2/0)|14(3/0)|
|xxx.W|AbsoluteShort|8(2/0)|12(3/0)|
+------------+----------------------------------------------+------------------+
|xxx.L|AbsoluteLong|12(3/0)|16(4/0)|
|PC@(d)|ProgrammCounterwithDisplacement|8(2/0)|12(3/0)|
+------------+----------------------------------------------+------------------+
|PC@(d,ix)*|ProgrammCounterwithIndex|10(2/0)|14(3/0)|
|#xxx|Immediate|4(1/0)|8(2/0)|
+------------+----------------------------------------------+------------------+
*Thesizeoftheindexregister(ix)doesnoraffectexecutiontime
üD.3MOVEINSTRUCTIONCLOCKPERIODSÇ
TablesD-2andD-3indicatethenumberofclockperiodsforthemoveinstruc⑨
tion.Thisdataincludesinstructionfetch,operandreads,andoperandwrites.
Thenumberofbusreadandwritecyclesisshowninparenthesisas:(r/w).
üTABLED-2.MoveByteandWordInstructionClockPeriodsÇ
DnAnAn@An@+An@-An@(d)An@(d,ix)xxx.Wxxx.L
Dn4(1/0)4(1/0)8(1/1)8(1/1)8(1/1)12(2/1)14(2/1)12(2/1)16(3/1)
An4(1/0)4(1/0)8(1/1)8(1/1)8(1/1)12(2/1)14(2/1)12(2/1)16(3/1)
An@8(2/0)8(2/0)12(2/1)12(2/1)12/2/1)16(3/1)18(3/1)16(3/1)20(4/1)
An@+8(2/0)8(2/0)12(2/1)12(2/1)12(2/1)16(3/1)18(3/1)16(3/1)20(4/1)
An@-10(2/0)10(2/0)14(2/1)14(2/1)14(2/1)18(3/1)20(3/1)18(3/1)22(4/1)
An@(d)12(3/0)12(3/0)16(3/1)16(3/1)16(3/1)20(4/1)22(4/1)20(4/1)24(5/1)
An@(d,ix)14(3/0)14(3/0)18(3/1)18(3/1)18(3/1)22(4/1)24(4/1)22(4/1)26(5/1)
xxx.W12(3/0)12(3/0)16(3/1)16(3/1)16(3/1)20(4/1)22(4/1)20(4/1)24(5/1)
xxx.L16(4/0)16(4/0)20(4/1)20(4/1)20(4/1)24(5/1)26(5/1)24(5/1)28(6/1)
PC@(d)12(3/0)12(3/0)16(3/1)16(3/1)16(3/1)20(4/1)22(4/1)20(4/1)24(5/1)
PC@(d,ix)14(3/0)14(3/0)18(3/1)18(3/1)18(3/1)22(4/1)24(4/1)22(4/1)26(5/1)
#xxx8(2/0)8(2/0)12(2/1)12(2/1)12(2/1)16(3/1)18(3/1)16(3/1)20(4/1)
*Thesizeoftheindexregisterdoesnotaffectexecutiontime
üTABLED-2.MoveLongInstructionClockPeriodsÇ
DnAnAn@An@+An@-An@(d)An@(d,ix)xxx.Wxxx.L
Dn4(1/0)4(1/0)12(1/2)12(1/2)14(1/2)16(2/2)18(2/2)16(2/2)20(3/2)
An4(1/0)4(1/0)12(1/2)12(1/2)14(1/2)16(2/2)18(2/2)16(2/2)20(3/1)
An@12(3/0)12(3/0)20(3/2)20(3/2)20/3/2)24(4/2)26(4/2)24(4/2)28(5/2)
An@+12(3/0)12(3/0)20(3/2)20(3/2)20(3/2)24(4/2)26(4/2)24(4/2)28(5/2)
An@-14(3/0)14(3/0)22(3/2)22(3/2)22(3/2)26(4/2)28(4/2)26(4/2)30(5/2)
An@(d)16(4/0)16(4/0)24(4/2)24(4/2)24(4/2)28(5/2)30(5/2)28(5/2)32(6/2)
An@(d,ix)18(4/0)18(4/0)26(4/2)26(4/2)26(4/2)30(5/2)32(5/2)30(5/2)34(6/2)
xxx.W16(4/0)16(4/0)24(4/2)24(4/2)24(4/2)28(5/2)30(5/2)28(5/2)32(6/2)
xxx.L20(5/0)20(5/0)28(5/2)28(5/2)28(5/2)32(6/2)34(6/2)32(6/2)36(7/2)
PC@(d)16(4/0)16(4/0)24(4/2)24(4/2)24(4/2)28(5/2)30(5/2)28(5/2)32(6/2)
PC@(d,ix)18(4/0)18(4/0)26(4/2)26(4/2)26(4/2)30(5/2)32(5/2)30(5/2)34(6/2)
#xxx12(3/0)12(3/0)20(3/2)20(3/2)20(3/2)24(4/2)26(4/2)24(4/2)28(5/2)
*Thesizeoftheindexregisterdoesnotaffectexecutiontime
üD.4STANDARDINSTRUCTIONCLOCKPERIODSÇ
ThenumberofclockperiodsshowninTableD-4indicatesthetimerequiuredtoü
Çperformtheoperations,storetheresults,andreadthenextinstruction.The
numberofbusreadandwritecyclesisshowninparenthesisas:(r/w).Thenumber
ofclockperiodsandthenumberofreadandwritecyclesmustbeaddedtothose
oftheeffectiveaddresscalculationwhereindicated.
InTableD-4,theheadingshavethefollowingmeanings:An=addressregister
operand,Dn=dataregisteroperand,ea=andoperandspecifiedbyaneffective
address,andM=memoryeffectiveaddressoperand.
üTableD-4.StandardInstructionClockPeriodsÇ
+-------------+-----------+------------+------------+-----------+
|Instruction|Size|op<ea>,An|op<ea>,Dn|opDn,<M>|
+-------------+-----------+------------+------------+-----------+
||Byte,Word|8(1/0)+|4(1/0)+|8(1/1)+|
|ADD+-----------+------------+------------+-----------+
||Long|6(1/0)+**|6(1/0)+**|12(1/2)+|
+-------------+-----------+------------+------------+-----------+
||Byte,Word|-|4(1/0)+|8(1/1)+|
|AND+-----------+------------+------------+-----------+
||Long|-|6(1/0)+**|12(1/2)+|
+-------------+-----------+------------+------------+-----------+
||Byte,Word|6(1/0)+|4(1/0)+|-|
|CMP+-----------+------------+------------+-----------+
||Long|6(1/0)+|6(1/0)+|-|
+-------------+-----------+------------+------------+-----------+
|DIVS|-|-|158(1/0)+*|-|
+-------------+-----------+------------+------------+-----------+
|DIVU|-|-|140(1/0)+*|-|
+-------------+-----------+------------+------------+-----------+
||Byte,Word|-|4(1/0)***|8(1/1)+|
|EOR+-----------+------------+------------+-----------+
||Long|-|8(1/0)***|12(1/2)+|
+-------------+-----------+------------+------------+-----------+
|MULS|-|-|70(1/0)+*|-|
+-------------+-----------+------------+------------+-----------+
|MULU|-|-|70(1/0)+*|-|
+-------------+-----------+------------+------------+-----------+
||Byte,Word|-|4(1/0)+|8(1/1)+|
|OR+-----------+------------+------------+-----------+
||Long|-|6(1/0)+**|12(1/1)+|
+-------------+-----------+------------+------------+-----------+
||Byte,Word|8(1/0)+|4(1/0)+|8(1/1)+|
|SUB+-----------+------------+------------+-----------+
||Long|6(1/0)+**|6(1/0)+**|12(1/2)+|
+-------------+-----------+------------+------------+-----------+
+addeffectiveaddresscalculationtime
*indicatesmaximumvalue
**totalof8clockperiodsforinstructioniftheaddressisregisterdirect
***onlyavailableeffectiveaddressmodeisdataregisterdirect
üD.5IMMEDIATEINTRUCTIONCLOCKPERIODSÇ
ThenumberofclockperiodsshowninTableD-5includesthetimetofetch
immediateoperands,performtheoperations,storetheresults,andreadthenext
operation.Thenumberofbusreadandwritecyclesisshowninparenthesis
as:(r/w).Thenumberofclockperiodsandthenumberofreadandwritecycles
mustbeaddedtothoseoftheeffectiveaddresscalculationwhereindicated.
InTableD-5,theheadingshavethefollowingmeanings:#=immediateoperandAn
=addressregisteroperand,Dn=dataregisteroperand,andM=memoryeffective
addressoperand.
üTableD-5.ImmediateIntructionClockPeriodsÇ
+-------------+-----------+------------+------------+-----------+
|Instruction|Size|op#,Dn|op#,An|op#,M|
+-------------+-----------+------------+------------+-----------+
||Byte,Word|8(2/0)|-|12(2/1)+|
|ADDI+-----------+------------+------------+-----------+
||Long|16(3/0)|-|20(3/2)+|
+-------------+-----------+------------+------------+-----------+
||Byte,Word|4(1/0)|8(1/0)*|8(1/1)+|
|ADDQ+-----------+------------+------------+-----------+
||Long|8(1/0)|8(1/0)|12(1/2)+|
+-------------+-----------+------------+------------+-----------+
||Byte,Word|8(2/0)|-|12(2/1)+|
|ANDI+-----------+------------+------------+-----------+
||Long|16(3/0)|-|20(3/2)+|
+-------------+-----------+------------+------------+-----------+
||Byte,Word|8(2/0)|8(2/0)|8(2/0)+|
|CMPI+-----------+------------+------------+-----------+
||Long|14(2/0)|14(3/0)|12(3/0)+|
+-------------+-----------+------------+------------+-----------+
||Byte,Word|8(2/0)|-|12(2/1)+|
|EORI+-----------+------------+------------+-----------+
||Long|16(3/0)|-|20(3/2)+|
+-------------+-----------+------------+------------+-----------+
|MOVEQ|Long|4(1/0)|-|-|
+-------------+-----------+------------+------------+-----------+
||Byte,Word|8(2/0)|-|12(2/1)+|
|ORI+-----------+------------+------------+-----------+
||Long|16(3/0)|-|20(3/2)+|
+-------------+-----------+------------+------------+-----------+
||Byte,Word|8(2/0)|-|12(2/1)+|
|SUBI+-----------+------------+------------+-----------+
||Long|16(3/0)|-|20(3/2)+|
+-------------+-----------+------------+------------+-----------+
||Byte,Word|4(1/0)|8(1/0)*|8(1/1)+|
|SUBQ+-----------+------------+------------+-----------+
||Long|8(1/0)|8(1/0)|12(1/2)+|
+-------------+-----------+------------+------------+-----------+
+addeffectiveaddresscalculationtime
*wordonly
üD.6SINGLEOPERANDINSTRUCTIONCLOCKPERIODSÇ
TableD-6indicatesthenumberofclockperiodsforthesingleoperand
instruction.Thenumberofbusreadandwritecyclesisshowninparenthesis
as:(r/w).Thenumberofclockperiodsandthenumberofreadandwritecycles
mustbeaddedtothoseoftheeffectiveaddresscalculationwhereindicated
üTableD-6.SingleOperandInstructionClockPeriodsÇ
+-------------+-----------+------------+------------+
|Instruction|Size|Register|Memory|
+-------------+-----------+------------+------------+
||Byte,Word|4(1/0)|8(1/1)+|
|CLR+-----------+------------+------------+
||Long|6(1/0)|12(1/2)+|
+-------------+-----------+------------+------------+
|NBCD|Byte|6(1/0)|8(1/1)+|
+-------------+-----------+------------+------------+
||Byte,Word|4(1/0)|8(1/2)+|
|NEG+-----------+------------+------------+
||Long|6(1/0)|12(1/2)+|
+-------------+-----------+------------+------------+
||Byte,Word|4(1/0)|8(1/1)+|
|NEGX+-----------+------------+------------+
||Long|6(1/0)|12(1/2)+|
+-------------+-----------+------------+------------+
||Byte,Word|4(1/0)|8(1/1)+|
|NOT+-----------+------------+------------+
||Long|6(1/0)|12(1/2)+|
+-------------+-----------+------------+------------+
||Byte,False|4(1/0)|8(1/1)+|
|Scc+-----------+------------+------------+
||Byte,True|6(1/0)|8(1/1)+|
+-------------+-----------+------------+------------+
|TAS|Byte|4(1/0)|10(1/1)+|
+-------------+-----------+------------+------------+
||Byte,Word|4(1/0)|4(1/0)+|
|TST+-----------+------------+------------+
||Long|4(1/0)|4(1/0)+|
+-------------+-----------+------------+------------+
+addeffectiveaddresscalculationtime
üD.7SHIFTANDROTATEINSTRUCTIONCLOCKPERIODSÇ
TableD-7indicatesthenumberofclockperiodsfortheshiftandrotate
instructions.Thenumberofbusreadandwritecyclesisshowninparenthesis
as:(r/w).Thenumberofclockperiodsandthenumberofreadandwritecycles
mustbeaddedtothoseoftheeffectiveaddresscalculationwhereindicated
üTableD-7.ShiftandRotateInstructionClockPeriodsÇ
+-------------+-----------+------------+------------+
|Instruction|Size|Register|Memory|
+-------------+-----------+------------+------------+
||Byte,Word|6+2n(1/0)|8(1/1)+|
|ASR,ASL+-----------+------------+------------+
||Long|8+2n(1/0)|-|
+-------------+-----------+------------+------------+
||Byte,Word|6+2n(1/0)|8(1/1)+|
|LSR,LSL+-----------+------------+------------+
||Long|8+2n(1/0)|-|
+-------------+-----------+------------+------------+
||Byte,Word|6+2n(1/0)|8(1/1)+|
|ROR,ROL+-----------+------------+------------+
||Long|8+2n(1/0)|-|
+-------------+-----------+------------+------------+
||Byte,Word|6+2n(1/0)|8(1/1)+|
|ROXR,ROXL+-----------+------------+------------+
||Long|8+2n(1/0)|-|
+-------------+-----------+------------+------------+
+addeffectiveaddresscalculationtime
nistheshiftcount
üD.8BITMANIPULATIONINSTRUCTIONCLOCKPERIODSÇ
TableD-8indicatesthenumberofclockperiodsforthebitmanipulation
instructions.Thenumberofbusreadandwritecyclesisshowninparenthesis
as:(r/w).Thenumberofclockperiodsandthenumberofreadandwritecycles
mustbeaddedtothoseoftheeffectiveaddresscalculationwhereindicated
üTableD-8.BitManipulationInstructionClockPeriodsÇ
+-------------+-----------+-------------------------+-------------------------+
|||Dynamic|Static|
|Instruction|Size+------------+------------+------------+------------+
|||Register|Memory|Register|Memory|
+-------------+-----------+------------+------------+------------+------------+
||Byte|-|8(1/1)+|-|12(2/1)+|
|BCHG+-----------+------------+------------+------------+------------+
||Long|8(1/0)*|-|12(2/0)*|-|
+-------------+-----------+------------+------------+------------+------------+
||Byte|-|8(1/1)+|-|12(2/1)+|
|BCLR+-----------+------------+------------+------------+------------+
||Long|10(1/0)*|-|14(2/0)*|-|
+-------------+-----------+------------+------------+------------+------------+
||Byte|-|8(1/1)+|-|12(2/1)+|
|BSET+-----------+------------+------------+------------+------------+
||Long|8(1/0)*|-|12(2/0)|-|
+-------------+-----------+------------+------------+------------+------------+
||Byte|-|8(1/1)+|-|12(2/1)+|
|BTST+-----------+------------+------------+------------+------------+
||Long|6(1/0)*|-|10(2/0)|-|
+-------------+-----------+------------+------------+------------+------------+
+addeffectiveaddresscalculationtime
*indicatesmaximumvalue
üD.9CONDITIONALINSTRUCTIONCLOCKPERIODSÇ
TableD-9indicatesthenumberofclockperiodsfortheconditionalinstruc⑨
tions.Thenumberofbusreadandwritecyclesisshowninparenthesisas:(r/w).
Thenumberofclockperiodsandthenumberofreadandwritecyclesmustbe
addedtothoseoftheeffectiveaddresscalculationwhereindicated.
üTableD-9.ConditionalInstructionClockPeriodsÇ
+-------------+------------+-------------------------+-------------------------+
|||TraporBranch|TraporBranch|
|Instruction|Displacement|||
|||Taken|notTaken|
+-------------+------------+-------------------------+-------------------------+
||Byte|10(2/0)|8(1/0)|
|Bcc+------------+-------------------------+-------------------------+
||Word|10(2/0)|12(2/0)|
+-------------+------------+-------------------------+-------------------------+
||Byte|10(2/0)|-|
|BRA+------------+-------------------------+-------------------------+
||Word|10(2/0)|-|
+-------------+------------+-------------------------+-------------------------+
||Byte|18(2/2)|-|
|BSR+------------+-------------------------+-------------------------+
||Word|18(2/2)|-|
+-------------+------------+-------------------------+-------------------------+
||cctrue|-|12(2/0)|
|DBcc+------------+-------------------------+-------------------------+
||ccfalse|10(2/0)|14(3/0)|
+-------------+------------+-------------------------+-------------------------+
|CHK|-|40(5/3)+*|8(1/0)|
+-------------+------------+-------------------------+-------------------------+
|TRAP|-|34(4/3)|-|
+-------------+------------+-------------------------+-------------------------+
|TRAPV|-|34(5/3)|4(1/0)|
+-------------+------------+-------------------------+-------------------------+
+addeffectiveaddresscalculationtime
*indicatesmaximumvalue
üD.10JMP,JSR,LEA,PEA,MOVEMINTRUCTIONCLOCKPERIODSÇ
TableD-10indicatesthenumberofclockperiodsrequiredforthejump,jumpto
subroutine,loadeffectiveaddress,pusheffectiveaddress,andmovemultiple
registerinstructions.Thenumberofbusreadandwritecyclesisshowmin
parenthesisas:(r/w).
üTableD-10.JMP,JSR,LEA,PEA,MOVEMInstructionClockPeriodsÇ
InstSzAn@An@+An@-An@(d)An@(d,ix)xxx.Wxxx.LPC@(d)PC@(d,ix)
---------------+-------+-------+-------+-------+-------+-------+-------+--------
JMP-8(2/0)|-|-|10(2/0)|14(2/0)|10(2/0)|12(3/0)|10(2/0)|14(3/0)*
---------------+-------+-------+-------+-------+-------+-------+-------+--------
JSR-16(2/2)|-|-|18(2/2)|22(2/2)|18(2/2)|20(3/2)|18(2/2)|22(3/2)*
---------------+-------+-------+-------+-------+-------+-------+-------+--------
LEA-4(1/0)|-|-|8(2/0)|12(2/0)|8(2/0)|12(3/0)|8(2/0)|12(3/0)*
---------------+-------+-------+-------+-------+-------+-------+-------+--------
PEA-12(1/2)|-|-|16(2/2)|20(2/2)|16(2/2)|20(3/2)|16(2/2)|20(2/2)*
---------------+-------+-------+-------+-------+-------+-------+-------+--------
12+4n|12+4n|-|16+4n|18+4n|16+4n|20+4n|16+4n|18+4n*
W||||||||
MOVEM(3+n/0)|(3+n/0)|-|(4+n/0)|(4+n/0)|(4+n/0)|(5+n/0)|(4+n/0)|(4+n/0)
---------+-------+-------+-------+-------+-------+-------+-------+--------
M->R12+8n|12+8n|-|16+8n|18+8n|16+8n|20+8n|16+8n|18+8n*
L||||||||
(3+2n/0|(3+2n/0|-|(4+2n/0|(4+2n/0|(4+2n/0|(5+2n/0|(4+2n/0|(4+2n/0)
---------------+-------+-------+-------+-------+-------+-------+-------+--------
8+5n|-|8+5n|12+5n|14+5n|12+5n|16+5n|-|-
W||||||||
MOVEM(2/n)|-|(2/n)|(3/n)|(3/n)|(3/n)|(4/n)|-|-
---------+-------+-------+-------+-------+-------+-------+-------+--------
R->M8+10n|-|8+10n|12+10n|14+10n|12+10n|16+10n|-|-
L||||||||
(2/2n)|-|(2/2n)|(3/2n)|(3/2n)|(2/2n)|(4/2n)|-|-
---------------+-------+-------+-------+-------+-------+-------+-------+--------
nisthenumberofregisterstomove
*thesizeoftheindexregister(ix)doesnotaffecttheinstruction's
executiontime
*Thesizeoftheindexregisterdoesnotaffectexecutiontime
üD.11MULTI-PRECISIONINSTRUCTIONCLOCKPERIODSÇ
TableD-11indicatesthenumberofclockperiodsforthemulti-precision
instructions.thenumberofclockperiodsincludesthetimetofetchboth
operands,performtheoperations,storetheresults,andreadthenextinstruc⑨
tions.Thenumberofreadandwritecyclesisshowninparenthesisas:(r/w).
InTableD-11,theheadingshavethefollowingmeanings:Dn=dataregister
operandandM=memoryoperand.
+-------------+-----------+------------+------------+
|Instruction|Size|Register|Memory|
+-------------+-----------+------------+------------+
||Byte,Word|4(1/0)|18(3/1)|
|ADDX+-----------+------------+------------+
||Long|8(1/0)|30(5/2)|
+-------------+-----------+------------+------------+
||Byte,Word|-|12(3/0)|
|CMPM+-----------+------------+------------+
||Long|-|20(5/0)|
+-------------+-----------+------------+------------+
||Byte,Word|4(1/0)|18(3/1)|
|SUBX+-----------+------------+------------+
||Long|8(1/0)|30(5/3)|
+-------------+-----------+------------+------------+
|ABCD|Byte|6(1/0)|18(3/1)|
+-------------+-----------+------------+------------+
|SBCD|Byte|6(1/0)|18(3/1)|
+-------------+-----------+------------+------------+
üD.12MISCELLANEOUSINSTRUCTIONCLOCKPERIODSÇ
TablesD-12andD-13indicatethenumberofclockperiodsforthemiscellaneous
instructionslisted.Thenumberofbusreadandwritecyclesisshownin
parenthesisas:(r/w).Thenumberofclockperiodsandthenumberofreadand
writecyclesmustbeaddedtothoseoftheeffectiveaddresscalculationwhere
indicated.
+--------------+----------+----------+---+--------------+----------+----------+
|Instruction|Register|Memory||Instruction|Register|Memory|
+--------------+----------+----------++--------------+----------+----------+
|ANDItoCCR|20(3/0)|-||MOVWfromUSP|4(1/0)|-|
|ANDItoSR|20(3/0)|-||NOP|4(1/0)|-|
|EORItoCCR|20(3/0)|-||ORItoCCR|20(3/0)|-|
|EORItoSR|20(3/0)|-||ORItoSR|20(3/0)|-|
|EXG|6(1/0)|-||RESET|132(1/0)|-|
|EXT|4(1/0)|-||RTE|20(5/0)|-|
|LINK|18(2/2)|-||RTR|20(5/0)|-|
|MOVEtoCCR|12(2/0)+|12(2/0)+||RTS|16(4/0)|-|
|MOVEtoSR|12(3/0)+|12(2/0)+||STOP|4(0/0)|-|
|MOVEfromSR|6(1/0)|8(1/1)+||SWAP|4(1/0)|-|
|MOVEtoUSP|4(1/0)|-||UNLK|12(3/0)|-|
+--------------+----------+----------+---+--------------+----------+----------+
+addeffectiveaddresscalculationtime
+--------------+------+--------------------+--------------------+
|Instruction|Size|Register->Memory|Memory->Register|
+--------------+------+--------------------+--------------------+
|MOVEP|Word|16(2/2)|16(4/0)|
||Byte|24(2/4)|24(6/0)|
+--------------+------+--------------------+--------------------+
üD.13EXCEPTIONPROCESSINGCLOCKPERIODSÇ
TableD-14indicatesthenumberofclockperiodsforexceptionprocessing.The
numberofclockperiodsincludedthetimeforallstacking,vectorfetch,and
thefetchofthefirstinstructionofthehandlerroutine.Thenumberofbus
readandwritecyclesisshowninparenthesisas:(r/w).
üTableD-14.ExceptionProcessingClockPeriodsÇ
+-----------------------------------+---------+
|Addresserror|50(4/7)|
+-----------------------------------+---------+
|Buserror|50(4/7)|
+-----------------------------------+---------+
|Interrupt|44(5/3)*|
+-----------------------------------+---------+
|IllegalInstruction|34(4/3)|
+-----------------------------------+---------+
|PriviledgedInstruction|34(4/3)|
+-----------------------------------+---------+
|Trace|34(4/3)|
+-----------------------------------+---------+
*theinterruptacknowledgebuscycleisassumedtotakefourexternal
clockperiods