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1990-12-11
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.HM A 1 1 1 1 1 1
.H 1 "Appendix for as2650 Frankenstein Assembler"
.H 2 "Pseudo Operations"
.H 3 "Standard Pseudo Operation Mnemonics"
.VL 40 5 1
.LI "End"
END
.LI "File Inclusion"
INCL
INCLUDE
.LI "If"
IF
.LI "Else"
ELSE
.LI "End If"
ENDI
.LI "Equate"
EQU
.LI "Set"
SET
.LI "Org"
ORG
.LI "Reserve Memory"
RES
RESERVE
RMB
.LI "Define Byte Data"
BYTE
DATA
DB
FCB
.LI "Define Word Data"
DW
FDB
WORD
.LI "Define String Data"
FCC
STRING
.LI "Define Character Set Translation"
CHARSET
.LI "Define Character Value"
CHARDEF
CHD
.LI "Use Character Translation"
CHARUSE
.LE
.H 3 "Machine Dependent Pseudo Operations"
.H 4 "Define Address Constant"
.DS I N
[Label] ACON expression [, expression] ...
.DE
The acon statement generates a two byte integer for each expression in the
expression list.
Each expression is limited in value from 0 to 32767, values outside this
range will result in an "expression exceeds available field width" error.
There can be up to 128 expressions on the line, within the line length limit.
The optional label is set to the address of the first expression.
.H 2 "Instructions"
.H 3 "Instruction List"
.TS H
;
l l l.
Opcode Syntax Selection Criteria
.sp
.TH
.sp
ADDA ',' REG expr
ADDA ',' REG '*' expr ',' REG ',' '+'
ADDA ',' REG '*' expr ',' REG ',' '-'
ADDA ',' REG '*' expr ',' REG
ADDA ',' REG '*' expr
ADDA ',' REG expr ',' REG ',' '+'
ADDA ',' REG expr ',' REG ',' '-'
ADDA ',' REG expr ',' REG
.sp
ADDI ',' REG expr
.sp
ADDR ',' REG '*' expr
ADDR ',' REG expr
.sp
ADDZ REG
.sp
ANDA ',' REG expr
ANDA ',' REG '*' expr ',' REG ',' '+'
ANDA ',' REG '*' expr ',' REG ',' '-'
ANDA ',' REG '*' expr ',' REG
ANDA ',' REG '*' expr
ANDA ',' REG expr ',' REG ',' '+'
ANDA ',' REG expr ',' REG ',' '-'
ANDA ',' REG expr ',' REG
.sp
ANDI ',' REG expr
.sp
ANDR ',' REG '*' expr
ANDR ',' REG expr
.sp
ANDZ REG REG1
ANDZ REG REG2
ANDZ REG REG3
.sp
BCFA ',' CONDITION '*' expr COND0
BCFA ',' CONDITION '*' expr COND1
BCFA ',' CONDITION '*' expr COND2
BCFA ',' CONDITION expr COND0
BCFA ',' CONDITION expr COND1
BCFA ',' CONDITION expr COND2
.sp
BCFR ',' CONDITION '*' expr COND0
BCFR ',' CONDITION '*' expr COND1
BCFR ',' CONDITION '*' expr COND2
BCFR ',' CONDITION expr COND0
BCFR ',' CONDITION expr COND1
BCFR ',' CONDITION expr COND2
.sp
BCTA ',' CONDITION '*' expr
BCTA ',' CONDITION expr
.sp
BCTR ',' CONDITION '*' expr
BCTR ',' CONDITION expr
.sp
BDRA ',' REG '*' expr
BDRA ',' REG expr
.sp
BDRR ',' REG '*' expr
BDRR ',' REG expr
.sp
BIRA ',' REG '*' expr
BIRA ',' REG expr
.sp
BIRR ',' REG '*' expr
BIRR ',' REG expr
.sp
BRNA ',' REG '*' expr
BRNA ',' REG expr
.sp
BRNR ',' REG '*' expr
BRNR ',' REG expr
.sp
BSFA ',' CONDITION '*' expr COND0
BSFA ',' CONDITION '*' expr COND1
BSFA ',' CONDITION '*' expr COND2
BSFA ',' CONDITION expr COND0
BSFA ',' CONDITION expr COND1
BSFA ',' CONDITION expr COND2
.sp
BSFR ',' CONDITION '*' expr COND0
BSFR ',' CONDITION '*' expr COND1
BSFR ',' CONDITION '*' expr COND2
BSFR ',' CONDITION expr COND0
BSFR ',' CONDITION expr COND1
BSFR ',' CONDITION expr COND2
.sp
BSNA ',' REG '*' expr
BSNA ',' REG expr
.sp
BSNR ',' REG '*' expr
BSNR ',' REG expr
.sp
BSTA ',' CONDITION '*' expr
BSTA ',' CONDITION expr
.sp
BSTR ',' CONDITION '*' expr
BSTR ',' CONDITION expr
.sp
BSXA '*' expr ',' REG REG3
BSXA expr ',' REG REG3
.sp
BXA '*' expr ',' REG REG3
BXA expr ',' REG REG3
.sp
COMA ',' REG expr
COMA ',' REG '*' expr ',' REG ',' '+'
COMA ',' REG '*' expr ',' REG ',' '-'
COMA ',' REG '*' expr ',' REG
COMA ',' REG '*' expr
COMA ',' REG expr ',' REG ',' '+'
COMA ',' REG expr ',' REG ',' '-'
COMA ',' REG expr ',' REG
.sp
COMI ',' REG expr
.sp
COMR ',' REG '*' expr
COMR ',' REG expr
.sp
COMZ REG
.sp
CPSL expr
.sp
CPSU expr
.sp
DAR ',' REG
.sp
EORA ',' REG expr
EORA ',' REG '*' expr ',' REG ',' '+'
EORA ',' REG '*' expr ',' REG ',' '-'
EORA ',' REG '*' expr ',' REG
EORA ',' REG '*' expr
EORA ',' REG expr ',' REG ',' '+'
EORA ',' REG expr ',' REG ',' '-'
EORA ',' REG expr ',' REG
.sp
EORI ',' REG expr
.sp
EORR ',' REG '*' expr
EORR ',' REG expr
.sp
EORZ REG
.sp
HALT
.sp
IORA ',' REG expr
IORA ',' REG '*' expr ',' REG ',' '+'
IORA ',' REG '*' expr ',' REG ',' '-'
IORA ',' REG '*' expr ',' REG
IORA ',' REG '*' expr
IORA ',' REG expr ',' REG ',' '+'
IORA ',' REG expr ',' REG ',' '-'
IORA ',' REG expr ',' REG
.sp
IORI ',' REG expr
.sp
IORR ',' REG '*' expr
IORR ',' REG expr
.sp
IORZ REG
.sp
LODA ',' REG expr
LODA ',' REG '*' expr ',' REG ',' '+'
LODA ',' REG '*' expr ',' REG ',' '-'
LODA ',' REG '*' expr ',' REG
LODA ',' REG '*' expr
LODA ',' REG expr ',' REG ',' '+'
LODA ',' REG expr ',' REG ',' '-'
LODA ',' REG expr ',' REG
.sp
LODI ',' REG expr
.sp
LODR ',' REG '*' expr
LODR ',' REG expr
.sp
LODZ REG REG0
LODZ REG REG1
LODZ REG REG2
LODZ REG REG3
.sp
LPSL
.sp
LPSU
.sp
NOP
.sp
PPSL expr
.sp
PPSU expr
.sp
REDC ',' REG
.sp
REDD ',' REG
.sp
REDE ',' REG expr
.sp
RETC ',' CONDITION
.sp
RETE ',' CONDITION
.sp
RRL ',' REG
.sp
RRR ',' REG
.sp
SPSL
.sp
SPSU
.sp
STRA ',' REG expr
STRA ',' REG '*' expr ',' REG ',' '+'
STRA ',' REG '*' expr ',' REG ',' '-'
STRA ',' REG '*' expr ',' REG
STRA ',' REG '*' expr
STRA ',' REG expr ',' REG ',' '+'
STRA ',' REG expr ',' REG ',' '-'
STRA ',' REG expr ',' REG
.sp
STRR ',' REG '*' expr
STRR ',' REG expr
.sp
STRZ REG REG1
STRZ REG REG2
STRZ REG REG3
.sp
SUBA ',' REG expr
SUBA ',' REG '*' expr ',' REG ',' '+'
SUBA ',' REG '*' expr ',' REG ',' '-'
SUBA ',' REG '*' expr ',' REG
SUBA ',' REG '*' expr
SUBA ',' REG expr ',' REG ',' '+'
SUBA ',' REG expr ',' REG ',' '-'
SUBA ',' REG expr ',' REG
.sp
SUBI ',' REG expr
.sp
SUBR ',' REG '*' expr
SUBR ',' REG expr
.sp
SUBZ REG
.sp
TMI ',' REG expr
.sp
TPSL expr
.sp
TPSU expr
.sp
WRTC ',' REG
.sp
WRTD ',' REG
.sp
WRTE ',' REG expr
.sp
ZBRR '*' expr
ZBRR expr
.sp
ZBSR '*' expr
ZBSR expr
.TE
.H 3 "Register and Condition Reserved Symbols"
The REG and CONDITION fields in instructions are restricted to only
the values available as reserved symbols.
These are r0 - r3, or R0 - R3 for registers, and plus, PLUS, minus, MINUS,
zero, ZERO, gt, GT, lt, LT, eq, EQ, un, UN, always, and ALWAYS for
conditions.
.H 3 "Destination Register for Indexed Addressing"
If the destination register, the one adjacent to the opcode, is not R0 when
one of the absolute indexed addressing modes is used, an error is issued.
.H 3 "Selection Criteria Keywords"
.VL 10 5
.LI "REG0 REG1 REG2 REG3"
.SP
Some instructions are restricted to a subset of the registers.
Only those instructions with the specified registers are valid.
.LI "COND0 COND1 COND2 COND3"
.SP
Some instructions are restricted to a subset of the conditions.
Only those instructions with the specified conditions are valid.
.VL 10 0 1
.LI "COND0"
EQ, or ZERO
.LI "COND1
GT, or PLUS
.LI "COND2"
LT, or MINUS
.LI "COND3"
ALWAYS, or UN
.LE
.LE
.H 3 "Apostrophes"
The apostrophes in the syntax field are a notation used for the
parser generator and are not put in the assembler source statement.
.H 2 "Notes"
.H 3 "Location Counter"
The Dollar Sign is used as the location counter symbol in this assembler.
.H 3 "Memory Addressing Error Messages"
.VL 5 0
.LI "ERROR - expression exceeds available field width"
.SP
This message occurs when :
.DL
.LI
The absolute branch address is to an invalid address, one greater than
32767.
.LI
The absolute or relative address was not in the present memory page.
.LI
The relative offset was outside the range that can be represented in 7 bits.
.LE
.LI "ERROR - instruction crosses page boundary"
.SP
The first and last bytes of an instruction are on different sides of an 8k
page.
.LI "WARNING - Page Boundary"
.SP
The first byte of an instruction is on a 8k page boundry.
.H 3 "Page Wraparound for Relative Addressing"
The wraparound of an effective address, where a relative address from an
instruction near a page boundary accesses memory at the other side of the
page, is not supported in this assembler and will result in one or more
error messages.
.P
This does not apply to the ZBRR and ZBSR instructions.
Memory destinations for these can range from 0 to $3f and $1fc0 to $1fff.
.H 3 "Relational Operators"
The relational operator keywords GT, LT, and EQ are not available.
The '<', '>', and '==' special character representations must be used.
.H 3 "Reserved Symbols"
.H 4 "Machine Dependent Reserved Symbols"
ALWAYS
AND
DEFINED
EQ
GE
GT
HIGH
LE
LOW
LT
MINUS
MOD
NE
NOT
OR
PLUS
R0
R1
R2
R3
SHL
SHR
UN
XOR
ZERO
always
and
defined
eq
ge
gt
high
le
low
lt
minus
mod
ne
not
or
plus
r0
r1
r2
r3
shl
shr
un
xor
zero
.TC 1 1 7