Computer Installation Guide - Dragon Clan Series

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Text File | 1996-09-23 | 23.5 KB | 619 lines

Program 5X86.EXE Author Peter N Moss E-Mail Address pmoss@yoda.alt.za Version C2, 12 May 1996. Source code: Source code is not included. Compiled with Turbo Pascal V5.5 and TASM V1.1 Files: 5X86xx.ZIP The combined zipped distribution package 5X86.EXE The program file CX5X86.EXE Device driver for cache 5X86.REG Registration form 5X86.DOC This file The program: 5X86.EXE What it is not: A magic wand. *********************************************************************** The program is a tool that allows the user to enable the Cyrix 5X86 register bits. It can not make any feature work, only enable it. *********************************************************************** For use with DOS, Windows, Windows 95 and OS/2. The program detects the presence of a 5x86 processor and will not run if a Cyrix/IBM 5x86 is not found. 5x86.EXE will report and enable the modification of the performance control registers of the Cyrix 5x86 (TM) processor. Access to register bits marked reserved (*) is not supported other than to report status if in some cases non zero. See Undocumented commands. Usage: 5x86 <[/H|?] [/Q]> </BTB_EN=[on|off] /LOOP_EN=[on|off] /LSSER=[on|off] /RSTK_EN=[on|off] /BWRT=[on|off] /WT1=[on|off] /LINBRST=[on|off] /MEM_BYP=[on|off] /DTE_EN=[on|off] /FP_FAST=[on|off]> <[/ICD|/CWT|/CWB]> <[/T]> Where BTB_EN Branch prediction LOOP_EN Loop (Prefetch buffer) LSSER Load store serialise, enable reorder RSTK_EN Return stack BWRT Burst write cycle 4 dwords on cache line replacement. WT1 Write through region one (640kb..1Mb). LINBRST Linear burst mode. MEM_BYP Memory read bypassing DTE_EN Directory table cache FP_FAST Fast NPU exception reporting ICD CPU Internal cache disable CWT CPU cache enable, write through mode CWB CPU cache enable, write back mode Q = Program version H,? = Help T = Status of PCR0 register E = (Reserved) Debug report. Status of PCR0, CCR1..4 and CR0 Note that T may be combined with register bit settings and will report status after the register has been set by reading the register. Thus giving confirmation that the register has been set correctly ie 5x86 /LSSER=on /BTB_EN=on /RTS=off /t /E is included for debugging and expansion. The report is more than 25 lines so it would be advisable to use this with either a DOS pipe to more (| more) or redirection to a file (> filename). It is is not part of the program and is not expected to continue beyond its current use. Note CR0 NW bit cache status will always report write through mode regardless of the actual operating mode. This has been changed and now reports status 1 or 0. On = enable, 1; Off = disable, 0. On and off are valid and all other values are treated as a error. The first three characters only need be entered. LIN=on is the same as LINBRST=on. Less than three characters of the register bit name will cause an error. The cache enable/disable parameters are only valid for the CPU at level 0. DOS operates at level 0 (ring 0) if EMM386 is not loaded. No checking or testing is done for ring 0 operation. The report of CR0 will be incorrect for cache status as the NW bit does not reflect cache status. This is a currently known fault and will be corrected in a future version. It is only reported using the /e switch which is for debugging purposes only. Upper case or lower case characters may be used. The order of register input is not important. H, ? or Q will terminate any other command line parameters. No spaces can be placed between the register, equal sign and action, ie. "BTB = on" is invalid as a space is a valid separator. BTB=on is the correct form. T may be placed anywhere on the command line. Command line input may use any legal DOS separator, space tab / ; etc. ****************************************************************** [Undocumented commands added to version B9,C2] /CPUID=[on|off] on = enable the CPUID command. /SMAC=[on|off] /MMAC=[on|off] /USE_SMI=[on|off] on = enable SMM pins /IORT=[on|off] on = 16 clks, off = 0 clks /AISP=[on|off] on = all instructions stalled to serialise pipeline /RLML=[on|off] on = reorder locked misalighned loads ******************************************************************* Errorlevel: 5 = No Cyrix 5x86. 1 = Command line entry error 0 = Normal termination. The Cyrix 5x86 CPU registers: Full details of the register address and access requirements can be found in the Cyrix 5x86 (TM) processor data book #94192-00. -oo- Register: Performance control register 0 The following bits of this register perform various functions detailed with the register bit name. Register PRC0 Index 20h Access to this register is via I/O ports 22h (Index) and 23h (Data) and the MAP_EN bits of the CCR3 register. Bit map: ---------------------------------------------------------------- 7 6 5 4 3 2 1 0 ---------------------------------------------------------------- |LSSER| Res4| Res3| Res2| Res1| LOOP_EN| BTB_EN| RSTK_EN| ---------------------------------------------------------------- Bit Name Function 7 LSSER 1 = Load store serialise enable (Reorder disable) 6 BTBT Res4, BTB Test register 5 Res3 Reserved 4 RLML Res2, Reordering of locked misalighned loads 3 AISP Res1, All instructions stalled to serialise pipeline 2 LOOP_EN Loop enable 1 BTB_EN Branch target buffer enable 0 RSTK_EN Return stack enable RSTK_EN: 1 = The return stack is enabled and RET instructions will speculatively execute the code following the associated CALL to improve performance. BTB_EN: 1 = Branch target buffer enable. Branch prediction occurs. LOOP_EN: 1 = The CPU will not flush the prefetch buffer if the destination jump is already in the prefetch buffer eliminating the need for a read from the cache. LSSER: 1 = All memory reads and writes will occur in execution order. Reordering disabled. LSSER should be set to ensure that memory mapped I/O devices operating outside of the address range 640k..1M will operate correctly. Memory accesses in the range 640k..1M will always be issued in execution order. -oo- Register: Configuration control register 2 The following bits of this register perform various functions detailed with the register bit name. Register CCR2 Index C2h Bit map: ---------------------------------------------------------------- 7 6 5 4 3 2 1 0 ---------------------------------------------------------------- |USE_SUSP| BWRT | Res2 | WT1 |SUSP_HALT|LOCK_NW|USE_WBAK| Res1 | ---------------------------------------------------------------- Bit Name Function 7 USE_SUSP 1 = Enable suspend pins 6 BWRT 1 = Enable use of 16 byte write back cycles 5 Res2 Reserved 4 WT1 1 = Write through region 1 (640k..1M) 3 SUSP_HALT 1 = CPU enters suspend mode after HALT instruction 2 LOCK_NW 1 = Prohibit change of state of NW bit of CR0 1 USE_WBAK 1 = Enable cache write back pins 0 Res1 Reserved USE_WBAK: Enable INVAL and WM_RST input pins, and CACHE# and HITM# output pins. Must be set prior to enabling NW bit of CR0. WT1: Forces all writes to the address region between 640k and 1M that hit in the on-chip cache to be issued on the external bus. BWRT: Enable use of 16 byte write back cycles. Set only if system logic supports. -oo- Register: Configuration control register 3 The following bits of this register perform various functions detailed with the register bit name. Register CCR3 Index C3h Bit map: ------------------------------------------------------------------- 7 6 5 4 3 2 1 0 ------------------------------------------------------------------- |MAP_EN3|MAP_EN2|MAP_EN1|MAP_EN0 |SMM_MODE|LINBRST|NMI_EN|SMI_LOCK| ------------------------------------------------------------------- Bit Name Function 7 MAP_EN3 = 0 6 MAP_EN2 = 0 5 MAP_EN1 = 0 4 MAP_EN0 1 = All configuration registers are available 3 SMM_MODE 1 = SL device compatible mode 2 LINBRST 1 = Linear address sequence is used 1 NMI_EN 1 = NMI is enabled during SMM 0 SMI_LOCK 1 = SMM register lock SMI_LOCK: Once set can only be cleared by asserting the RESET pin. LINBRST: Enable linear address sequence. 0 = 1 + 4 sequence, Intel compatible. -oo- Register: Configuration control register 4 The following bits of this register perform various functions detailed with the register bit name. Register: CCR4 Index E8h Bit map: ---------------------------------------------------------------- 7 6 5 4 3 2 1 0 ---------------------------------------------------------------- |CPUIDEN| Res | FP_FAST| DTE_EN| MEM_BYP| IORT2 | IORT1 | IORT0 | ---------------------------------------------------------------- Bit Name Function 7 *CPUIDEN 1 = Enable CPUID instruction and EFlags bit 21 6 Res Reserved 5 *FP_FAST 1 = Fast FPU exception reporting 4 DTE_EN 1 = Enable directory table entry cache 3 MEM_BYP 1 = Memory read bypassing is enabled 2 IORT2 1 IORT1 0 IORT0 I/O recovery time 0..128 bus clocks 2^x * = Reserved function CPUIDEN: Step level 1 up only. No working sample reported. IORT: 0 = no clock delay ... 7h = 128 clock delay. -oo- Usage and optimisation: In setting the CPU please note the the results are very dependent on the correct setup of the CMOS parameters. Particular attention should be placed on the L1, L2 cache settings as well as memory read and write wait states. It is suggested that these setting be optimised first before attempting to "tune" the CPU performance control register. There maybe some interaction of the CMOS settings and CPU settings requiring iteration to find the most suitable. The Cyrix 5x86 as other Cyrix processors requires that the motherboard and BIOS support the on chip cache (L1) as well as other signal pins. For this reason the motherboard jumpers and CMOS must be set correctly. Before starting it is a good idea to run 5x86 /e to see what register bits have been set by the BIOS. ------------------------------------------------------------------ Internal cache enable option ------------------------------------------------------------------ The cache is enabled/disabled by setting CPU CR0 register which can only be accessed (written) when the CPU is operating at CPL 0 or ring 0. This feature is not to be used in protected mode (32 bit programs) such as Windows, Unix etc. No checking is done at present although possible. The user is expected to read and understand this statement and not foolishly attempt to modify the cache setting when operating the CPU at any other level than 0. The use of this feature is only included for those motherboards without Cyrix cache support as a test at present. Note running EMM386.EXE and similar memory managers places DOS at CPL 3 and you will not be able to change the setting of CR0. A clean DOS boot is absolutely essential to use ICD, CWT and CWB. CBW will enable the write back pins of the CPU and if these are not supported by the hardware, writeback mode can not be expected to work. CX5X86.EXE is included so that if it is required that the internal cache be manually enabled, this can be done in CONFIG.SYS. This device driver has no other purpose. See device driver, cx5x86.exe ------------------------------------------------------------------ Some problems have been noted with LSSER set to 0 the default when other functions (bits) have been enabled. Suggested BIOS default values are: CCR2 BWRT = 0 System logic must support CCR4 MEM_BYP = 1 DTE_EN = 1 FP_FAST = 0 IORT = 0 PCR0 RSTACK = 0 BTB = 0 LOOP = 0 LSSER = 1 for PCI memory mapped devices LSSER = 0 for systems without PCI These are a very good starting point. The parameters for use can be found by entering h or ? on the command line. When the optimum parameters have been found path\5x86 {parameters} may be placed in your autoexec.bat file with those parameters so that the PC is set on startup. As a guide for current revisions of 5x86 CPU enable the following registers if not enabled by the BIOS. Note BTB may not work for all operating systems and hardware. BTB_EN=on may cause problems with windows.... MEM_BYP=on safe setting DTE_EN=on safe setting FP_FAST=on safe setting WT1=on if writeback L1 is selected in CMOS USE_WBAK=on writeback mode only BWRT=on writeback mode only LSSER=on for PCI or if instability is noted. Registers that should be enabled by the BIOS Write through mode: MEM_BYP DTE_EN LSSER for PCI, see above Write back mode: USE_WBAK BWRT Some MBs will not operate with this setting WT1 MEM_BYP DTE_EN LSSER for PCI, see above It may be found that if the BIOS is Cyrix 5x86 aware that some of these registers are enabled. Notably MEM_BYP and DTE_EN, with USE_WBAK, WT1 and sometimes BWRT enabled if the cache is in writeback mode and burst writes have been enabled. If BWRT is enabled disable burst write in the CMOS and check again. It is a possible area for failure to operate. The only way to find out is to check with 5x86 /e and note any enabled registers. These settings were tested with IBM5x86-100 step 1, rev 3 and an Asustek SV2GX4-VL motherboard. BWRT or burst writes would not operate on this motherboard and required that CMOS setting for burst writes be disabled. OS/2: In startup.cmd start /c /dos /win [drive:\path\5x86 <parameters>] @exit This is untested and due to my total ignorance of OS/2 may contain errors Your manuals and documentation will be of use here, I will not. -oo- Optimisation: Part of my problem in writing documentation is the level to aim it at. I am sure that anyone can appreciate that it is really not possible to bring up to speed all users of the program. Microsoft even fails at that. The setting of the advanced features does require an understanding of at least some of the technicalities and processes. As does setting the CMOS. Use benchmarks such as Landmark SPEED V2, Norton SI and Ziff-Davis PCBENCH V9 for your testing as these have published results. Step 1: Start by setting the CMOS/BIOS such that maximum performance is obtained. This is to check that the system is functional to a proper level. The results obtained should be similar to any 486DX4 at the same speed. If this can not be obtained there is no purpose in feeding the system purple hearts by setting the advanced features in the hopes of making a sick child well. Note what if any features the BIOS enables. Step 2 may not be required. Step 2: Once all problems have been resolved, enable MEM_BYP and DTE_EN. If the system is a PCI bus enable LSSER. This is the basis of advanced features and the setting used by most BIOSs that support the Cx5x86. Performance should be at or close to the Cyrix published figures. If not go back to step 1. Step 3: Enable BTB and test at this point you may have to go back to step 1 as some settings may have been on the edge and will now fail. Pay attention to cache and dram settings. There are many owners who can not operate with branch prediction enabled, especially in windows or windows 95. The revision of your CPU may be a factor here and step 1 revision 3 up should be suitable but is not guaranteed. Step 4: Disable LSSER if it was enabled. Enable WT1. Some chipsets support linear burst mode and enabling this may be possible. These are listed. ALI M1489/87 OPTI 82C465MVB Picopower 868/818 668/618 768/718 Symphony 491/492 Wagner UMC 8880 Anyone having success with linear burst mode please report it fully. Step 5: You are on your own. Note that BTB is not guaranteed to work nor are steps 3 and 4 and there are many MBs+hardware combinations that will not run correctly. There is no magic formulae to sort yours out. It takes hard work and much testing. Keep notes of what has been done and the results. Even without BTB enabled this is one of the fastest 486 class processors available. It may be possible to run BTB enabled in DOS but not in Windows. Notes: I have assumed that the mother board supports writeback L1 cache. If you don't understand a particular aspect ask. A general query such as "my 5x86 will not work, what is wrong?" will be ignored as nobody has that much time. Give as much detail as will be required to answer the question. -oo- What are we dealing with? Memory management: Load-store reordering; that prioritises memory reads required by the integer unit over writes to external memory. Memory-read bypassing; that eliminates unnecessary memory reads by using valid data still in the execution unit. Branch prediction: The branch prediction target buffer (BTB) is used to store branch target addresses and branch prediction information. The target address of a RET instruction is dynamic rather than static and return addresses are cached in a return stack rather than the BTB. The return address is pushed on the return stack during a CALL instruction and popped during the corresponding RET instruction. -oo- The device driver : CX5X86.EXE USE: Only if the BIOS does not enable writeback mode and the system logic supports write back mode. Use in config.sys file as the FIRST device loaded. It is of no use at all if loaded after EMM386 and similar programs. It is intended for older motherboards that do not enable the cache. Write back mode may not be usable. See Usage and optimisation section. Usage: DEVICE=[Path\]CX5X86.EXE <[/CD|/WT|/WB]> Where /CD = Cache disable /WT = Cache enable in write through mode /WB = Cache enable in write back mode The syntax is exact; "/" must be used to proceed the option and only the options as given are valid. Upper or lower case characters may be used. Only one option (the first) on the config.sys "device = CX5x86" line is valid. EXAMPLE:Device=c:\util\cx5x86.exe /wt (Write through mode selected) Write through mode sets the CR0 register and LOCK_NW bit of CCR2. Write back mode sets the CR0 register and USE_WBAK and LOCK_NW bits of CCR2. This will cause problems if the hardware does not support the write back configuration. Your motherboard supplier or manufacture should be able to answer this question. If not are you buying from the right company? Cache disable sets CR0 bit CD. This device driver is not installed and thus takes up no memory after use. It can only be used with DOS, Windows and Windows 95. -oo- References: Cyrix 5x86(TM) Microprocessor Data Book IBM 5x86 BIOS Writers Guide CTCHIPZ configuration files Functionality, type and rights: 5x86.EXE is not crippled or contain nagware and relies completely on the honesty of the user. Use of the program is not free and the user is both legally and morally bound to registration and payment of the registration fee. 5x86xx.ZIP is shareware, all rights are reserved by Peter N Moss. Copyright: 5x86.EXE, Cx5x86.EXE and 5x86.DOC are copyright 1995 Peter N Moss. Disclaimer: No claim is made for the fitness of purpose of this software and no claim for damages of any nature will be accepted. The program is for use at entirely your own risk. Distribution: You may distribute the files only on condition that they are not altered and all files are included. No charge may be made for the software. The latest version can be found at ftp://compnt.cs.unp.ac.za/uploads/cyrix/5x86(Ver).zip. And at http://www.dfw.net/~sdw/cxstuff.html This site may lag the ftp site. Updates to registered users will only be sent via Internet e-mail without charge. Disk updates will be charged at the cost of materials and postage. Reports and support: Whilst reports of results or bugs are welcomed, it is not possible to support questions on how to setup or optimise any motherboards. You are referred to the dealer that sold the board and or CPU. Registered users can expect free update notification and as much help as can be given. Unregistered users can expect the same consideration as they have given the author. Thanks: Mr C Chan, Mr K J Wren, Mr J Stiel and Mr C D Regenberg for testing and feedback. Cyrix Corp for data. IBM for data. Dave Harter of Cyrix for help and information. Paul Naylor of Cyrix for data. Trademarks: Cyrix is a registered trademark of Cyrix Corp. Cx5x86 is a registered trademark of Cyrix Corp. IBM is a registered trademark of International Business Machines. Windows and windows 95 are registered trademarks of Microsoft Corp. Payment: You are offered 30 days free trial for evaluation only. After that period has expired and registration or payment has not taken place then the program must not be used. Personal/corporate cheques are the preferred method of payment. Payment of US$15.00 or the equivalent is such a small amount that anyone that uses the program continuously should contribute to the development of it. Approximately 500 man hours have gone into the development of the programs. It will also insure that the program continues to be developed. Your honesty will ensure the continued development of shareware programs, in particular 5x86. No shareware author wishes to donate his time and effort to people unwilling to appreciate that effort. Would you offer a similar amount of time or effort to the shareware author? If not, please pay the small amount requested. Not doing so is theft. For money order payment from outside of South Africa please add $4.00. Payment in cash, cheques (preferred) or money order may be made to: P N Moss P O Box 212144 Oribi Pietermaritzburg Rep of South Africa, 3205 When making payment please include your e-mail address if you have one and your return mail address. Registration form: 5X86.REG